Sharp ER-A850 (serv.man2) Service Manual ▷ View online
***
Hard Disk Controller
***
(Not used)
Name
Type
Pin No.
Description
SELHDK1n
O
108
HARD DISK SELECT2:
When Conner’s hard disk is
installed, this pin is used as
one of the chip select signal
decoding addresses 3F6 &
3F7. This pin is multiplexed
with POFF3n.
When Conner’s hard disk is
installed, this pin is used as
one of the chip select signal
decoding addresses 3F6 &
3F7. This pin is multiplexed
with POFF3n.
SELHDK0n
O
107
HARD DISK SELECT1:
active low to selection-board
hard disk drive. This pin is
multiplexed with POFF2n.
active low to selection-board
hard disk drive. This pin is
multiplexed with POFF2n.
***
Co-processor Interface
***
Name
Type
Pin No.
Description
NPERRn
I
34
NUMERICAL PROCESSOR
ERROR: active low. It
indicates that an unmasked
exception has occurred
during numeric instruction
execution when
co-processor interrupt is
enabled.
ERROR: active low. It
indicates that an unmasked
exception has occurred
during numeric instruction
execution when
co-processor interrupt is
enabled.
NPBSYn
I
35
NUMERICAL PROCESSOR
BUSY: active low. It is
connected directly to the
BUSY signal of the
co-processor.
BUSY: active low. It is
connected directly to the
BUSY signal of the
co-processor.
NPCSn
O
36
NUMERICAL PROCESSOR
CHIP SELECT: When low,
the co-processor is selected.
CHIP SELECT: When low,
the co-processor is selected.
BUSY286n
O
38
BUSY TO CPU: active low.
It is connected directly to the
BUSY input of the CPU.
It is connected directly to the
BUSY input of the CPU.
NPPREQ
I
37
NUMERICAL PROCESSOR
REQUEST: active high. It
indicates that the
co-processor is requesting
an operand transfer. This
pin is coming from the
PEREQ output of the
co-processor.
REQUEST: active high. It
indicates that the
co-processor is requesting
an operand transfer. This
pin is coming from the
PEREQ output of the
co-processor.
CPEREQ
O
39
CPU REQUEST: active
high. It indicates to the CPU
that the co-processor is
requesting an operand
transfer. This pin goes to the
CPU to request the transfer.
high. It indicates to the CPU
that the co-processor is
requesting an operand
transfer. This pin goes to the
CPU to request the transfer.
***
NMI Generation
***
Name
Type
Pin No.
Description
IOCKn
I
43
I/O CHANNEL CHECK:
when low, it indicates an I/O
channel error condition is
detected.
when low, it indicates an I/O
channel error condition is
detected.
PAR0
∼
PAR1
I/O
77
∼
78
PARITY BIT (0
∼
1): are the
memory parity bits for even
and odd bytes of the
memory bank. Each parity
bit is generated and written
during the memory write
operation. Each is checked
and reported on an error to
the system at the end of
memory read cycle. PAR0 is
memory parity bit for even
byte, PAR1 is the memory
parity bit for odd byte.
and odd bytes of the
memory bank. Each parity
bit is generated and written
during the memory write
operation. Each is checked
and reported on an error to
the system at the end of
memory read cycle. PAR0 is
memory parity bit for even
byte, PAR1 is the memory
parity bit for odd byte.
SYSRAMn
I
131
ENABLE MEMORY
PARITY: is an active low
signal indicating that
on-board RAM is being
accessed.
PARITY: is an active low
signal indicating that
on-board RAM is being
accessed.
RMRDn
I/O
130
ROM/RAM READ: is an
active low signal indicating
that on board ROM or RAM
is being read. It is an output
equal to NPBSYn signal
when I/O address F8 is
selected.
active low signal indicating
that on board ROM or RAM
is being read. It is an output
equal to NPBSYn signal
when I/O address F8 is
selected.
NMI
O
42
NON-MASKABLE
INTERRUPT: is an active
high signal to CPU
indicating that an error has
occurred in one of the
following area:
– memory parity error.
– I/O channel check signal.
INTERRUPT: is an active
high signal to CPU
indicating that an error has
occurred in one of the
following area:
– memory parity error.
– I/O channel check signal.
***
Chip Select Signals
***
Name
Type
Pin No.
Description
PGIOCS0n
O
137
PROGRAMMABLE I/O
CHIP SELECT 0: is an
active low I/O chip select
signal with a programmable
I/O address space. The I/O
device should reside on the
XD bus.
CHIP SELECT 0: is an
active low I/O chip select
signal with a programmable
I/O address space. The I/O
device should reside on the
XD bus.
COM1CSn
O
135
SERIAL PORT 1 CHIP
SELECT: is an active low
I/O chip select signal for the
serial port 1. This pin is
multiplexed with POFF7n.
SELECT: is an active low
I/O chip select signal for the
serial port 1. This pin is
multiplexed with POFF7n.
COM2CSn
O
136
SERIAL PORT 2 CHIP
SELECT: is an active low
I/O chip select signal for the
serial port 2. This pin is
multiplexed with POFF8n.
SELECT: is an active low
I/O chip select signal for the
serial port 2. This pin is
multiplexed with POFF8n.
PRTCSn
O
134
PRINTER PORT CHIP
SELECT: is an active low
I/O chip select signal for the
printer port. This pin is
multiplexed with POFF6n.
SELECT: is an active low
I/O chip select signal for the
printer port. This pin is
multiplexed with POFF6n.
PRTOEn
O
133
PRINTER PORT OUTPUT
ENABLE: is an active low
bidirectional printer port
output enable signal. This
pin is multiplexed with
POFF5n.
ENABLE: is an active low
bidirectional printer port
output enable signal. This
pin is multiplexed with
POFF5n.
– 49 –
***
Power Control Signals
***
Name
Type
Pin No.
Description
POFF0n
I/O
140
PROGRAMMABLE
BIDIRECTIONAL
CONTROL SIGNALS: I/O
signal to control peripherals
or as status input to system.
This pin is multiplexed with
LEDn.
BIDIRECTIONAL
CONTROL SIGNALS: I/O
signal to control peripherals
or as status input to system.
This pin is multiplexed with
LEDn.
POFF1n ~
POFF8n
POFF8n
I/O
141,
107
107
∼
109,
133
∼
137
PROGRAMMABLE
BIDIRECTIONAL
CONTROL SIGNALS: I/O
signal to control peripherals
or as status input to system.
These pins are multiplexed
with chip select signals.
BIDIRECTIONAL
CONTROL SIGNALS: I/O
signal to control peripherals
or as status input to system.
These pins are multiplexed
with chip select signals.
***
Miscellaneous
***
Name
Type
Pin No.
Description
CHGCLKn
O
124
CHANGE SYSTEM SPEED:
An active low output to
OTI-021 for changing
system clock frequency.
An active low output to
OTI-021 for changing
system clock frequency.
OSC
I
126
14.318 MHz OSCILLATOR
OUTPUT: a 14.318MHz TTL
level clock signal to
generate the clock for
on-chip 8254.
OUTPUT: a 14.318MHz TTL
level clock signal to
generate the clock for
on-chip 8254.
LEDn
I/O
140
LED CONTROL OUTPUT
OR GENERAL PURPOSE
I/O PIN: when active low will
turn on the LED which is
controlled by TURBOn pin
or an OAK proprietary
register. Power up default is
TURBOn. It can also be
used as a general-purpose
input/output pin controlled
by bit 1 of index register FD.
OR GENERAL PURPOSE
I/O PIN: when active low will
turn on the LED which is
controlled by TURBOn pin
or an OAK proprietary
register. Power up default is
TURBOn. It can also be
used as a general-purpose
input/output pin controlled
by bit 1 of index register FD.
TURBOn
I
141
TURBO SPEED
SELECTION INPUT: when
inactive high forces
CPUCLK to the 8MHz and
when active low CPUCLK
will be controlled by the
speed control register. This
pin is multiplexed with
POFF1n.
SELECTION INPUT: when
inactive high forces
CPUCLK to the 8MHz and
when active low CPUCLK
will be controlled by the
speed control register. This
pin is multiplexed with
POFF1n.
GND
I
17, 54,
65, 71,
74, 83,
89, 101,
122, 127
65, 71,
74, 83,
89, 101,
122, 127
GROUND: @0V
VDD
I
19, 59,
76, 80,
96, 97
76, 80,
96, 97
POWER: @5V
NOTE: The OTI-022 WOULD GO INTO THE TEST MODE UNDER
THE FOLLOWING INPUT COMBINATION.
RESET = "0"
MASTERn = "0"
DACK2n = "0"
MREFn = "0"
RESET = "0"
MASTERn = "0"
DACK2n = "0"
MREFn = "0"
3-1-5. VGA controller (F65510)
1. Introduction
The 65510 VGA flat panel controller provides a very low power con-
sumption, minimum-chip-count/board-space, low-cost graphics solu-
tion for inexpensive notebook, sub-notebook, hand-held, and pen-
based portable PCs and word processors. The 65510 requires only a
single 256K x 16 DRAM and single clock input, such that a complete
VGA subsystem can be implemented with just two ICs. The 65510
employs separate address and data buses and direct flat panel drive
capability, so that no external transceivers or buffers are required.
sumption, minimum-chip-count/board-space, low-cost graphics solu-
tion for inexpensive notebook, sub-notebook, hand-held, and pen-
based portable PCs and word processors. The 65510 requires only a
single 256K x 16 DRAM and single clock input, such that a complete
VGA subsystem can be implemented with just two ICs. The 65510
employs separate address and data buses and direct flat panel drive
capability, so that no external transceivers or buffers are required.
The 65510 employs a variety of advanced power management fea-
tures to reduce power consumption of the display subsystem and
extend battery life. The 65510’s internal logic, memory interface, bus
interface, and flat panel interface can be independently configured to
operate at either 3.3V or 5V. The 65510 is optimized for minimum
power consumption during normal operation and two power-saving
modes – Panel Off and Standby.
tures to reduce power consumption of the display subsystem and
extend battery life. The 65510’s internal logic, memory interface, bus
interface, and flat panel interface can be independently configured to
operate at either 3.3V or 5V. The 65510 is optimized for minimum
power consumption during normal operation and two power-saving
modes – Panel Off and Standby.
The 65510 supports a wide variety of monochrome Single-Panel,
Singe-Drive (SS) and Dual-Panel, Dual-Drive (DD) STN LCDs, TFT
LCDs, EL and plasma panels with up to 64 gray scales at 640 x 480
resolution. The 65510 provides a variety of programmable features to
optimize display quality, such as Vertical and Horizontal Compensa-
tion, SMARTMAP
Singe-Drive (SS) and Dual-Panel, Dual-Drive (DD) STN LCDs, TFT
LCDs, EL and plasma panels with up to 64 gray scales at 640 x 480
resolution. The 65510 provides a variety of programmable features to
optimize display quality, such as Vertical and Horizontal Compensa-
tion, SMARTMAP
TM
, Text Enhancement, three selectable color to
gray scale reduction techniques, and a polynomial FRC gray scale
algorithm, which reduces flicker on fast response "mouse quick" LCDs
without increasing the LCD’s vertical refresh rate.
algorithm, which reduces flicker on fast response "mouse quick" LCDs
without increasing the LCD’s vertical refresh rate.
The 65510 is fully compatible with the VGA graphics standard at the
register, gate, and BIOS levels. The 65510 provides full backwards
compatibility with the EGA, CGA, MDA, and Hercules graphics stand-
ards without using NMIs. CHIPS’ and third-party vendors supply fully
VGA-compatible BIOS’s, end-user utilities, and drivers for common
application programs (e.g., Windows, OS/2, Word Perfect, Lotus,
etc.). CHIPS’ drivers for Windows include a Big Cursor (to increase
the cursor’s legibility on monochrome flat panels), a panning/scrolling
driver (to increase performance), and a high performance 32-bit linear
addressing driver for the 640 x 480 256 color mode.
register, gate, and BIOS levels. The 65510 provides full backwards
compatibility with the EGA, CGA, MDA, and Hercules graphics stand-
ards without using NMIs. CHIPS’ and third-party vendors supply fully
VGA-compatible BIOS’s, end-user utilities, and drivers for common
application programs (e.g., Windows, OS/2, Word Perfect, Lotus,
etc.). CHIPS’ drivers for Windows include a Big Cursor (to increase
the cursor’s legibility on monochrome flat panels), a panning/scrolling
driver (to increase performance), and a high performance 32-bit linear
addressing driver for the 640 x 480 256 color mode.
■
Highly integrated Flat Panel controller
•
Separate Address and Data buses
•
Direct support for Dual or Single Scan panels
•
Single clock source
•
100-pin package
■
Single 256K x 16 DRAM provides two-chip VGA subsystem
■
Innovative clock "doubling" functionality
■
Memory options are (1) 256K x 16 DRAM or (4) 256K x 4 DRAMs
■
3.3V/5V memory interface for low power normal mode of operation
■
3.3V/5V panel and bus interfaces to support a variety of panels
and buses
and buses
■
Register-programmable 4mA or 8mA drive on bus data lines D0-15
and panel interface signals
and panel interface signals
■
Advanced power management features minimize power consump-
tion during normal operation
tion during normal operation
■
Dedicated input pin supports minimum power operation in Sus-
pend and Resume modes (less than 500
pend and Resume modes (less than 500
µ
A)
■
Integrated Multiple Bus Interface
•
High-speed x 86 SL PI Bus
•
EISA/ISA (PC/AT) Bus
•
Micro Channel (MC) Bus
•
High Speed 386 SX/DX Local Bus
■
High performance resulting from buffered writes (Write Buffer) and
fast screen updates (internal asynchronous 16-level FIFO)
fast screen updates (internal asynchronous 16-level FIFO)
■
16-bit display memory operations
■
CPU activity indicated for orderly power down procedure
– 50 –
■
Generates 64 gray levels on Monochrome Panels
■
Supports 640 x 480, x400, x200 Dual Panel/Dual Drive (D/D) and
Single Panel/Single Drive (S/S) LCD, Plasma, and EL Panels
Single Panel/Single Drive (S/S) LCD, Plasma, and EL Panels
■
Single clock source with rate multiplier function to generate a wide
range of dot clock frequencies for low power operation
range of dot clock frequencies for low power operation
■
Programmable polynomial based Frame Rate Control gray scale
algorithm supports fast response "mouse quick" displays by reduc-
ing flicker without increasing panel vertical refresh rate
algorithm supports fast response "mouse quick" displays by reduc-
ing flicker without increasing panel vertical refresh rate
■
Programmable vertical compensation techniques maximize display
area
area
■
Intelligent SMARTMAP
TM
color to gray scale conversion
■
Text Enhancement feature improves contrast of text on flat panel
displays
displays
■
Three software selectable RGB color to gray scale reduction tech-
niques
niques
■
Linearly Addressable Video Memory enables utilization of high per-
formance 32-bit software drivers
formance 32-bit software drivers
■
Fully compatible with IBM
TM
VGA
■
Full backwards compatability with EGA, CGA, MDA, and Hercules
graphics standards
graphics standards
■
Small low-cost package: EIAJ-standard 100-pin plastic flat pack
available in thin 20 mil lead pitch or standard 25 mil lead pitch
packages
available in thin 20 mil lead pitch or standard 25 mil lead pitch
packages
■
Chip pinouts optimized for PCB layout
2. Pin Assignments
Pin
No.
Pin Name
Type
Active
Description
21
D0
I/O
High
System Data Bus
20
D1
I/O
High
19
D2
I/O
High
18
D3
I/O
High
17
D4
I/O
High
16
D5
I/O
High
15
D6
I/O
High
14
D7
I/O
High
12
D8
I/O
High
11
D9
I/O
High
10
D10
I/O
High
9
D11
I/O
High
8
D12
I/O
High
7
D13
I/O
High
6
D14
I/O
High
5
D15
I/O
High
23
A0
In
High
System Address Bus
24
A1
In
High
25
A2
In
High
26
A3
In
High
27
A4
In
High
28
A5
In
High
29
A6
In
High
30
A7
In
High
31
A8
In
High
32
A9
In
High
33
A10
In
High
34
A11
In
High
35
A12
In
High
36
A13
In
High
37
A14
In
High
39
A15
In
High
40
A16
In
High
41
A17
In
High
42
A18
In
High
43
A19 (VGAHI)
In
High
When the Linear
Addressing Register has
a non-zero value, this
input serves as an active
high Chip Select for
ISA/EISA bus operation to
access memory beyond
the 1M address range
(A0-18 are used to
uniquely address each of
the 512K bytes in display
memory).
Addressing Register has
a non-zero value, this
input serves as an active
high Chip Select for
ISA/EISA bus operation to
access memory beyond
the 1M address range
(A0-18 are used to
uniquely address each of
the 512K bytes in display
memory).
99
RESET
In
High
Reset. Connect directly to
ISA bus reset.
Configuration inputs are
sampled on the falling
edge. Must be
synchronous to LCLK in
local bus interface mode.
Typically, ISA bus reset is
synchronized to the CPU
clock by the core logic
chipset.
ISA bus reset.
Configuration inputs are
sampled on the falling
edge. Must be
synchronous to LCLK in
local bus interface mode.
Typically, ISA bus reset is
synchronized to the CPU
clock by the core logic
chipset.
45
RFSH/
In
Low
This pin is an active low
signal indicating a
Refresh cycle. When this
pin is low, display
memory is not accessible.
signal indicating a
Refresh cycle. When this
pin is low, display
memory is not accessible.
ENAVDD
ACTIND
MEMW/
MEMR/
AEN
RFSH/
BHE/
A19
A18
A17
A16
A15
VCCM
A14
A13
A12
A11
A10
A9
A8
ACTIND
MEMW/
MEMR/
AEN
RFSH/
BHE/
A19
A18
A17
A16
A15
VCCM
A14
A13
A12
A11
A10
A9
A8
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
MD14
MD13
MD12
MD11
MD10
MD13
MD12
MD11
MD10
MD9
MD8
MD8
VCCM
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MD6
MD5
MD4
MD3
MD2
MD1
MD0
GND
STNDBY/
RESET
CLKIN
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
IO
R
D
/
IO
W
R
/
RDY
GN
D
D1
5
D1
4
D1
3
D1
2
D1
1
D1
0
D9
D8
(F
o
r
sy
st
e
m
b
u
s)
V
C
C
B
D7
D6
D5
D4
D3
D2
D1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GN
D
A0
A1
A2
A3
A4
A5
A6
A7
D0
MD
15
GN
D
MA
0
MA
1
MA
2
MA
3
MA
4
MA
5
MA
6
MA
7
MA
8
WE/
C
ASH
/
C
ASL
/
R
AS/
A
C
DCL
K
SH
F
C
L
K
VC
C
D
P7
P6
80
79
78
P5
P4
P3
P2
P1
P0
GN
D
FL
M
LP
EN
AVEE
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
77
(For memory
& Internal logic)
& Internal logic)
(VGAHI)
[CSFB/]
[ADL/]
[S0]
[S1]
[S1]
[MIO]
[DISA/]
[BHE/]
(ICTENA1/)
(TSENA1/)
(For memory
& Internal logic)
(TSENA1/)
(For memory
& Internal logic)
(ICTENA0/)
(TSENA0/)
(TSENA0/)
F65510
Flat Panel
VGA Controller
(M
)
(F
or
di
s
p
la
y
)
(L
D
0
)
(L
D
1
)
(L
D
2
)
(L
D
3
)
(U
D
0
)
(U
D
1
)
(U
D
2
)
(U
D
3
)
– 51 –
Pin
No.
Pin Name
Type
Active
Description
44
BHE/
In
Low
Byte High Enable. BHE/
low indicates the high
order byte at the current
word address is being
accessed.
low indicates the high
order byte at the current
word address is being
accessed.
46
AEN
In
High
In ISA interface, defines
valid I/O address: 0 =
valid I/O address, 1 =
Invalid I/O address
(latched internally).
valid I/O address: 0 =
valid I/O address, 1 =
Invalid I/O address
(latched internally).
49
ACTIND
Out
High
CPU Activity Indicator.
1
IORD/
In
Low
In ISA interface, indicates
an I/O Read Cycle.
an I/O Read Cycle.
2
IOWR/
In
Low
In ISA interface, indicates
an I/O Write Cycle.
an I/O Write Cycle.
47
MEMR/
In
Low
In the ISA bus, indicates a
Memory Read cycle.
Memory Read cycle.
48
MEMW/
In
Low
In ISA bus, indicates a
Memory Write cycle.
Memory Write cycle.
S1/
S0/
Operation
0
0
Undefined
0
1
Read
1
0
Write
1
1
Underfined
3
RDY
Out
High
Ready. Driven low during
bus cycle to indicate that
the current cycle should
be extended with wait
states. Driven low during
PI/LB cycles to indicate
the current cycle should
be completed. This signal
is driven high at the end
of the cycle, then tristated.
bus cycle to indicate that
the current cycle should
be extended with wait
states. Driven low during
PI/LB cycles to indicate
the current cycle should
be completed. This signal
is driven high at the end
of the cycle, then tristated.
78
MA0
Out
High
DRAM address bus
77
MA1
Out
High
76
MA2
Out
High
75
MA3
Out
High
74
MA4
Out
High
73
MA5
Out
High
72
MA6
Out
High
71
MA7
Out
High
XCV/ = 0: ENAVDD
becomes VGARD
becomes VGARD
70
MA8
Out
High
CD/ = 0: Enable Clock
Doubling
Doubling
66
RAS/
Out
Low
Row address strobe
67
CASL/
Out
Low
Column address strobe
for lower byte
for lower byte
68
CASH/
Out
Low
Column address strobe
for upper byte
for upper byte
69
WE/
Out
Low
Write enable
96
MD0
I/O
High
DRAM data bus
95
MD1
I/O
High
94
MD2
I/O
High
93
MD3
I/O
High
92
MD4
I/O
High
91
MD5
I/O
High
90
MD6
I/O
High
89
MD7
I/O
High
87
MD8
I/O
High
86
MD9
I/O
High
85
MD10
I/O
High
84
MD11
I/O
High
83
MD12
I/O
High
Pin
No.
Pin Name
Type
Active
Description
82
MD13
I/O
High
81
MD14
I/O
High
80
MD15
I/O
High
62
P7 (LD0)
Out
High
8-bit flat panel data output
61
P6 (LD1)
Out
High
60
P5 (LD2)
Out
High
59
P4 (LD3)
Out
High
58
P3 (UD0)
Out
High
57
P2 (UD1)
Out
High
56
P1 (UD2)
Out
High
55
P0 (UD3)
Out
High
53
FLM
Out
High
First Line Marker. Flat
Panel equivalent of
VSYNC.
Panel equivalent of
VSYNC.
52
LP
Out
High
Latch Pulse. Flat Panel
equivalent of HSYNC.
equivalent of HSYNC.
64
SHFCLK
Out
High
Shift Clock. Pixel clock for
panel data outputs.
panel data outputs.
65
ACDCLK
Out
High
ACD Clock or Display
Enable signal for flat
panels
Enable signal for flat
panels
(M)
Out
High
50
ENAVDD
Out
High
Not used
51
ENAVEE
Out
High
May optionally be
configured as an output
for vertical sync interrupts
(selectable as either
active high or active low).
configured as an output
for vertical sync interrupts
(selectable as either
active high or active low).
100
CLKIN
In
High
Single clock input serves
as both memory clock
(MCLK) and dot (pixel)
clock (DCLK). This input
is internally rate multiplied
to generate a range of dot
clock frequencies. This
input may be 14.31818
MHz if the clock doubling
(CD/) configuration bit is
asserted low on RESET,
otherwise this input is
typically connected to the
CPU clock (25-50 MHz).
as both memory clock
(MCLK) and dot (pixel)
clock (DCLK). This input
is internally rate multiplied
to generate a range of dot
clock frequencies. This
input may be 14.31818
MHz if the clock doubling
(CD/) configuration bit is
asserted low on RESET,
otherwise this input is
typically connected to the
CPU clock (25-50 MHz).
98
STNDBY/
In
Low
Standby mode entry and
exit pin
exit pin
13
VCCB
Power
—
Power input (System Bus
Interface)
Interface)
38
VCCM
Power
—
Power input (Memory
Interface & Internal Logic)
Interface & Internal Logic)
63
VCCD
Power
—
Power input (Display
Interface)
Interface)
88
VCCM
Power
—
Power input (Memory
Interface & Internal Logic)
Interface & Internal Logic)
4
GND
Ground
—
Ground input
22
GND
Ground
—
Ground input
54
GND
Ground
—
Ground input
79
GND
Ground
—
Ground input
97
GND
Ground
—
Ground input
– 52 –
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