Sharp ER-A850 (serv.man2) Service Manual ▷ View online
Name
Type
Pin No.
Description
SEL1
O
112
SELECT FUNCTION 1:
Together with SEL0
encodes the following
address ranges:
Together with SEL0
encodes the following
address ranges:
SEL1 SEL0
FUNCTION
0
0
Nothing selected
0
1
A15–A10=0 (I/O)
or on-board video
RAM
or on-board video
RAM
1
0
On-board video
ROM
ROM
1
1
I/O channel
memory but within
1M
memory but within
1M
PWRGOOD
I
145
POWER GOOD: An active
high signal from the power
supply after DC power level
is stable.
high signal from the power
supply after DC power level
is stable.
XD7
∼
XD0
I/O
148
∼
151,
153
∼
156
XDATA BUS: Bi-directional
data lines for accessing this
chip.
data lines for accessing this
chip.
REFRQT
I
117
MEMORY REFRESH
REQUEST: Memory refresh
request signal from 8254
Timer channel 1 which
comes from the OTI-022.
REQUEST: Memory refresh
request signal from 8254
Timer channel 1 which
comes from the OTI-022.
MREFn
I/O
159
MEMORY REFRESH: An
active low signal indicating
that refresh cycle is going on.
active low signal indicating
that refresh cycle is going on.
ENPARn
O
123
ENABLE MEMORY
PARITY: An active low
signal indicating that
on-board RAM is being
accessed.
PARITY: An active low
signal indicating that
on-board RAM is being
accessed.
RMRDn
I/O
118
ROM/RAM READ: An active
low signal indicating that
on-board ROM or RAM is
being read. It is an input
representing the signal
NPBSYn when accessing
80287 operation code for
80386SX CPU.
low signal indicating that
on-board ROM or RAM is
being read. It is an input
representing the signal
NPBSYn when accessing
80287 operation code for
80386SX CPU.
***
Memory Interface
***
Name
Type
Pin No.
Description
MA (1
∼
11)
O
31
∼
33,
27
∼
29,
23
∼
25,
21
MEMORY ADDRESS: It is a
time multiplexed memory
address bus. (For 256K
memory type MA (10, 11)
are not used, for 1M
memory type MA (11) is not
used).
time multiplexed memory
address bus. (For 256K
memory type MA (10, 11)
are not used, for 1M
memory type MA (11) is not
used).
RAS0n
∼
RAS3n
O
17
∼
14
ROW ADDRESS STROBE:
These are active low control
signals to the on-board
DRAM to strobe the row
address.
These are active low control
signals to the on-board
DRAM to strobe the row
address.
CASH0
∼
3n
∼
CASL0
∼
3n
O
5
∼
8,
10
∼
13
COLUMN ADDRESS
STROBE: (High & Low):
These are active low control
signals to on-board DRAM
to strobe the column
address:
STROBE: (High & Low):
These are active low control
signals to on-board DRAM
to strobe the column
address:
–
CASHn for odd byte
[D (15
[D (15
∼
8)].
–
CASLn for even byte
[D (7
[D (7
∼
0)].
MWEn
O
4
MEMORY WRITE ENABLE:
An active low signal used to
control ROM/RAM
read/write cycle.
An active low signal used to
control ROM/RAM
read/write cycle.
***
Miscellaneous
***
Name
Type
Pin No.
Description
CLKIN0
I
59
CLOCK INPUT 0: A 32MHz
TTL clock input with 50%
duty cycle. It is used for: the
CPU clock generation with
CPU running at 8 or 16MHz,
asynchronous bus clock
generation, and memory
refresh time.
TTL clock input with 50%
duty cycle. It is used for: the
CPU clock generation with
CPU running at 8 or 16MHz,
asynchronous bus clock
generation, and memory
refresh time.
CLKIN1
I
57
CLOCK INPUT 1: An
optional 20/25/40/50MHz
TTL clock input with 50%
duty cycle. It is used for
CPU clock generation with
CPU running at 10, 12.5, 20
and 25MHz.
optional 20/25/40/50MHz
TTL clock input with 50%
duty cycle. It is used for
CPU clock generation with
CPU running at 10, 12.5, 20
and 25MHz.
VDD
1, 18,
26, 62,
101, 139
26, 62,
101, 139
POWER: +5V supply.
VSS
5, 9,
20, 22,
27, 30,
41, 46,
52, 60,
68, 80,
90,,97
20, 22,
27, 30,
41, 46,
52, 60,
68, 80,
90,,97
GROUND:
NOTE: OTI-021 enters into TEST mode under the following input pin
combination: IORD-, IOWR-, INTA-, MEMRD- and MEMWR-
are all low and MASTER- high when PWRGOOD turns from
low to high.
are all low and MASTER- high when PWRGOOD turns from
low to high.
– 45 –
3-1-4. Peripheral controller (OTI-022)
1. Introduction
The OTI-022 is an I/O peripheral controller intended to be used with
the OTI-021 for a highly integrated IBM AT compatible systems.
the OTI-021 for a highly integrated IBM AT compatible systems.
The OTI-022 integrates peripheral devices with data and command
buffers. It is implemented using 1.0 micron HCMOS technology and
packaged in a 144-pin PQFP.
buffers. It is implemented using 1.0 micron HCMOS technology and
packaged in a 144-pin PQFP.
The OTI-022 features the following functions:
•
Programmable bi-directional control pins
•
Programmable I/O chip select pins
•
8254 compatible timer/counter
•
Two 8259 compatible interrupt controllers
•
Chip select logic for serial/parallel ports, disk controllers, video
controller and keyboard controller
controller and keyboard controller
•
Supports 80387SX with 80386SX CPU
•
Supports 80287 with 80286 CPU
•
Memory parity checker & generator
•
NMI generation logic
•
146818 compatible real-time clock with 128 bytes of CMOS RAM
•
Integrates all data buffers on the AT-bus
•
82395SX support
•
Optional external data buffer support
2. Pin Assignments
Fig. 1 OTI-022 Pin Assignment
1
N.C.
2
N.C.
3
IQR1
4
IRQ3
5
IRQ4
6
IRQ5
7
IRQ6
8
IRQ7
9
IRQ9
1 0
IRQ10
1 1
IRQ11
1 2
IRQ12
1 3
IRQ14
1 4
IRQ15
1 5
VDPMSEL
1 6
VDSEL/VGAEN
1 7
VSS
1 8
PCA9
1 9
VDD
2 0
PCA8
2 1
PCA7
2 2
PCA6
2 3
PCA5
2 4
PCA4
2 5
PCA3
2 6
PCA2
2 7
PCA1
2 8
PCA0
2 9
PVBHE
3 0
SEL0
3 1
SEL1
3 2
ROMCS
3 3
N.C.
3 4
NPERR
3 5
NPBUSY
3 6
NPCS
108
SELHDK1/POFF3
107
SELHDK0/POFF2
106
PDLDIR
105
PDHDIR
104
SPKOUT
103
XD0
102
XD1
101
VSS
100
XD2
9 9
XD3
9 8
XD4
9 7
VDD
9 6
VDD
9 5
XD5
9 4
XD6
9 3
XD7
9 2
PCD15
9 1
PCD14
9 0
PCD13
8 9
VSS
8 8
PCD12
8 7
PCD11
8 6
PCD10
8 5
PCD9
8 4
PCD8
8 3
VSS
8 2
PCD7
8 1
PCD6
8 0
VDD
7 9
PCD5
7 8
PAR1
7 7
PAR0
7 6
VDD
7 5
PCD4
7 4
VSS
7 3
PCD3
14
4
N.
C.
14
3
N.
C.
14
2
N.
C.
14
1
T
U
R
BQ/
PO
F
F
1
14
0
P
O
F
F
0/
LED
13
9
PC
A
E
N
13
8
M
A
ST
ER
13
7
PQ
IO
C
S
13
6
CO
M2
CS
/P
O
FF8
13
5
CO
M1
CS
/P
O
FF7
13
4
P
RTCS
/P
O
F
F6
13
3
P
RTO
E
/P
O
FF5
13
2
CRO
MCS
13
1
SY
SR
AM
13
0
RMRD
12
9
IO
R
D
12
8
IO
W
R
12
7
VS
S
12
6
OS
C
12
5
N.
C.
12
4
CHQ
CL
K
12
3
ME
MW
R
12
2
VS
S
12
1
PC
M
R
D
12
0
PC
M
W
R
11
9
N.
C.
11
8
RE
FRE
Q
11
7
ME
MRD
11
6
PW
R
G
OO
D
11
5
V
DDRTC
11
4
XT
AL
1
11
3
XT
AL
2
11
2
FQ
A
2
0
11
1
DA
CK
2
11
0
FL
US
H
10
9
FL
P
C
S
/P
O
FF4
37
N
PPR
E
Q
38
BU
S
Y
286
39
C
PER
E
Q
40
INTA
41
INT
R
42
NM
I
43
IO
C
K
44
SE
L
KBD
45
MRE
F
46
CP
UHL
DA
47
EN
S
W
AP
48
DE
N
49
R
ESE
T
50
SD
Q
51
SD
1
52
SD
2
53
SD
3
54
VS
S
55
SD
4
56
SD
5
57
SD
6
58
SD
7
59
VD
D
60
SD
8
61
SD
9
62
SD
1
0
63
SD
1
1
64
SD
1
2
65
VS
S
66
SD
1
3
67
SD
1
4
68
SD
1
5
69
P
CD0
70
P
CD1
71
VS
S
72
P
CD2
– 46 –
3. Block Diagram
Fig. 2 OTI-022 Block Diagram
4. Pin Description (OTI-022)
***
CPU Interface
***
Name
Type
Pin No.
Description
CPUHLDA
I
46
CPU HOLD
ACKNOWLEDGE: this
signal is active when the
CPU releases the control of
the bus.
ACKNOWLEDGE: this
signal is active when the
CPU releases the control of
the bus.
SD (0
∼
5)
I/O
50
∼
53,
55
∼
58,
60
∼
64,
66
∼
68
CPU DATA BUS (0
∼
15): is
the CPU data bus.
***
System Interface
***
Name
Type
Pin No.
Description
DENn
I
48
DATA BUFFER ENABLE: is
an active low control signal
to enable/disable the
internal data transceiver
between SD (0
an active low control signal
to enable/disable the
internal data transceiver
between SD (0
∼
15) and
PCD (0
∼
15).
PDLDIRn
O
106
EXTERNAL DATA BUFFER
OUTPUT ENABLE: is an
active low control signal to
enable output for the
external data transceiver
between PCD (0
OUTPUT ENABLE: is an
active low control signal to
enable output for the
external data transceiver
between PCD (0
∼
7) and
slot data bus (0
∼
7).
PDHDIRn
O
105
EXTERNAL DATA BUFFER
OUTPUT ENABLE: is an
active low control signal to
enable output for the
external data transceiver
between PCD (8
OUTPUT ENABLE: is an
active low control signal to
enable output for the
external data transceiver
between PCD (8
∼
15) and
slot data bus (8
∼
15).
ENSWAPn
I
47
ENABLE DATA SWAP: is
an input signal used for
enabling the byte swapping
data buffer.
an input signal used for
enabling the byte swapping
data buffer.
Name
Type
Pin No.
Description
XD7
∼
XD0
I/O
93
∼
95,
98
∼
100,
102
∼
103
XD BUS: bi-directional data
lines to/from the XD bus for
accessing on-board
peripherals.
lines to/from the XD bus for
accessing on-board
peripherals.
IORDn
I
129
I/O READ COMMAND:
active low command to
instruct the I/O device to
drive its data onto the data
bus.
active low command to
instruct the I/O device to
drive its data onto the data
bus.
IOWRn
I
128
I/O WRITE COMMAND:
active low command to
instruct the I/O device to
read the data present on the
data bus.
active low command to
instruct the I/O device to
read the data present on the
data bus.
MEMRDn
I
117
MEMORY READ
COMMAND: active low
signal to instruct the
memory subsystem to drive
its data onto the data bus.
COMMAND: active low
signal to instruct the
memory subsystem to drive
its data onto the data bus.
MEMWRn
I
123
MEMORY WRITE
COMMAND: active low
signal to instruct the
memory subsystem to read
the data present on the data
bus.
COMMAND: active low
signal to instruct the
memory subsystem to read
the data present on the data
bus.
REFRQT
O
118
REFRESH REQUEST:
indicates to the arbiter in the
OTI-021 that DRAM needs
refreshing.
indicates to the arbiter in the
OTI-021 that DRAM needs
refreshing.
CROMCSn
I
132
CARTRIDGE ROM CHIP
SELECT: An active low
input signal from OTI-021
indicating cartridge ROM is
being accessed.
SELECT: An active low
input signal from OTI-021
indicating cartridge ROM is
being accessed.
SEL0
I/O
30
SELECT FUNCTION 0: is
one of the two address
encoding signals. It is output
during refresh period as
TURBO signal for the
OTI-021.
one of the two address
encoding signals. It is output
during refresh period as
TURBO signal for the
OTI-021.
SEL1
I
31
SELECT FUNCTION 0:
together with SEL0 encodes
address ranges.
together with SEL0 encodes
address ranges.
ROMCS-
I
32
ROM CHIP SELECT: is an
active low signal used to
enable the ROM BIOS to
output data on to the data
bus.
active low signal used to
enable the ROM BIOS to
output data on to the data
bus.
VDPMSELn
O
15
VIDEO ROM CHIP
SELECT: is the chip select
signal for on board video
ROM.
SELECT: is the chip select
signal for on board video
ROM.
VDSEL/
VGAEN
VGAEN
O
16
VIDEO CHIP
SELECT/ENABLE: is the
chip select signal for on
board video I/O and RAM
address space, special for
OAK VGA OTI-037. If IBM
compatible VGA is used,
this pin becomes VGA
enable signal.
SELECT/ENABLE: is the
chip select signal for on
board video I/O and RAM
address space, special for
OAK VGA OTI-037. If IBM
compatible VGA is used,
this pin becomes VGA
enable signal.
NMI
IOCKn
PAR0,1
SYSRAMn
NPERRn
NPBSYn
NPEREQ
NPCSn
BUSY286n
CPEREQ
IRQ
INTR
INTAn
VDDRTC
XTAL1
XTAL2
WAKEUP
RESET
XD
PCD
SD
DENn
PDHDIRn,
PDLDIRn
ENSWAP
PDLDIRn
ENSWAP
CROMCSn
MEMRD/WRn,
IORD/WR n
IORD/WR n
SADR
SEL0,1
PGIOCSn
VDSELn,
SELKBDn,
FLPCSn,
SELHDn,
COM1CSn,
COM2CSn,
PRTCSn
SELKBDn,
FLPCSn,
SELHDn,
COM1CSn,
COM2CSn,
PRTCSn
OSC
REFRQT
ASPKOUT
Parity
&
NMI
Logic
Co-Processor
interface
2X
8259
Interrupt
controllers
RTC
&
Wakeup
time/counter
Data buffer
I/O
Chip select
logic
8254
Counter/timer
– 47 –
***
82395SX Support
***
Name
Type
Pin No.
Description
FGA20
O
112
FAST GATE A20
FLUSH
O
110
FLUSH CACHE: this pin
acts as cache flush when
EMS mapper is updated.
acts as cache flush when
EMS mapper is updated.
***
Bus Interface
***
Name
Type
Pin No.
Description
PCMEMRDn
O
121
MEMORY READ
COMMAND: active low
signal to instruct the
memory subsystem within
1M on the I/O channel to
drive its data onto the data
bus.
COMMAND: active low
signal to instruct the
memory subsystem within
1M on the I/O channel to
drive its data onto the data
bus.
PCMEMWRn
O
120
MEMORY WRITE
COMMAND: active low
signal to instruct the
memory subsystem within
1M on the I/O channel to
store the data present on
the data bus.
COMMAND: active low
signal to instruct the
memory subsystem within
1M on the I/O channel to
store the data present on
the data bus.
PCAEN
O
139
ADDRESS ENABLE: signal
to de-gate the I/O devices
from the I/O channel and
allow DMA transfers to take
place.
to de-gate the I/O devices
from the I/O channel and
allow DMA transfers to take
place.
MASTERn
I
138
MASTER: this signal is used
together with a DRQ line to
gain control of the system.
together with a DRQ line to
gain control of the system.
PCD (0
∼
15)
I/O
69
∼
70,
72
∼
73,
75, 79,
81
81
∼
82,
84
∼
88,
90
∼
92
I/O CHANNEL DATA BUS
(0
(0
∼
15): is the I/O channel
data bus. There are 2 sets
of data transceivers that are
connected internally, i.e.
between SD (0
of data transceivers that are
connected internally, i.e.
between SD (0
∼
7) and
PCD (0
∼
7) and between
SD (8
∼
15) and PCD (8
∼
15)
PCA9 ~
PCA0
PCA0
I
18,
20
20
∼
28
ADDRESS BUS: I/O
channel address bus.
channel address bus.
PCBHEn
I
29
BYTE HIGH ENABLE:
MREFn
I
45
MEMORY REFRESH
CYCLE: active low. It
indicates that the system is
in the memory refresh cycle.
CYCLE: active low. It
indicates that the system is
in the memory refresh cycle.
***
Real Time Clock
***
Name
Type
Pin No.
Description
XTAL1
I
114
XTAL INPUT FOR RTC: is
the crystal input for the
built-in real time clock.
the crystal input for the
built-in real time clock.
XTAL2
O
113
XTAL OUTPUT FOR RTC:
is the crystal output for the
built-in real time clock.
is the crystal output for the
built-in real time clock.
VDDRTC
I
115
POWER: battery power for
the built-in Real Time Clock.
the built-in Real Time Clock.
***
Reset Generation
***
Name
Type
Pin No.
Description
PWRGOOD
I
116
POWER GOOD:
PWRGOOD is coming from
the power supply to indicate
that power is stable.
PWRGOOD is coming from
the power supply to indicate
that power is stable.
RESET
I
49
RESET: is an active high
signal synchronized to the
CPU clock to reset the
system.
signal synchronized to the
CPU clock to reset the
system.
***
Timer Counter
***
Name
Type
Pin No.
Description
SPKOUT
O
104
SPEAKER DATA OUTPUT:
speaker output data, to be
connected to a speaker
driver to drive the speaker or
beeper.
speaker output data, to be
connected to a speaker
driver to drive the speaker or
beeper.
***
Interrupt Controller
***
Name
Type
Pin No.
Description
IRQ1, 3
∼
7
I
3
∼
14,
9
∼
12,
14
∼
15
INTERRUPT REQUEST
INPUTS: asynchronous
interrupt request inputs to
the internal 8259 controllers.
INPUTS: asynchronous
interrupt request inputs to
the internal 8259 controllers.
INTR
O
41
INTERRUPT REQUEST:
interrupt request to the CPU
and is generated whenever
a valid IRQ is received.
interrupt request to the CPU
and is generated whenever
a valid IRQ is received.
INTAn
I/O
40
INTERRUPT
ACKNOWLEDGE: is an
active low signal from the
OTI-021 indicating an
interrupt acknowledge cycle
is in progress. This pin also
carries MASTERn & single
ROM BIOS information from
OTI-021.
ACKNOWLEDGE: is an
active low signal from the
OTI-021 indicating an
interrupt acknowledge cycle
is in progress. This pin also
carries MASTERn & single
ROM BIOS information from
OTI-021.
***
Keyboard and Mouse Interface
***
Name
Type
Pin No.
Description
SELKBDn
O
44
SELECT KEYBOARD:
active low. Indicates the
keyboard controller is
selected.
active low. Indicates the
keyboard controller is
selected.
***
Floppy Disk Controller
***
(Not used)
Name
Type
Pin No.
Description
FLPCSn
O
109
FLOPPY SELECT: active
low. This pin is to select the
floppy disk controller. This
pin is multiplexed with
POFF4n.
low. This pin is to select the
floppy disk controller. This
pin is multiplexed with
POFF4n.
DACK2n
I
111
DMA ACKNOWLEDGE:
active low. It indicates that
the floppy disk controller has
been granted a DMA cycle.
active low. It indicates that
the floppy disk controller has
been granted a DMA cycle.
– 48 –
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