Sharp ER-A850 (serv.man2) Service Manual ▷ View online
2. Pin descriptions
Pin
No.
I/O
Signal name
Function
Remark
157
I
LA23
ISA BUS A23 NO
LATCH
LATCH
*
(CS1)
5V
158
I
LA22
ISA BUS A22 NO
LATCH
LATCH
*
(CS0)
5V
159
I
LA21
ISA BUS A21 NO
LATCH
LATCH
*
(NCS2)
5V
160
I
LA20
ISA BUS A20 NO
LATCH
LATCH
*
(ADS)
5V
161
I
LA19
ISA BUS A19 NO
LATCH
LATCH
*
(SIN)
5V
162
I
LA18
ISA BUS A18 NO
LATCH
LATCH
*
(MR)
5V
163
I
LA17
ISA BUS A17 NO
LATCH
LATCH
*
(DCD)
5V
164
I
(LA16)
FOR TEST INPUT
*
(RI)
5V
165
I
SA19
ISA ADDRESS BUS
A19
A19
*
(DSR)
5V
166
I
SA18
ISA ADDRESS BUS
A18
A18
*
(CTS)
5V
167
I
SA17
ISA ADDRESS BUS
A17
A17
*
(XTAL2)
5V
168
I
SA16
ISA ADDRESS BUS
A16
A16
*
(XTAL1)
5V
169
I
SA15
ISA ADDRESS BUS
A15
A15
*
(A2)
5V
170
I
SA14
ISA ADDRESS BUS
A14
A14
*
(A1)
5V
171
I
SA13
ISA ADDRESS BUS
A13
A13
*
(A0)
5V
172
I
SA12
ISA ADDRESS BUS
A12
A12
*
(IOR)
5V
173
I
SA11
ISA ADDRESS BUS
A11
A11
*
(NIOR)
5V
174
I
SA10
ISA ADDRESS BUS
A10
A10
*
(IOW)
5V
175
I
SA9
ISA ADDRESS BUS
A9
A9
*
(NIOW)
5V
176
I
SA8
ISA ADDRESS BUS
A8
A8
*
(RCLK)
5V
177
I
SA7
ISA ADDRESS BUS
A7
A7
*
(DIN7)
5V
178
I
SA6
ISA ADDRESS BUS
A6
A6
*
(DIN6)
5V
179
I
SA5
ISA ADDRESS BUS
A5
A5
*
(DIN5)
5V
180
I
SA4
ISA ADDRESS BUS
A4
A4
*
(DIN4)
5V
181
I
SA3
ISA ADDRESS BUS
A3
A3
*
(DIN3)
5V
182
Fixed
power
GND
183
Fixed
power VDD
5V
184
I
SA2
ISA ADDRESS BUS
A2
A2
*
(DIN2)
5V
185
I
SA1
ISA ADDRESS BUS
A1
A1
*
(DIN1)
5V
186
I
SA0
ISA ADDRESS BUS
A0
A0
*
(DIN0)
5V
Pin
No.
I/O
Signal name
Function
Remark
187
3.3V power
VDD
3.3V
188
N.C
5V
189
N.C
5V
190
N.C
5V
191
N.C
5V
192
N.C
5V
193
N.C
5V
194
N.C
5V
195
N.C
5V
196
Power
source
GND
197
Power
source
VDD
5V
198
I/O
SD7
ISA DATA BUS D7
5V
199
I/O
SD6
ISA DATA BUS D6
5V
200
I/O
SD5
ISA DATA BUS D5
5V
201
I/O
SD4
ISA DATA BUS D4
5V
202
I/O
SD3
ISA DATA BUS D3
5V
203
I/O
SD2
ISA DATA BUS D2
5V
204
I/O
SD1
ISA DATA BUS D1
5V
205
I/O
SD0
ISA DATA BUS D0
5V
206
Power
source
GND
207
I
BALE
ISA BUS ADDRESS
LATCH ENABLE
LATCH ENABLE
5V
208
I
AEN
ISA ADDRESS
ENABLE
ENABLE
5V
1
I
MEMR_
ISA MEMORY
READ COMMAND
READ COMMAND
5V
2
I
MEMW_
ISA MEMORY
WRITE COMMAND
WRITE COMMAND
5V
3
I
IOW_
ISA IO WRITE
COMMAND
COMMAND
5V
4
I
IOR_
ISA IO READ
COMMAND
COMMAND
5V
5
I
RESETDRV
ISA SYSTEM RESET
5V
6
I
BUSCLK
ISA BUS CLOCK
(8MHz)
(8MHz)
5V
7
I
REFRESH_
ISA REFERSH
5V
8
N.C
5V
9
O
IRQ3
ISA INTERRUPT
REQUEST 3
REQUEST 3
5V
10
O
IRQ4
ISA INTERRUPT
REQUEST 4
REQUEST 4
5V
11
O
IRQ5
ISA INTERRUPT
REQUEST 5
REQUEST 5
5V
12
O
IRQ10
ISA INTERRUPT
REQUEST 10
REQUEST 10
5V
13
O
IRQ11
ISA INTERRUPT
REQUEST 11
REQUEST 11
5V
14
O
IRQ15
ISA INTERRUPT
REQUEST 15
REQUEST 15
5V
15
Power
source
GND
16
O
DRQ0
ISA DMA REQUEST
0
0
5V
17
O
DRQ3
ISA DMA REQUEST
3
3
5V
18
I
DACK0
ISA DMA
ACKNOWLEDGE 0
ACKNOWLEDGE 0
5V
– 57 –
Pin
No.
I/O
Signal name
Function
Remark
19
I
DACK3
ISA DMA
ACKNOWLEDGE 3
ACKNOWLEDGE 3
5V
20
I
TC
ISA TERMINAL
COUNT
COUNT
5V
21
N.C
5V
22
N.C
5V
23
N.C
5V
24
O
PEN
POWER ON RESET
ENABLE
ENABLE
5V
25
I
CLK183
UART CLOCK
(1.843MHz)
(1.843MHz)
5V
26
Fixed
power
VDD
5V
27
Fixed
power
GND
28
O
ROS1_
BIOS ROM CHIP
SELECT
SELECT
5V
29
O
ROS2_
SYSTEM ROM
CHIP SELECT
CHIP SELECT
5V
30
O
VGACS
VGA CHIP SELECT
5V
31
O
VMCS16_
VRAM MEMCS16
5V
32
I
SW5
SYSTEM SWITCH 5
5V
33
I
SW4
SYSTEM SWITCH 4
5V
34
I
SW3
SYSTEM SWITCH 3
5V
35
I
SW4
SYSTEM SWITCH 2
5V
36
I
SW1
SYSTEM SWITCH 1
5V
37
O
HP3
NOT USED
5V
38
I
HP4
ODS_
5V
39
I
HP5
PNLSNS_
5V
40
I
HP6
NOT USED
5V
41
I
HP7
NOT USED
5V
42
Power
source
GND
5V
43
O
CLK307
307KHz FOR
OPTION CLERK
OPTION CLERK
5V
44
O
CLKTXD
TXD FOR OPTION
CLERK
CLERK
5V
45
I
CLKRXD
RXD FOR OPTION
CLERK
CLERK
5V
46
O
CLKDTR
DTR FOR OPTION
CLERK
CLERK
5V
47
I
CLKDSR
DSR FOR OPTION
CLERK
CLERK
5V
48
O
CLKRFS
RTS FOR OPTION
CLERK
CLERK
5V
49
I
CLKCTS
CTS FOR OPTION
CLERK
CLERK
5V
50
I
CLKDCD
DCD FOR OPTION
CLERK
CLERK
5V
51
I
CLKRI
RI FOR OPTION
CLERK
CLERK
5V
52
I
PSX
PS/S-RAM BOARD
SENSE INPUT
SENSE INPUT
5V
53
Power
source
VDD
3.3V
54
Power
source
GND
55
I
PGOOD
POWER GOOD
3.3V
56
O
RA22
RAM ADDRESS A22
3.3V
57
O
RA21
RAM ADDRESS A21
3.3V
Pin
No.
I/O
Signal name
Function
Remark
58
O
RA20
RAM ADDRESS A20
3.3V
59
O
RA19
RAM ADDRESS
A19
A19
*
(BOUDOUT)
3.3V
60
O
RA18
RAM ADDRESS
A18
A18
*
(DOIS)
3.3V
61
Power
source
GND
62
O
RA17
RAM ADDRESS
A17
A17
*
(CSOUT)
3.3V
63
O
RA16
RAM ADDRESS
A16
A16
*
(INTRPT)
3.3V
64
O
RA15
RAM ADDRESS
A15
A15
*
(OUT2)
3.3V
65
O
RA14
RAM ADDRESS
A14
A14
*
(OUT1)
3.3V
66
O
RA13
RAM ADDRESS
A13
A13
*
(RTS)
3.3V
67
O
RA12
RAM ADDRESS
A12
A12
*
(DTR)
3.3V
68
O
RA11
RAM ADDRESS
A11
A11
*
(SOUT)
3.3V
69
O
RA10
RAM ADDRESS
A10
A10
*
(D7)
3.3V
70
Power
source
GND
71
O
RA9
RAM ADDRESS A9
*
(D6)
3.3V
72
O
RA8
RAM ADDRESS A8
*
(D5)
3.3V
73
O
RA7
RAM ADDRESS A7
*
(D4)
3.3V
74
O
RA6
RAM ADDRESS A6
*
(D3)
3.3V
75
O
RA5
RAM ADDRESS A5
*
(D2)
3.3V
76
O
RA4
RAM ADDRESS A4
*
(D1)
3.3V
77
O
RA3
RAM ADDRESS A3
*
(D0)
3.3V
78
Fixed
power
VDD
3.3V
79
Fixed
power
GND
80
O
RA2
RAM ADDRESS A2
3.3V
81
O
RA1
RAM ADDRESS A1
3.3V
82
O
RA0
RAM ADDRESS A0
3.3V
83
I/O
RD7
RAM DATA D7
3.3V
84
I/O
RD6
RAM DATA D6
3.3V
85
I/O
RD5
RAM DATA D5
3.3V
86
I/O
RD4
RAM DATA D4
3.3V
87
I/O
RD3
RAM DATA D3
3.3V
88
Power
source
GND
89
Power
source
VDD
3.3V
90
I/O
RD2
RAM DATA D2
3.3V
91
I/O
RD1
RAM DATA D1
3.3V
92
I/O
RD0
RAM DATA D0
3.3V
93
O
PSWR_
PS-RAM WRITE
3.3V
– 58 –
Pin
No.
I/O
Signal name
Function
Remark
94
O
PSREF_
PS-RAM
READ/REFRESH
READ/REFRESH
3.3V
95
O
PRAS1E_
OPTION RAM EVEN
CHIP SELECT
CHIP SELECT
3.3V
96
O
PRAS10_
OPTION RAM ODD
CHIP SELECT
CHIP SELECT
3.3V
97
O
PRASOE_
STD RAM EVEN
CHIP SELECT
CHIP SELECT
3.3V
98
Power
source
GND
99
O
PRASOO_
STD RAM ODD
CHIP SELECT
CHIP SELECT
3.3V
100
O
RRES_
RAM MODULE
RESET
RESET
3.3V
101
O
DR0
DRAWER0
3.3V
102
O
DR1
DRAWER1
3.3V
103
O
DR2
DRAWER2
3.3V
104
O
DR3
DRAWER3
3.3V
105
I
POFF_
ACL INPUT FROM
PS UNIT
PS UNIT
5V
106
I
IS6_
RRDY- FROM IOC
5V
107
I
IS5_
EVRQ- FROM IOC
5V
108
I
IS4_
SHEN- FROM
CKDC4
CKDC4
5V
109
I
IS3_
SRNRQ- FROM
SRN I/F
SRN I/F
5V
110
I
IS2_
N.U
5V
111
I
IS1_
N.U
5V
112
I
IS0_
N.U
5V
113
Power
source
GND
114
O
SRNCS_
SRN CHIP SELECT
5V
115
O
TCH
TERMINAL COUNT
TO HOST
TO HOST
5V
116
I
DRQRH
DRQ READ TO
HOST
HOST
5V
117
I
DRQWH
DRQ WRITE TO
HOST
HOST
5V
118
O
DAKSRN_
DACK SRN
5V
119
O
SRNRES
SRN RESET
(POSITIVE)
(POSITIVE)
5V
120
O
SRNRES_
SRN RESET
(NEGATIVE)
(NEGATIVE)
5V
121
Power
source
GND
122
I
RI1_
RS232 CH1 RI
5V
123
O
TXD1
RS232 CH1 TXD
5V
124
I
RXD1
RS232 CH1 RXD
5V
125
O
DTR1_
RS232 CH1 DTR
5V
126
I
DSR1_
RS232 CH1 DSR
5V
127
O
RTS1_
RS232 CH1 RTS
5V
128
I
CTS1_
RS232 CH1 CTS
5V
129
I
DCD1_
RS232 CH1 DCD
5V
130
Fixed
power
VDD
5V
131
Fixed
power
GND
132
I
RI2_
RS232 CH2 RI
5V
133
O
TXD2
RS232 CH2 TXD
5V
Pin
No.
I/O
Signal name
Function
Remark
134
I
RXD2
RS232 CH2 RXD
5V
135
O
DTR2_
RS232 CH2 DTR
5V
136
I
DSR2_
RS232 CH2 DSR
5V
137
O
RTS2_
RS232 CH2 RTS
5V
138
I
CTS2_
RS232 CH2 CTS
5V
139
I
DCD2_
RS232 CH2 DCD
5V
140
O
HTIO
HOST TO IOC
5V
141
I
IOTH
IOC TO HOST
5V
142
O
(BAUDOUT)
N.U
5V
143
O
IORES_
IOC RESET
(NEGATIVE)
(NEGATIVE)
5V
144
Power
GND
145
I
CDV
TEST (1:
NORMAL/0:
COUNTER)
NORMAL/0:
COUNTER)
5V
146
I
URT0
UART TEST
5V
147
I
URT1
UART TEST
5V
148
I
URT2
UART TEST
5V
149
I
DS
DRAWER OPEN
SENSE
SENSE
5V
150
O
KRES_
CKDC RESET
(NEGATIVE)
(NEGATIVE)
5V
151
O
HTS
HOST TO SUB
5V
152
I
STH
SUB TO HOST
5V
153
O
SCK
SHIFT CLOCK
5V
154
O
HP2
NOT USED
5V
155
O
HP1
OCLKRES
(NEGATIVE)
(NEGATIVE)
5V
156
O
HP0
BKLT
5V
UART TEST MODE
URT2
URT1
URT0
1
X
X
Normal operation
0
0
0
UART0 TEST MODE
0
0
1
UART1 TEST MODE
0
1
0
UART2 TEST MODE
0
1
1
UART3 TEST MODE
Signals marked with "
*
" or in parentheses ( ) mean 8250 pin at UART
test.
– 59 –
3-2-3. Drawer drive circuit
The above drawer drive circuit is provided for four drawers. Drawer
connectors are provided for two drawers. Since the drawer solenoid
operates on 24V, the voltage is +12V
connectors are provided for two drawers. Since the drawer solenoid
operates on 24V, the voltage is +12V
∼
–12V (24V range).
3-2-4. RS-232 circuit
The above RS-232 circuit is standard provision.
IRQ signal
I/O address
COM
Port #
IRQ4
3F8-3FF
COM1
P1
IRQ3
2F8-2FF
COM2
P2
3-2-5. System ROM circuit
System ROM control
The system area for DOS and the related utilities is defined to the
1MB linear area of E00000H
1MB linear area of E00000H
∼
EFFFFFH.
Interface is performed in 8 bits of data bus width. Bus timing is de-
signed to be AT bus timing.
In the ER-A850/A880, decode control is performed as follows:
signed to be AT bus timing.
In the ER-A850/A880, decode control is performed as follows:
ROS2#:
System ROM (standard installation)
(*1)
E00000H
∼
EFFFFFH (actual installation: 256K
×
8,
EPROM)
Expandable up to 1MB in the architecture
Expandable up to 1MB in the architecture
RASIE-:
Optional RAM disk area
(*2)
RASIO-: Optional RAM disk area
3-2-6. RAM disk circuit
RAM disk control
As the application and data file area, RAM disk is defined to the linear
area (max. 4MB) of 600000H
area (max. 4MB) of 600000H
∼
DFFFFFH.
Interface is performed in 8 bits of data bus width. Bus timing is de-
signed to be AT bus timing. Since the RAM disk is backed up by a
battery (+3.3V), voltage translation between 5V and 3.3V for interface
is performed by the PSC, supporting both of 5V I/O and 3V I/O.
In the ER-A850/A880, decode control is performed as follows:
signed to be AT bus timing. Since the RAM disk is backed up by a
battery (+3.3V), voltage translation between 5V and 3.3V for interface
is performed by the PSC, supporting both of 5V I/O and 3V I/O.
In the ER-A850/A880, decode control is performed as follows:
* 1
PRAS0E :
Standard RAM disk
600000H
600000H
∼
67FFFFH (512K x 8 PSRAM)
* 2
PRAS0O :
Standard RAM disk
680000H
680000H
∼
6FFFFFH (512K x 8 PSRAM)
* 3, * 4, * 5, * 6:
The chip select signal of the option RAM disk (ER-
03MB/04MB) is generated as follows:
PSC
DS
DR0~4
DTC144EK
DTA144EK
(-12V): Power supply unit
STA401A
Drawer connector
Micro SW
Drawer solenoid
+12V
IRQ3
IRQ4
RI1/2, DCD1/2
PSC
RXD1/2, DSR1/2, CTS1/2
TXD1/2, DTR1/2, RTS1/2
MCT45406
RS-232 connector (9pin)
CPU
OTI-021
PS C
SD0~7
PCA0~15
ROS2
System
ROM
ROM
RAM AREA
RAS1E-
RAS1O-
C00000H
D00000H
E00000H
F00000H
ROS2#
ROS1#
NOT USED
SYSTEM ROM
OPTIONAL RAM DISK *2
*1
PSC
RA19~21
RA0~18
PSK
RRES
PSREF
PSWR
PSWR
PRAS0E
PRAS0O
PRAS1O
PRAS1E
Standard
RAM
disk
Standard
RAM
disk
PSREF
PSWR
PSWR
PRAS0E
PSREF
PSWR
PSWR
PRAS0O
PSK
RRES
PSREF
PSWR
PSWR
PRAS1O
PRAS1E
ER-03MB
ER-04MB
ER-04MB
Option RAM
connector
connector
900000H
PRAS1O (CS4)
*6
PRAS1E (CS0)
* 5
800000H
PRAS1O (CS7)
*4
PRAS1E (CS3)
* 3
700000H
PRAS0O
*2
PRAS0E
* 1
600000H
ER-03MB
ER-04MB
Standard RAM disk
– 60 –
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