Sharp ER-A850 (serv.man2) Service Manual ▷ View online
Pin No.
Signal name/in-out/Description
30 – 26
23 22, 21
23 22, 21
DO-D7 (Data Bus) – Input/output (3 state)
When the
When the
µ
PD8257 is programmed by the CPU (Z-80), the data bus accepts the upper/Lower byte of DMA address and
TC register value output from the CPU, or 8-bit data to be loaded into the Mode Set register (Slave mode). When the
CPU wants to read the value of the DMA address register, TC register, or status register, the data bus is used to transfer
the pertinent data value to the CPU (Slave mode).
During the DMA cycle (when the
CPU wants to read the value of the DMA address register, TC register, or status register, the data bus is used to transfer
the pertinent data value to the CPU (Slave mode).
During the DMA cycle (when the
µ
PD8257 is bus master), the data bus is used to transfer the upper byte of memory
address from a DMA address register to the
µ
PD8212. This address byte is transferred at the beginning of a DMA cycle.
The data bus is subsequently used to transfer memory data in the remaining portion of the DMA cycle.
32 – 35
A0-A3 (Address Bus) – Input/output (3 state)
When in the Slave mode, these pins serve as inputs to select a register to be read or written. When in the Master mode,
these pins output the lower 4 bits of 16-bit memory address.
When in the Slave mode, these pins serve as inputs to select a register to be read or written. When in the Master mode,
these pins output the lower 4 bits of 16-bit memory address.
37 – 40
A4-A7 (Address Bus) – Output (3 state)
When in the Master mode, these pins output bits 4-7 of the 16-bit memory address. When in the Slave mode, these pins
are set to high impedance.
When in the Master mode, these pins output bits 4-7 of the 16-bit memory address. When in the Slave mode, these pins
are set to high impedance.
36
TC (Terminal Count) – Output
The TC output Indicates to the currently selected I/O device that the current DMA cycle is the last cycle of the data
block. If the TC stop bit of the Mode Set register is set, the selected channel will be automatically disabled at the end of
the DMA cycle.
The TC signal is output when bit 14 of the TC register on the selected channel is reset to zero. The value (n-1) must be
loaded in the lower 14 bits of the TC register, where "n" is the number of DMA cycles to be executed.
The TC output Indicates to the currently selected I/O device that the current DMA cycle is the last cycle of the data
block. If the TC stop bit of the Mode Set register is set, the selected channel will be automatically disabled at the end of
the DMA cycle.
The TC signal is output when bit 14 of the TC register on the selected channel is reset to zero. The value (n-1) must be
loaded in the lower 14 bits of the TC register, where "n" is the number of DMA cycles to be executed.
5. Oscillator Circuit
The LSI system clocks and transfer clocks for the SRN system are
obtained by dividing a single master clock. The master clock (16.0
MHz) is applied to the CLK pin (pin 1) of the MB62H149, where it is
divided into system clocks for the individual LSI chips. The resulting
clocks of
obtained by dividing a single master clock. The master clock (16.0
MHz) is applied to the CLK pin (pin 1) of the MB62H149, where it is
divided into system clocks for the individual LSI chips. The resulting
clocks of
φ
(4MHz) and TXC (1 or 0.5 MHz) appear at pins 8 and 71,
respectively.
Fig. 25
6. Timer counter Z80A-CTC (TMPZ84C30AP) descriptions
This device is composed of four sets of counter/timer, and is provided
with the Z-80 CPU bus and the interface interruption control circuit.
In this board, the channels are used as follows:
with the Z-80 CPU bus and the interface interruption control circuit.
In this board, the channels are used as follows:
CH0: Used as the timer mode 50
µ
s/100
µ
s pre-scaler. (System clock
φ
is divided.)
CH1: Used for interruption from the counter mode MB62H149 INTS
signal (7 pin) to the Z-80 CPU.
CH2: Used as the counter mode internal timer (50us/100us input:
The ZC/T00 signal of CH0 is inputted.)
CH3: Used as the counter mode internal timer (0.5ms/1ms input:
The TM1 signal (10 pin) of MB62H149 is inputted.)
(Note) "(A time)/(B time)" shows 1MBPS/0.5MBPS.
11
IC24
CLK
TXC
Φ
To ADLC (1 or 0.48 [MHz})
System CLK (4 [MHz])
ICD2028
MB62H149
– 69 –
TMPZ84C30AP (Z-80A CTC)
Pin descriptions
Signal name
Pin No.
Direction
Descriptions
D0
∼
D7
1
∼
4
25
∼
28
B
8 bit bidirectional bus.
Used to transmit command data between the CPU and the CTC.
Used to transmit command data between the CPU and the CTC.
RD
6
I
Read signal.
Used in combination with IORQ and CE when transmitting data and channel control words between
the CPU and the CTC.
Used in combination with IORQ and CE when transmitting data and channel control words between
the CPU and the CTC.
IORQ
10
I
I/O request signal.
Used in combination with RD and CD when transmitting data and channel control words between
the CPU and the CTC.
Used in combination with RD and CD when transmitting data and channel control words between
the CPU and the CTC.
ZC/TO0
ZC/TO1
ZC/TO2
ZC/TO1
ZC/TO2
7
8
9
8
9
O
O
O
O
O
Zero count/time out.
When the down counter value becomes zero in the timer mode and in the counter mode, pulses are
outputted from these pins.
When the down counter value becomes zero in the timer mode and in the counter mode, pulses are
outputted from these pins.
IEO
11
O
Interruption enable output
Controls interruption of lower peripheral LSIs in the daisy chain.
Controls interruption of lower peripheral LSIs in the daisy chain.
IEI
13
I
Interruption request.
Shows presence of interruption of the upper peripheral LSIs in the daisy chain.
Shows presence of interruption of the upper peripheral LSIs in the daisy chain.
INT
12
O
Interrupt request.
When IEI pin is at HIGH level and an interruption is enabled by the program, if any channel down
counter counts zero, INT is driven to LOW.
When IEI pin is at HIGH level and an interruption is enabled by the program, if any channel down
counter counts zero, INT is driven to LOW.
M1
14
I
Machine cycle 1.
Shows M1 signal of the Z-80 CPU.
Shows M1 signal of the Z-80 CPU.
CLK
15
I
Single phase clock input.
Inputs the single phase Z-80 standard system clocks.
Inputs the single phase Z-80 standard system clocks.
CE
16
I
Chip enable.
Used in combination with IORQ and RD when writing channel control words, interruption vector, and
time constant between the CPU and the CTC or when reading the down counter content of each
channel.
Used in combination with IORQ and RD when writing channel control words, interruption vector, and
time constant between the CPU and the CTC or when reading the down counter content of each
channel.
RESET
17
I
Reset signal.
When all channels stop operations, the interruption bits in all channel control registers are reset.
RESET must be kept LOW for min. 3 system clocks.
When all channels stop operations, the interruption bits in all channel control registers are reset.
RESET must be kept LOW for min. 3 system clocks.
CS0
CS1
CS1
18
19
19
I
I
I
Channel select.
Used to select one of four sets of CTC channels by 2 bit codes when writing or reading.
Used to select one of four sets of CTC channels by 2 bit codes when writing or reading.
CLK/TRG0
CLK/TRG1
CLK/TRG2
CLK/TRG3
CLK/TRG1
CLK/TRG2
CLK/TRG3
23
22
21
20
22
21
20
I
I
I
I
I
I
I
External clock/timer trigger.
These four CLK/TRG pins corresponds to the four sets of channels.
By each active edge of these pins, the down counter is decremented in the counter mode and the
timer operation is started in the timer mode.
These four CLK/TRG pins corresponds to the four sets of channels.
By each active edge of these pins, the down counter is decremented in the counter mode and the
timer operation is started in the timer mode.
VCC
24
—
+5V
GND
6
—
GND
7. Serial/Parallel Conversion for Data Transmission
(MC68B54)
1) General
Since a serial synchronous transmission scheme is used for SRN
communications, serial/parallel conversion is equired on the send/re-
ceive data. The serial/parallel converter circuit uses an MC68B54
Advanced Data Link Controller (ADLC). The ADLC converts D0-D7
parallel data into serial data in synchronicity with the TXC signal (pin
5), and converts serial data (RXD) into parallel in synchronicity with
the RXC signal (pin 4).
communications, serial/parallel conversion is equired on the send/re-
ceive data. The serial/parallel converter circuit uses an MC68B54
Advanced Data Link Controller (ADLC). The ADLC converts D0-D7
parallel data into serial data in synchronicity with the TXC signal (pin
5), and converts serial data (RXD) into parallel in synchronicity with
the RXC signal (pin 4).
– 70 –
Pin No.
Symbol
Pin name and function
Input/
Output
1
VSS
Ground pin
–
2
RTS
This pin indicates that send data exists in the TxFIF0. If CR2b7 is set to one, this output is set to Low.
This pin is set to High when a Close flag has been transmitted after a frame is completed, an Abort is
transmitted, CR2b7 is reset in the Mark Idle state (RTS remains at Low if CR2b7 is reset to zero in any
state other than the Mark Idle state), or the RESET input is held at Low.
(Requeset Data Input)
This pin is set to High when a Close flag has been transmitted after a frame is completed, an Abort is
transmitted, CR2b7 is reset in the Mark Idle state (RTS remains at Low if CR2b7 is reset to zero in any
state other than the Mark Idle state), or the RESET input is held at Low.
(Requeset Data Input)
Out
3
RXD
Receiver Data input to accept received data.
(Receiver Data Input)
(Receiver Data Input)
In
4
RXC
Receiver Clock input to accept a synchronization signal for the received data input.
(Receiver Clock Input)
(Receiver Clock Input)
In
5
TXC
Transmitter Clock input, used to synchronize the transmit data output.
When in the Loop mode (including Test mode), the signal at this pin must be in-phase with the RxC.
(Transmitter Clock Input)
When in the Loop mode (including Test mode), the signal at this pin must be in-phase with the RxC.
(Transmitter Clock Input)
In
6
TXD
Transmit Data output.
(Transmit Data output)
(Transmit Data output)
Out
7
IRQ
Interrupt Request output. This pin is set Low if an interrupt occurred and the corresponding Enable bit
is set. It is set High when the cause of the interrupt is removed or the Enable bit is reset.
(Interrupt Request Output)
is set. It is set High when the cause of the interrupt is removed or the Enable bit is reset.
(Interrupt Request Output)
Out
8
RESET
RESET input. If a Low signal is applied to this pin, the RxReset (CR1b6) and TxReset (CR1b7) are set
to one, which resets the Rx and Tx circuits, respectively. The TxAbort (CR4b5), RTS (CR2b7), Loop
Mode (CR3b5), and Loop on Line/DTR (CR367) are reset to zero.
All initial status conditions are reset. The RTS and LOC/DTR output pins are set to High when the
corresponding control registers are reset, and the TxD output is placed in Mark Idle state.
While the RESET inputs is kept at Low, none of the control register bits mentioned above can be
updated. If the RESET input is set to High, the reset condition continues until CR1b6 and CR1b7 are
reset to zeros by software.
(RESET Input)
to one, which resets the Rx and Tx circuits, respectively. The TxAbort (CR4b5), RTS (CR2b7), Loop
Mode (CR3b5), and Loop on Line/DTR (CR367) are reset to zero.
All initial status conditions are reset. The RTS and LOC/DTR output pins are set to High when the
corresponding control registers are reset, and the TxD output is placed in Mark Idle state.
While the RESET inputs is kept at Low, none of the control register bits mentioned above can be
updated. If the RESET input is set to High, the reset condition continues until CR1b6 and CR1b7 are
reset to zeros by software.
(RESET Input)
In
9
CS
Chip Select input. Read/write access to the device is enabled only if this input is Low and the Enable
input is High.
(Chip Select Input)
input is High.
(Chip Select Input)
In
10
11
11
RS0
RS1
RS1
Register Select inputs. These inputs are used with the R/W input (CR1b0) to address a register within
the device for read/write access.
(Register Select Input)
the device for read/write access.
(Register Select Input)
In
12
R/W
Read/Write Control input used to indicate the tha direction of the data flow.
The Data I/O buffer is placed in the Output mode if this input is High; it is placed in Input mode if this
Low.
(Read/Write Control Input)
The Data I/O buffer is placed in the Output mode if this input is High; it is placed in Input mode if this
Low.
(Read/Write Control Input)
In
13
E
Enable Clock input used to time the CS, RS0, RS1, and R/W inputs. Data read/write access to the
device is enabled only if this input is kept high.
This pin is also used for data transfer through the RxFIFO of TxFIFO.
(Enable Clock Input)
device is enabled only if this input is kept high.
This pin is also used for data transfer through the RxFIFO of TxFIFO.
(Enable Clock Input)
In
14
VCC
This pin accepts a +5V power supply.
(Voltage Source)
(Voltage Source)
I/O
15
∼
22
D7 – D0
Bidirectional data bus used to transfer data with the system. It is a three-state bus except during Read
access.
(Data Bus)
access.
(Data Bus)
I/O
23
RDSR
Receive Data Service Request output. This pin reflects the value of ST1b0. A high state of this pin
indicates that the RxFIFO is in request for service.
When the RxFIFO is read, the RDSR outputs is reset to Low. (The RxFIFO here refers to the one
(CR2b1 = 0) or two (CR2b1 = 1) nearest to the data bus.)
When in the Preferred Status mode (CR2b0 = 1) , this pin is kept Low as long as the other status
condition exists.
(Receive Data Service Request Output)
indicates that the RxFIFO is in request for service.
When the RxFIFO is read, the RDSR outputs is reset to Low. (The RxFIFO here refers to the one
(CR2b1 = 0) or two (CR2b1 = 1) nearest to the data bus.)
When in the Preferred Status mode (CR2b0 = 1) , this pin is kept Low as long as the other status
condition exists.
(Receive Data Service Request Output)
Out
24
TDSR
Transmitter Data Service Request output. This pin outputs the value of ST1b6 in any mode other than
the FC mode (CR2b3 = 1). A high state of this pin indicates that the TxFIFO requests service. When
data is written into the TxFIFO, the RDSR is reset to Low. (The TxFIFO here refers to the one (CR2b1
= 0) or two (CR2b1 = 1) nearest to the data bus.)
This pin is kept Low when the RESET pin is at an active Low. CTS pin is High, or CR1b7 is High.
When in the Preferred Status mode (CR2b0 = 1), this pin is also kept High if the Tx-Underrun condition
exists.
(Transmitter Data Service Request Output)
the FC mode (CR2b3 = 1). A high state of this pin indicates that the TxFIFO requests service. When
data is written into the TxFIFO, the RDSR is reset to Low. (The TxFIFO here refers to the one (CR2b1
= 0) or two (CR2b1 = 1) nearest to the data bus.)
This pin is kept Low when the RESET pin is at an active Low. CTS pin is High, or CR1b7 is High.
When in the Preferred Status mode (CR2b0 = 1), this pin is also kept High if the Tx-Underrun condition
exists.
(Transmitter Data Service Request Output)
Out
25
FD
Flag Detect output. This pin remains Low for a one-bit time interval (while Receiver Clock = RxC) after
the last flag bit is detected.
(Flag Detect Output)
the last flag bit is detected.
(Flag Detect Output)
Out
– 71 –
Pin No.
Symbol
Pin name and function
Input/
Output
26
LOC/DTR Loop
On
Line
Control/Data Terminal Ready output. This pin functions as the DTR in any mode other
than Loop mode (CR3b5 = 0). It is set Low if CR3b7 is set to one, and is set High when the same bit is
set to zero.
When in the Loop mode (CR3b5 = 1), this pin functions as the LOC, which is used to control the
external loop interface hardware between On Loop and Off Loop.
If CR3b7 is set to zero, this pin is set High when RxD = 01111111 is detected, causing the hardware to
go into the On Loop. If CR3b7 is set to zero, this pin is set High when RxD = 11111111 is detected,
causing the hardware to return to the Off Loop.
If the RESET input is set Low, CR3b5 is set to zero (Non-Loop Mode), which sets CR3b7 to zero. As a
result, this pin issues a High level signal.
(Loop On Line Control/Data Terminal Ready Output)
set to zero.
When in the Loop mode (CR3b5 = 1), this pin functions as the LOC, which is used to control the
external loop interface hardware between On Loop and Off Loop.
If CR3b7 is set to zero, this pin is set High when RxD = 01111111 is detected, causing the hardware to
go into the On Loop. If CR3b7 is set to zero, this pin is set High when RxD = 11111111 is detected,
causing the hardware to return to the Off Loop.
If the RESET input is set Low, CR3b5 is set to zero (Non-Loop Mode), which sets CR3b7 to zero. As a
result, this pin issues a High level signal.
(Loop On Line Control/Data Terminal Ready Output)
Out
28
CTS
Clear to Send input. Setting this pin to High disables ST1b6 and related IRQ.
If SR1b4 is set and this pin is enabled, an IRQ is issued. Low-to-High transition at the CTS input is set
in SR1b4, which is cleared by CR2b6 or CR1b7.
(Clear to Send Input)
If SR1b4 is set and this pin is enabled, an IRQ is issued. Low-to-High transition at the CTS input is set
in SR1b4, which is cleared by CR2b6 or CR1b7.
(Clear to Send Input)
In
27
DCD
Loop On Line Control/Data Terminal Ready output. Setting this pin to High resets the Receiver register
and sets SR2b5, which causes an IRQ to be issued if enabled. Low-to-High transition at the DCD input
is set in ST2b5, which cleared by CR2b5 or CR1b6.
(Loop On Line Control/Data Terminal Ready Output)
and sets SR2b5, which causes an IRQ to be issued if enabled. Low-to-High transition at the DCD input
is set in ST2b5, which cleared by CR2b5 or CR1b6.
(Loop On Line Control/Data Terminal Ready Output)
In
3) Pin Configuration (top view)
Fig. 26
8. Modulator/Demodulator circuit
Phase encoding (PE) modulation is used for SRN communications.
The PE modulation has a changing point in the signal at the center of
the bit, the timing signal is regenerated from this signal, making the
modulation and demodulation simplier by providing continuous sig-
nals for the DC components.
The PE modulation has a changing point in the signal at the center of
the bit, the timing signal is regenerated from this signal, making the
modulation and demodulation simplier by providing continuous sig-
nals for the DC components.
Fig. 27 PE Modulation
Serial send data applied from the ADLC to TXD (pin 72) of the
MB62H149 and the TXC synchronization signal is subject to PE
modulation. The resulting signal is output through TDI (pin 67) of the
MB62H149 to the transmission driver.
Received data is applied from the receiver to RDI (pin 66) of the
MB62H149, where it is demodulated into serial receive data and syn-
chronization clock. They are output to the ADLC through RXS (pin 70)
and RXC (pin 69), respectively.
The modulator and demodulator are located within the MB62H149.
MB62H149 and the TXC synchronization signal is subject to PE
modulation. The resulting signal is output through TDI (pin 67) of the
MB62H149 to the transmission driver.
Received data is applied from the receiver to RDI (pin 66) of the
MB62H149, where it is demodulated into serial receive data and syn-
chronization clock. They are output to the ADLC through RXS (pin 70)
and RXC (pin 69), respectively.
The modulator and demodulator are located within the MB62H149.
9. Transmitter and Receiver Circuits
1) Transmitter
The modulated send data output through TDI (pin 67) of the
MB62H149 is controlled by the RTS (Request to Send) signal trans-
ferred from the ADLC during transmission.
The TDI is NAND’ed with RTS, so that data transmission is disabled
when the RTS is high.
RTS is Low state during transmission and Transistor Q3 is turned ON.
When transmitting data "1", the output at pin 12 of the NAND gate
(IC45) is set Low. (the RTS is Low) Since pin 11 of the following
transistor (IC45) is set Low, it is turned off.
When the RTS is set Low, transistor Q4 is turned on through an
inverter, which applies a bias current to Q3, turning it on. When Q3
and pins 10 and 9 of IC7 are turned on, the output transistors IC45
(pins 6 and 5) is turned on. Since the output transistor is a common-
emitter circuit, data "1" is obtained at LINE.
MB62H149 is controlled by the RTS (Request to Send) signal trans-
ferred from the ADLC during transmission.
The TDI is NAND’ed with RTS, so that data transmission is disabled
when the RTS is high.
RTS is Low state during transmission and Transistor Q3 is turned ON.
When transmitting data "1", the output at pin 12 of the NAND gate
(IC45) is set Low. (the RTS is Low) Since pin 11 of the following
transistor (IC45) is set Low, it is turned off.
When the RTS is set Low, transistor Q4 is turned on through an
inverter, which applies a bias current to Q3, turning it on. When Q3
and pins 10 and 9 of IC7 are turned on, the output transistors IC45
(pins 6 and 5) is turned on. Since the output transistor is a common-
emitter circuit, data "1" is obtained at LINE.
Fig. 28
CTS
DCD
DTR/LOC
FD
TDSR
RDSR
D0
D1
D1
D2
D3
D4
D4
D5
D6
D7
D7
28
27
26
25
24
23
22
21
21
20
19
18
18
17
16
15
15
1
2
3
4
5
6
7
8
8
9
10
11
11
12
13
14
14
VSS
RTS
RXD
RXC
TXC
TXD
IRQ
RESET
CS
RS0
RS1
RS1
R/W
E
VCC
Data
NRZ
PE
0
1
1
0
0
1
1
0
SN75450BN
LINE
GND
R4
15
R3
150
4
5
6
IC45
+12V
R314
820
R315
1K
R316
560
Q4
1
13
12
45
SN75450 BN
RTS
TDI
11
10
9
R317
220
R312
470
+5V
IC7
RTS
TDI
Q3
– 72 –
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