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CS3 : Option RAM disk

700000H 

∼

 77FFFFH (512K x 8 PSRAM)

CS7 : Option RAM disk

780000H 

∼

 7FFFFFH (512K x 8 PSRAM)

CS0 : Option RAM disk

800000H 

∼

 87FFFFH (512K x 8 PSRAM)

CS4 : Option RAM disk

880000H 

∼

 8FFFFFH (512K x 8 PSRAM)

Adjust the backlight brightness with the control knob. 

Fig. 1 SRN controller board block diagram

Fig. 1 shows the block diagram of the controller board of the SHARP
RETAIL NETWORK. The Controller is connected to the system bus of
the host system as one of I/O. The Inside of the controller consists of
a Z-80 CPU, transmission link controller, DMA control circuit, ROM,
RAM, modulator, demodulator, carrier detection circuit,  collision de-
tect circuit and so on.
Data communications with the host system is performed by hand-
shaking. The controller side functions with DMA (Direct Memory Ac-
cess) and is capable of data transmission without waiting for the host
system side.

Pin Connections (C-MOS Version used)

Pin

Signal name

Input/

Output

Description

1

A11

Out

Address Bus A11

2

A12

Out

Address Bus A12

3

A13

Out

Address Bus A13

4

A14

Out

Address Bus A14

5

A15

Out

Address Bus A15

6

φ

In

CLK4 (MHz)

7

D4

I/O

Data Bus D4

8

D3

I/O

Data Bus D3

9

D5

I/O

Data Bus D5

10

D6

I/O

Data Bus D6

11

VCC

—

+5V

12

D2

I/O

Data Bus D2

13

D7

I/O

Data Bus D7

14

D0

I/O

Data Bus D0

15

D1

I/O

Data Bus D1

16

INT

In

Interrupt

17

NMI

In

Non Maskable Interrupt

18

HALT

Out

HALT

19

MREQ

Out

Memory Request

20

IOREQ

Out

I/O Request

21

RD

Out

Read

22

WR

Out

Write

23

BUSAK

Out

Bus acknowledge

24

WAIT

In

WAIT

25

BUSRQ

In

Bus Request

26

RES

In

Reset

27

M1

Out

M1 cycle

28

RFSH

Out

Refresh

29

GND

—

GND

30

A0

Out

Address Bus A0

31

A1

Out

Address Bus A1

32

A2

Out

Address Bus A2

33

A3

Out

Address Bus A3

34

A4

Out

Address Bus A4

35

A5

Out

Address Bus A5

36

A6

Out

Address Bus A6

37

A7

Out

Address Bus A7

38

A8

Out

Address Bus A8

39

A9

Out

Address Bus A9

40

A10

Out

Address Bus A10

PRAS1E

RA20

RA21

PRAS1O

PSC

A

B

G

CS0

CS3

Y0

Y3

Decorder

A

B

G

CS4

CS7

Y0

Y3

Decorder

Main PWB

Option RAM disk PWB

RSC

BKLT

20K

+12V

Invator PWB

Invator
connector

DATA BUS

CONTROL BUS

BUS BUFFER

D B

CONT

EXTERNAL

CABLE

HOST SYSTEM

BUS

RAM

DMA

CONTROLLER

CARRIER

DETECTION

COLLISION

DETECTION

CPU: Z80

ROM

CLOCK

CIRCUIT

MODULATOR

TRANSMISSION

LINK

CONTROLLER

DEMODU-

LATOR

OPC1

– 61 –

The MB62H149 is a semi-custom LSI chip for the peripheral circuits in
the SRN (SHARP Retail Network), its main function is to communi-
cate data with the host CPU and control the peripheral circuits and
transmission control circuits of the Sub CPU (Z-80). Fig. 2. shows the
general configuration of the functions:

Fig. 2

Is used because data processing speeds vary and the timing of the
HOST CPU and SUB CPU do not synchronize, the MB62H149 is
used for data handshaking. When the data handshaking portion is
broken down, the system consists of a Write Signal from the HOST
CPU to the MB62H149, Read Signal from the MB62H149 of the SUB
CPU, Write Signal from the SUB CPU to the MB62H149 and Read
Signal from the MB62H149 of the HOST CPU, all of which from two
blocks as shown.

Fig. 3

Fig. 4

The peripheral circuit consists of an I/O address generation unit on
the SUB CPU, block dividing circuit, and the wait signal control unit.

Fig. 5

(a)

I/O address generation circuit
A total of 11 I/O addresses are generated by A0, A1, A4, A5 and
RD and WR signals.

(b)

CPU and DMAC wait signal control unit
Clocks into the CPU (Z-80), SUB CPU and its peripheral LSI,
DMAC and CTC are operated respectively on 4 MHz.
While, the ADLC (MC68B54) (Advanced Data Link Control) is
operated by the E (Enable clock) of 2 MHz according to restric-
tions in terms of the hardware of the LSI.
It is necessary to synchronize the timing of the write and read in
the ADLC.
To control synchronization, timing, and input, the wait signal
goes into the CPU for CPU access and into the DMAC for DMA
access. This block is a circuit to generate such wait signal.

(c)

Clock dividing circuit
This block divides the blocks according to the CLK supplied from
outside to generate the clock for CPU, DMAC and CTC and the
E and transmission clock rate (480 KBPS or 1 MBPS selectable)
for the ADLC.

The transmission control circuit is divided into the modem unit, carrier
detect unit, collision detect unit.

Fig. 6

(a)

Modem circuit
The transmission data input from the ADLC are PE modulated
(phase encoding modulation), the circuit to be output to the
transmission driver and the reception data input from the trans-
mission receiver are demodulated and produced at the ADLC.

(b)

Collision detect circuit
The data transmitted from the home station is received and de-
tects a collision on the transmission line by means of an exclu-
sive OR gate.

(c)

Carrier detect circuit
This circuit detects whether data is flowing on the transmission
line. It consists of a circuit which immediately senses a no data
status on the line. When data is not on the line the circuit func-
tions to sense an elapse of the fixed time rate. The immediate
sensing circuit is used for response testing and the delayed
sensing circuit is used for data testing.
The fixed time rate is selectable according to the transmission
speed as shown below via SRV-mode programming. Job #922.

Transmission speed

Delay time

1 MBPS

1.6m sec, 3.2m sec, 4.8m sec, 6.4m sec.

480 KBPS

3.2m sec, 6.4m sec, 9.6m sec, 12.8m sec.

MB62H149

Line

TRANS-

MISSION

CONTROL

CIRCUIT

PERIPHERAL

CIRCUIT

DATA HAND

SHAKING

CIRCUIT

TIMER

COUNTER

SUB-CPU

(Z-80)

DMAC

(µPD8527)

ADLC

HOST CPU

HOS T CPU

MB62H149

SUB CPU

Write

Read

(HOST CPU TO S UB CPU)

(FROM SUB CPU TO HOST CPU)

HOS T CPU

MB62H149

SUB CPU

Write

Read

HOST CPU

DATA BUS

(8bit)

HOST CPU address

and RD, WR

SUB CPU

DATA BUS

(8bit)

HOST CPU · SUB CPU

& DMAC control

HOST CPU

address

decode

SUB CPU

write register

(HOST CPU

read register)

HOST CPU

write register

(SUB CPU

read register)

SUB CPU

write & HOST

CPU read control

unit (DMA &

CPU access)

HOST CPU

write & SUB

CPU read

control unit

(DMA & CPU

access)

CLK (16 MHz)

I/O address

Wait signal

SUB CPU address

& RD, WR

SUB CPU address

decoding unit

CPU & DMAC wait

signal control unit

Clock dividing

circuit

System clock

(4 MHz)

ADLC TDY

ADLC RDX

Collision detect

To transmission driver

From transmission receiver

Carrier detect 1

(for data)

Carrier detect 2

(for resronse)

MODEM unit

Collision

detect unit

Carrier

detect unit

– 62 –

Fig. 7

Pin

No.

Terminal

name

Host/

Sub

In/

Out

Description

1

CLK

Sub

In

Clock in (16 MHz)

2

—

—

—

N.U.

3

IORQ

Sub

In

I/O request

4

MREQ

Sub

In

Memory request

5

RDS

Sub

In

Read from sub

6

WRS

Sub

In

Write from sub

7

INTS

Sub

Out

Interrupt to sub

8

φ

Sub

Out

Clock out

9

TM0

Sub

In

Timer 0

10

TM1

Sub

Out

Timer 1

11

MRD

Sub

Out

Memory read

12

VSS

—

—

GND

13

WAIT

Sub

Out

Wait signal

14

A15

Sub

Out

Address bus for DMA

16

A9

Sub

Out

17

A8

Sub

Out

18

A5

Sub

In

19

A4

Sub

In

20

A1

Sub

In

21

A0

Sub

In

22

DAK01

Sub

In

DMA acknowledge 0+1

23

—

—

—

N.U.

24

MWR0

Sub

Out

Memory write

25

D7

Sub

I/O

Data bus

26

D6

Sub

I/O

27

D5

Sub

I/O

28

D4

Sub

I/O

29

D3

Sub

I/O

30

D2

Sub

I/O

31

D1

Sub

I/O

32

D0

Sub

I/O

33

VDD

—

—

+5V

34

—

—

—

N.U.

35

RES

Host

In

Reset

36

IO/WR

Sub

I/O

I/O write

37

IO/RD

Sub

I/O

I/O read

38

AEN

Sub

In

Address enable from DMAC

Pin

No.

Terminal

name

Host/

Sub

In/

Out

Description

39

AST

Sub

In

Address strobe from DMAC

40

TCS

Sub

In

Terminal count

41

DAK23

Sub

In

DMA acknowledge 2+3

42

DRQRS

Sub

Out

DMA request read to sub

43

DRQWS

Sub

Out

DMA request write to sub

44

RDH

Host

In

Read from Host

45

WRH

Host

In

Write from Host

46

INTH

Host

Out

Interrupt to host

47

DAK

Host

In

DMA acknowledge from host

48

TCH

Host

In

Terminal count from host

49

DRQWH

Host

Out

DMA request read to host

50

DRQWH

Host

Out

DMA request write to host

51

CS

Host

In

Chip select from host

52

VSS

—

—

GND

53

—

—

—

N.U.

54

DB0

Host

I/O

Data bus

55

DB1

Host

I/O

Data bus

56

DB2

Host

I/O

Data bus

57

DB3

Host

I/O

Data bus

58

DB4

Host

I/O

Data bus

59

DB5

Host

I/O

Data bus

60

DB6

Host

I/O

Data bus

61

DB7

Host

I/O

Data bus

62

AB0

Host

In

Address bus from host

63

—

—

—

N.U.

64

AB1

Host

In

Address bus from host

65

COL

Sub

In

Collision detect signal

66

RDI

Sub

In

Receive data from receiver

67

TDI

Sub

Out

Transmmit data to driver

68

RTS

Sub

In

Request to send

69

RXC

Sub

Out

Receive clock to ADLC

70

RXD

Sub

Out

Receive data to ADLC

71

TXC

Sub

Out

Transmmit clock

72

TXD

Sub

In

Transmmit data

73

VDD

—

—

+5V

74

E

Sub

In

Enable clock to ADLC

75

IRQ

Sub

In

Interrupt request from ADLC

76

LCS

Sub

Out

Link controller chip select

77

—

—

—

N.U.

78

RS1

Sub

Out

Register select 1

79

RS0

Sub

Out

Register select 0

80

MSK

Sub

Out

Mask signal

Pin functions will be described for the host and sub system.

1

DB0—DB7 (data bus) Input/Output, 3-state
Pins 54—61
These lines (data bus) are use for hardware flag assignments:
8-bit data write, hardware flag recognition, and 8-bit data read
from the host.

2

RDH (Read from host), Input
Pin 44 
An active low signal which is used when the host reads the
hardware flag and 8-bit data through the data bus.

14

17.

9 ±

 

0.

4

20

23.9 ± 

0.6

0.8 ± 

0.15

0.35 ± 

0.1

INDEX

LEAD

NO

1

24

25

40

41

64

65

80

– 63 –

3

WRH (Write from sub), Input
Pin 45
An active low signal which is used when the host writes the
hardware flag and 8-bit data through the data bus.

4

CS (Chip select from host), Input
Pin 51
An active low signal which is used when the host reads or writes
the hardware flag and 8-bit data through the data bus.

5

AB0, AB1(Address bus from host), Input
Pin 62, 64
An input signal used to select the register when the host reads or
writes the hardware flag and 8-bit data through the data bus.

6

DAK (DMA Acknowledge from host), Input
Pin 47
Not used (+5v)

7

DRQRH (DMA Request read to host), Output
Pin 49
Not used

8

DRQWH (DMA request write to host), Output
Pin 50
Not used

9

TCH (Terminal count from host), Input
Pin 48
Not used

F 

INTH (Interrupt to host), Output
Pin 46
An active low signal which is used to inform the interrupt signal
that the controller has the information to read or write.

G

RES (Reset), Input
Pin 35
Asynchronous reset signal from the host which is used to reset
registers within the controller.

•

HOST read timing.

Fig. 8

•

HOST write timing.

Fig. 9

1

D0 – D7 (Data bus) Input Output (3-state)
Pin 32 – 25
These lines (data bus) are used for hardware flag assignments:
8 bit data write, hardware flag recognition, and 8-bit data read
from the subsystem.

2

IORQ (I/O request), Input
Pin 3
An active low memory request input from the subsystem (Z-80A)
which is used to create I/O control signals in conjunciton with
RDS, WRS, A0, A1, A4 and A5.

3

MREQ (Memory request), Input
Pin 4
An active low memory request input from the subsystem (Z-80A)
which is used to create I/O control signals in conjunction with
RDS and WRS.

4

RDS (Read from sub), Input
Pin 5
Data read signal received from the subsystem (Z-80A) wihch is
used to create I/O and memory data read control signal.

5

WRS (Write from sub), Input
Pin 6 
Data write signal received from the subsystem (Z-80A) which is
used to create I/O and memory data write control signal.

6

MRD (Memory read), Output
Pin 11
Memory data read control signal sent to the subsystem (mem-
ory) which is created with MREQ and RDS.

7

MWRO (Memory write), Output
Pin 24
Memory data write control signal sent to the subsystem (mem-
ory) which is created with MREQ and RDS.

8

IO/WR (I/O write), Input/Output (3-state)
Pin 36
I/O data write control signal sent to the subsystem (peripheral
I/O) which is created with IORQ And WRS.
During the DMA mode, it is received from the DMAC to create
the memory  to I/O data transfer control signal.

9

IO/RD (I/O read), Input/Output (3-state)
Pin 37
I/O data read control signal sent to the subsysystem (peripheral
I/O) which is created with IORQ and WRS. During the DMA
mode, it is received from the DMAC to create the I/O to memory
data transfer control signal.

F

AO, A1, A4, A5 (Address bus from sub CPU), In
Pin 21, 20, 19, 18
An input signal used to create the selection signal which the sub
reads the hardware flag and subsystem  (peripheral I/O) 8-bit
data through the data bus.

G

A8, A9, A10, A15 (Address bus for DMA), Output (3-state)
Pin 17, 16, 15, 14
Used to create the memory address information on the basis of
the information from the DMAC during the DMA cycle. The out-
put has 3-stats and retains a high impedance except during the
DMA cycle.

H

AEN (Address enable from DMAC), In
Pin 38
An input from the DMAC which is used to enable the DMAC to
control by isolating the system address bus from the CPU (Z-
80A) during the DMA cycle.
That is, A8, A9, A10, and A15 are set to output condition from
their high impedance state.

CS

AB0, AB1

RDH

DB0-DB7

TAR

TRWS

TRA

TRDE

TRDF

CS

AB0, AB1

WRH

DB0-DB7

TAW

TWWS

TWA

TDW

TWD

– 64 –