Sharp ER-A850 (serv.man2) Service Manual ▷ View online
Table 5. Signal States During RESET and Hold Acknowledge
SIGNAL
NAME
SIGNAL STATE
DURING RESET
SIGNAL STATE
DURING HOLD
ACKNOWLEDGE
A20M
Ignored
Input recognized
A23-A1
1
Float
ADS
1
Float
BHE, BLE
Float
BUSY
Initiates self test
Ignored
D15-D0
Float
Float
D/C
1
Float
ERROR
Ignored
Ignored
FLT
Input recognized
Input recognized
FLUSH
Ignored
Input recognized
HLDA
0
1
HOLD
Ignored
Input recognized
INTR
Ignored
Input recognized
KEN
Ignored
Ignored
LOCK
1
Float
M/IO
0
Float
NA
Ignored
Ignored
NMI
Ignored
Input recognized
PEREQ
Ignored
Ignored
READY
Ignored
Ignored
RESET
Input recognized
Input recognized
SMADS
Float
Float
SMI
Ignored
Input recognized
SUSP
Ignored
Input recognized
SUSPA
Float
Driven
W/R
0
Float
3-1-3. System controller (OTI-021)
1. Introduction
The OTI-021 is a custom integrated circuit designed to work with the
80286/80386SX/Cx486SLC microprocessor. The chip integrates all
the functions of CPU interface, data flow control, system and memory
address generation. The OTI-021, together with OTI-022 (Peripheral
Controller), can provide a very cost effective solution to implement a
high performance system which is fully compatible with IBM AT archi-
tecture. It is implemented with 1.0 micron HCMOS technology and
packaged in a 160-pin PQFP.
80286/80386SX/Cx486SLC microprocessor. The chip integrates all
the functions of CPU interface, data flow control, system and memory
address generation. The OTI-021, together with OTI-022 (Peripheral
Controller), can provide a very cost effective solution to implement a
high performance system which is fully compatible with IBM AT archi-
tecture. It is implemented with 1.0 micron HCMOS technology and
packaged in a 160-pin PQFP.
The OTI-021 features the following functions:
•
Supports 80286, 80386SX and Cx486SLC processors
•
Supports local bus programmable memory range
•
Supports cartridge ROM
•
Command state machine generates memory, I/O & Interrupt Ac-
knowledge commands
knowledge commands
•
Address and data path control that includes byte swapping for 16
bit to 8 bit memory or I/O devices
bit to 8 bit memory or I/O devices
•
Bus arbiter arbitrates the system bus between CPU, DMA, and
DRAM refresh requests
DRAM refresh requests
•
DMA support logic provides 7 channels of DMA page map address
and burst mode DMA
and burst mode DMA
•
Integrates all address buffers for the AT-bus
•
Supports fast reset to switch from protected mode to real mode for
optimized OS/2 operation
optimized OS/2 operation
•
System Speed:
–
supports 8MHz, 10MHz, 12.5MHz, 16MHz,
20MHz, 25MHz and 33MHz
20MHz, 25MHz and 33MHz
•
I/O Channel Speed:
–
equal to or one half of system speed in
synchronous mode, fixed at 8MHz in asyn-
chronous mode
synchronous mode, fixed at 8MHz in asyn-
chronous mode
•
Memory Control:
–
page mode for zero wait state cycles
–
supports 60ns to 120ns DRAMs
–
zero wait state ROM cycle with shadow
RAM
RAM
–
EMS 4.0 hardware with two maps of 60
registers each
registers each
–
supports 640 Kbytes of system memory,
up to 32Mbytes of total on-board memory
including extended/expanded memory
up to 32Mbytes of total on-board memory
including extended/expanded memory
–
slow/staggered/CAS-before-RAS refresh
•
DMA Control:
–
supports fast (8M) and normal (4M) DMA
modes with embedded 8237
modes with embedded 8237
•
Local bus Support:
–
high performance video with the OTI-087
on CPU bus
on CPU bus
•
Video BIOS:
–
on-board video BIOS at either E000 or
C000
C000
– 41 –
2. Pin Assignments
Fig. 1 OTI-021 Pin Assignment
SEL0
120
SEL1
119
RMRD
118
REFRQ
117
MEMWR
116
MEMRD
115
IOWR
114
IORD
113
CROMCS
112
INTA
111
PCALE
110
PCBHEN
109
PCA0
108
PCA1
107
PCA2
106
VSS
105
PCA3
104
PCA4
103
PCA5
102
VD D
101
PCA6
100
PCA7
99
PCA8
98
VSS
97
PCA9
96
PCA10
95
PCA11
94
PCA12
93
PCA13
92
PCA14
91
VSS
90
PCA15
89
PCA16
88
PCA17
87
VD D
86
PCA18
85
PCA19
84
LA17
83
LA18
82
LA19
81
BUS
C
L
K
16
0
MR
E
F
15
9
WS
0
15
8
CHGCL
K
15
7
XD0
15
6
XD1
15
5
XD2
15
4
XD3
15
3
XD4
15
2
VSS
15
1
XD5
15
0
XD6
14
9
XD7
14
8
IO
C
S
1
5
14
7
ME
MC
S
1
6
14
6
RW
RG0
0
D
14
5
IO
CHRDY
14
4
RES
E
T
14
3
TC
14
2
VSS
14
1
DAC
K
7
14
0
VDD
13
9
13
8
13
7
13
6
13
5
13
4
13
3
DRE
Q
7
13
2
13
1
13
0
12
9
12
8
VSS
12
7
12
6
12
5
PCE
N
12
4
ENP
A
R
12
3
ENS
W
AP
12
2
ROM
C
S
12
1
DAC
K
6
DAC
K
5
DAC
K
3
DAC
K
2
DAC
K
1
DAC
K
0
DRE
Q
6
DRE
Q
5
DRE
Q
3
DRE
Q
2
DRE
Q
1
DRE
Q
0
SA
2
2
4
1
SA
2
1
4
2
SA
2
0
4
3
SA
1
9
4
4
SA
1
8
4
5
VSS
46
SA
1
7
4
7
SA
1
6
4
8
SA
1
5
4
9
SA
1
4
5
0
SA
1
3
5
1
SA
1
2
5
2
SA
1
1
5
3
CP
UHL
D
A
5
4
NP
C
L
K
5
5
CP
UHRQ
5
6
CL
K
IN1
5
7
NP
RST
5
8
CL
K
IN0
5
9
VSS
60
CP
UCL
K
6
1
VD
D
6
2
SA
1
0
6
3
SA
9
64
SA
8
65
SA
7
66
SA
6
67
68
69
70
71
72
73
74
75
76
77
78
79
80
SA
5
SA
4
SA
3
SA
2
SA
1
SA
0
BH
E
LA
23
LA
22
LA
21
LA
20
VSS
VSS
VD D
1
GATEA20
2
RST8042
3
MWE
4
CASH3
5
CASH2
6
CASH1
7
CASH0
8
VSS
9
CASL3
10
CASL2
11
CASL1
12
CASL0
13
RAS3
14
RAS2
15
RAS1
16
RAS0
17
VDD
18
MA11
19
VSS
20
MA10
21
VSS
22
MA9
23
MA8
24
MA7
25
VD D
26
MA6
27
MA5
28
MA4
29
VSS
30
MA3
31
MA2
32
MA1
33
M/IO
34
SO/WR
35
SI/DC
36
ADS
37
SRDY
38
RESET CPU
39
SA23
40
– 42 –
3. Block Diagram
Fig. 2 OTI-021 Block Diagram
4. Pin Description (OTI-021)
***
CPU Interface
***
Name
Type
Pin No.
Description
SA23
∼
SA0
I/O
40
∼
45,
47
∼
53,
63
∼
67,
69
∼
74
CPU ADDRESS BUS:
Address bus from CPU.
These signals become
outputs during DMA or
MASTER mode.
Address bus from CPU.
These signals become
outputs during DMA or
MASTER mode.
BHEn
I/O
75
BYTE HIGH ENABLE: An
active low signal used to
enable data on to the most
significant half of the data
bus (D15
active low signal used to
enable data on to the most
significant half of the data
bus (D15
∼
D8). This signal
becomes an output during
DMA or MASTER mode.
DMA or MASTER mode.
RESETCPU
NPRST
NPRST
O
O
O
39
58
58
RESET CPU: An active high
output to reset the CPU.
CO-PROCESSOR RESET:
An active high signal to
reset the numerical
co-processor.
output to reset the CPU.
CO-PROCESSOR RESET:
An active high signal to
reset the numerical
co-processor.
ADSn
I
37
ADDRESS STROBE: An
active low signal coming
from 80386SX. This input is
also used to detect the
presence of 386SX.
active low signal coming
from 80386SX. This input is
also used to detect the
presence of 386SX.
S1
∼
S0
I
36
∼
35
BUS CYCLES STATUS:
These signals together with
M/IO are used to decode
different bus cycles. S0 and
S1 are connected to W/R-
and D/C- respectively.
These signals together with
M/IO are used to decode
different bus cycles. S0 and
S1 are connected to W/R-
and D/C- respectively.
M/IO
I
34
MEMORY OR I/O CYCLE:
An input signal from CPU
indicating whether the
present cycle is memory or
I/O access.
An input signal from CPU
indicating whether the
present cycle is memory or
I/O access.
Name
Type
Pin No.
Description
CPUCLK
O
61
CPU CLOCK: A CMOS
driven clock signal to the
80286/80386SX CPU. The
frequency is programmable
through index port 03 (hex.)
driven clock signal to the
80286/80386SX CPU. The
frequency is programmable
through index port 03 (hex.)
NPCLK
O
55
CO-PROCESSOR CLOCK:
Clock signal for 80287 or
80387SX. This clock can be
programmed to stop if
co-processor is not used.
Clock signal for 80287 or
80387SX. This clock can be
programmed to stop if
co-processor is not used.
SRDYn
O
38
SYSTEM READY: An active
low signal to acknowledge
the CPU that the data
transfer for either memory or
I/O is complete.
low signal to acknowledge
the CPU that the data
transfer for either memory or
I/O is complete.
***
DMA Interface
***
Name
Type
Pin No.
Description
DRQ0
∼
3, 5
∼
7
I
125
∼
126,
128
∼
132
DMA REQUEST: These
are asynchronous active
high channel request
inputs used by peripheral
devices to request DMA
service.
are asynchronous active
high channel request
inputs used by peripheral
devices to request DMA
service.
DACK0
∼
3, 5
∼
7
O
133
∼
138,
140
DMA ACKNOWLEDGE:
These are active low
signals to notify the
individual peripheral that
it has been granted a
DMA cycle.
These are active low
signals to notify the
individual peripheral that
it has been granted a
DMA cycle.
CPUHRQ
O
56
HOLD REQUEST: An
active high signal
connected directly to
HOLD of the CPU. This
signal is used by the chip
to request the bus from
the CPU.
active high signal
connected directly to
HOLD of the CPU. This
signal is used by the chip
to request the bus from
the CPU.
CPUHLDA
I
54
HOLD
ACKNOWLEDGE: An
active high signal
connected directly to
HLDA of CPU. This
signal is used by the chip
to determine if the bus
request has been
granted by the CPU.
ACKNOWLEDGE: An
active high signal
connected directly to
HLDA of CPU. This
signal is used by the chip
to determine if the bus
request has been
granted by the CPU.
TC
O
142
TERMINAL COUNT: An
active high output pulse
signal when the terminal
count for any DMA
channel is reached.
active high output pulse
signal when the terminal
count for any DMA
channel is reached.
***
BUS Interface
***
Name
Type
Pin No.
Description
PC (0
∼
19)
I/O
108
∼
106,
104
∼
102,
100
∼
98,
96
∼
91,
89
∼
87,
95
∼
94
PC BUS ADDRESS: These
are the latched version of
SA (0
are the latched version of
SA (0
∼
19) and become
input during MASTER mode.
LA (17
∼
23)
I/O
83
∼
81,
79
∼
76
UNLATCHED ADDRESS:
These are the unlatched
versions of SA (17
These are the unlatched
versions of SA (17
∼
23).
The bus become input when
MASTER- is active.
MASTER- is active.
MIOS0.S1
MASTERN
IOCHRDY
SRDYn
WS0n
IOCS16n,MEMCS16n
IOR/WRn
MEMRD/WRn
INTAn
PCENn
ENSWAPn
CROMCSn
ISA
Bus
Controller
EMS
Mapper
CLKIN0
RESET
&
Clock
Generator
CLKIN1
NPCLK
CPUCLK
BUSCLK
POWERGOOD
RST8042
NPRST
RESETCPU
RESET
2X
8237
DMA
DMA
Controllers
DRQ
DACK
TC
System
Address
Buffer
SA
PCA
LA
BHEn
GATEA20
SEL0.1
AT
DRAM
Controller
MA
MWEn
RASn
CASn
ENPARn
Refresh
Cycle
Generator
REFRQT
MREFN
DMA
Refresh
CPU
Cycle
Arbiter
CPUHRQ
CPUHLDA
– 43 –
Name
Type
Pin No.
Description
PBHEn
I/O
109
I/O CHANNEL BYTE HIGH
ENABLE: An active low
signal on the I/O channel. It
is a latched version of BHE-.
When MASTER- is low, it
becomes an input.
ENABLE: An active low
signal on the I/O channel. It
is a latched version of BHE-.
When MASTER- is low, it
becomes an input.
WS0n
I
158
ZERO WAIT STATE: An
active low signal indicating
the present cycle can be
completed without any more
wait state.
active low signal indicating
the present cycle can be
completed without any more
wait state.
IOCS16n
I
147
16-BIT I/O CHIP SELECT:
An active low signal
indicates to the system that
the present data transfer is a
1 wait-state, 16-bit I/O cycle.
An active low signal
indicates to the system that
the present data transfer is a
1 wait-state, 16-bit I/O cycle.
MEMCS16n
I
146
16-BIT MEMORY CHIP
SELECT: An active low
signal indicates to the
system that the present data
transfer is a 16-bit memory
cycle.
SELECT: An active low
signal indicates to the
system that the present data
transfer is a 16-bit memory
cycle.
PCALE
O
110
PC ADDRESS LATCH
ENABLE: An active high
pulse signal indicating the
start of any bus cycle and is
always high when the CPU
bus is held. It is
synchronized to BUSCLK.
ENABLE: An active high
pulse signal indicating the
start of any bus cycle and is
always high when the CPU
bus is held. It is
synchronized to BUSCLK.
IOCHRDY
I
144
I/O CHANNEL READY: An
active high ready signal from
an I/O channel. It is pulled
low by a memory or I/O
device to lengthen memory
or I/O cycles.
active high ready signal from
an I/O channel. It is pulled
low by a memory or I/O
device to lengthen memory
or I/O cycles.
RESET
O
143
RESET: An active high
signal synchronized to
CPUCLK to reset the whole
system.
signal synchronized to
CPUCLK to reset the whole
system.
IORDn
I/O
113
I/O READ COMMAND: An
active low command to
instruct the I/O device to
drive its data onto the data
bus. It is input when
MASTER- is active.
active low command to
instruct the I/O device to
drive its data onto the data
bus. It is input when
MASTER- is active.
IOWRn
I/O
114
I/O WRITE COMMAND: An
active low command to
instruct the I/O device to
read the data present on the
data bus. It is input when
MASTER- is active.
active low command to
instruct the I/O device to
read the data present on the
data bus. It is input when
MASTER- is active.
MEMRDn
I/O
115
MEMORY READ
COMMAND: An active low
signal to instruct the
memory subsystem to drive
its data onto the data bus. It
is input when MASTER- is
active.
COMMAND: An active low
signal to instruct the
memory subsystem to drive
its data onto the data bus. It
is input when MASTER- is
active.
MEMWRn
I/O
116
MEMORY WRITE
COMMAND: An active low
signal to instruct the
memory subsystem to store
the data present on the data
bus. It is input when
MASTER- is active.
COMMAND: An active low
signal to instruct the
memory subsystem to store
the data present on the data
bus. It is input when
MASTER- is active.
BUSCLK
O
160
PC-BUSCLOCK: A CMOS
driven clock signal for the
I/O channel.
driven clock signal for the
I/O channel.
***
System Interface
***
Name
Type
Pin No.
Description
INTAn
I/O
111
INTERRUPT
ACKNOWLEDGE: An
active low signal to enable
the interrupt controller’s
interrupt-vector data onto
the data bus.
ACKNOWLEDGE: An
active low signal to enable
the interrupt controller’s
interrupt-vector data onto
the data bus.
GATEA20
I/O
2
GATE20: An active high
signal from 8042 used to
gate address A20. If
GATEA20 trapping function
is enabled, this signal
becomes an output carrying
OR’ed result of port 64 and
port 92.
signal from 8042 used to
gate address A20. If
GATEA20 trapping function
is enabled, this signal
becomes an output carrying
OR’ed result of port 64 and
port 92.
RST8042n
I
3
RESET FROM 8042: An
active low signal from 8042
to reset the CPU.
active low signal from 8042
to reset the CPU.
CHGLKn
I
157
CHANGE SYSTEM SPEED:
An active low input signal
from OTI-022 indicating
power-savings modes.
An active low input signal
from OTI-022 indicating
power-savings modes.
PCENn/
WAKEUPn
WAKEUPn
O
124
PC DATA BUS ENABLE:
An active low control signal
to enable the data buffer
between CPU and PC data
bus.
PCENn is active low if:
1. CPU I/O read/write cycle,
except co-processor I/O.
2. CPU memory read/write
cycle, except on-board
RAM and ROM.
3. Interrupt acknowledge
cycle. (INTAn active)
This pin carries the
WAKEUPn information
during powerdown modes.
An active low control signal
to enable the data buffer
between CPU and PC data
bus.
PCENn is active low if:
1. CPU I/O read/write cycle,
except co-processor I/O.
2. CPU memory read/write
cycle, except on-board
RAM and ROM.
3. Interrupt acknowledge
cycle. (INTAn active)
This pin carries the
WAKEUPn information
during powerdown modes.
ENSWAPn
O
122
ENABLE DATA SWAP: An
output to control the output
enable of the byte swapping
data buffer.
output to control the output
enable of the byte swapping
data buffer.
ROMCSn
O
121
ROM CHIP SELECT: An
active low signal used to
enable the ROM BIOS to
output data on to the data
bus.
active low signal used to
enable the ROM BIOS to
output data on to the data
bus.
CROMCSn
O
112
CARTRIDGE ROM CHIP
SELECT: An active low
output signal used to access
the cartridge ROM.
SELECT: An active low
output signal used to access
the cartridge ROM.
SEL0
I/O
120
SELECT FUNCTION 0: One
of the two address encoding
signals.
of the two address encoding
signals.
– 44 –
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