Sharp ER-A850 (serv.man2) Service Manual ▷ View online
CHAPTER 5. CIRCUIT DESCRIPTION
1. Block diagram
2. Memory control
The figure below shows the overall map of the physical memory area.
*1: Bios ROM is copied to address FC0000H
∼
FCFFFFH and
F00000H
∼
FFFFFFH. (Address 0C0000H
∼
0CFFFFH and ad-
dress 0F0000H
∼
0FFFFFH are overlapped and decoded. If,
however, BIOS setting is in shadow enable mode, an access to
the BIOS ROM is inhibited by PSC.
the BIOS ROM is inhibited by PSC.
*2: An address area of 512KB in F00000H
∼
F7FFFFH is reserved
for linear acceleration which is a feature of the VGA controller
(F65510).
(F65510).
*3:
This area is to make an access to the system ROM. Located to
E00000H
E00000H
∼
EFFFFFH.
ER-03MB: 1MB
ER-04MB: 2MB
ER-04MB: 2MB
*4:
An address area of 2MB in address 700000H
∼
8FFFFFH is
defined as the expansion RAM disk. This area is the reserved
area of option memory composed of battery-backed-up SRAM,
and is used when the data area or the application area becomes
greater. In the architecture, however, 8MB of 700000H
area of option memory composed of battery-backed-up SRAM,
and is used when the data area or the application area becomes
greater. In the architecture, however, 8MB of 700000H
∼
DFFFFFH is defined.
*5:
An address area of 1MB in 600000H
∼
6FFFFFH is defined as
the standard RAM disk. It is composed of battery-backed-up
pseudo-SRAM, and is used to store standard application files
and data files.
pseudo-SRAM, and is used to store standard application files
and data files.
BIOS ROM
CPU
27C120
1Mbit
1Mbit
TI486SLC
50MHz
50MHz
32MHz
Chip set
System controler
OTI-021
14.318MHz
Chip set
Peripheral
controller
controller
OTI-022
80C42-85
AT key
controller
controller
RTC
32.768
32.768
8MHz
F65510
VGA
controller
controller
14.318MHz
50MHz
1.843MHz
24MHz
32MHz
16MHz
OSC
14.318MHz
LOCAL
DRAM
1MB x 2pcs
(256KB x 16) x 2
(256KB x 16) x 2
14.318MHz
ISA bus
controller
ISA
monitor PWB
PS2
keyboard
keyboard
Video RAM
ER-A880: 50MHz
ER-A850: 24MHz
(256KB x 16) x 1pcs
LCD
POS controller
1.843MHz
IO controller
Buzzer
Clerk key I/F
circuit
MCR I/F
circuit
POS key I/F
circuit
Main PWB
IOC PWB
RAM disk
1MB
RS232 I/F
circuit
Drawer drive
circuit
Option display
I/F circuit
SRN I/F circuit
16MHz
PC-AT section
POS section
System ROM
512KB
8MHz
VGA RESERVE
BIOS AREA
SYSTEM ROM AREA
RESERVE
EXPANTION RAM DISK AREA
STANDARD RAM DISK AREA
MAIN MEMORY
EXTEND LOCAL DRAM
AREA
SIMM 1M x 16
EXTEND LOCAL DRAM
AREA
SIMM 1M x 16
100000H
0H
500000H
600000H
300000H
700000H
900000H
E00000H
F00000H
FFFFFFH
*1
*2
*3
*4
*5
*6
*7
BANK3 used
BANK2 used
BANK0/1 used
Refer to the real mode memory map
– 29 –
*6:
An address area of 8MB in 100000H
∼
5FFFFFH is defined as
the expansion area of main memory. IT is realized by making
bank 2/3 of local memory on the main board be of SIMM socket
type.
In the ER-A850/880, it can be expanded up to 4MB in each bank
as shown below.
bank 2/3 of local memory on the main board be of SIMM socket
type.
In the ER-A850/880, it can be expanded up to 4MB in each bank
as shown below.
Bank 1: 100000H
∼
2FFFFFH when 1M
×
16 bit DRAM module
is installed.
Bank 2: 300000H
∼
4FFFFFH when 1M
×
16 bit DRAM module
is installed.
*7:
The standard area of main memory 0H
∼
09FFFFH is used as
the conventional memory of DOS. When the shadow RAM fea-
ture is not used, 384KB of 0A0000H
ture is not used, 384KB of 0A0000H
∼
0FFFFFH can be re-
mapped to the highest location in main memory (that is, above
100000H in the standard, and above 300000H or above
500000H when an expansion memory is installed.) For remap-
ping, the memory size is automatically set by the AT chip set
register according to the BIOS setup.
Bank control of the main memory (DRAM local memory) is as-
signed as follows:
100000H in the standard, and above 300000H or above
500000H when an expansion memory is installed.) For remap-
ping, the memory size is automatically set by the AT chip set
register according to the BIOS setup.
Bank control of the main memory (DRAM local memory) is as-
signed as follows:
Bank 0: 256K
×
16 (512KB) One chip of 2CAS type DRAM is
used.
Bank 1: 256K
×
16 (512KB) One chip of 2CAS type DRAM is
used.
Bank 2: 1M
×
16 (2MB)
Two 30-pin SIMM modules of 1M
×
8 are used.
Bank 3: 1M
×
16 (2MB)
Two 30-pin SIMM modules of 1M
×
8 are used.
The figure below shows the real mode memory map.
*1:
The ROM which includes the IBM-PC standard BIOS as well as
the VGA BIOS is located. The address location on the ROM is
the same as that after shadow.
the VGA BIOS is located. The address location on the ROM is
the same as that after shadow.
*2:
After enabling shadow RAM, the standard BIOS and the VGA
BIOS are copied to a local memory.
BIOS are copied to a local memory.
*3:
The standard BIOS is located.
*4:
The expansion adapter area is located for use by the EMS win-
dow or the PCMCIA BIOS and its window.
dow or the PCMCIA BIOS and its window.
*5:
The VGA BIOS is located.
*6:
Frame window 128KB for VRAM is located.
*7:
The conventional memory 640KB of DOS is located.
The I/O area map conforms to the IBM-PC AT I/O map. The I/O port
used as the standard I/O of the ER-A850/A880 is decoded and con-
trolled in the PSC (POS System Controller) so that it can be relocated
on the expansion I/O. That is, addressing can be made arbitrarily by
setting a relocatable base value to the SSR register built in the PSC.
used as the standard I/O of the ER-A850/A880 is decoded and con-
trolled in the PSC (POS System Controller) so that it can be relocated
on the expansion I/O. That is, addressing can be made arbitrarily by
setting a relocatable base value to the SSR register built in the PSC.
The figure below shows the I/O map.
*1:
*2:
*3:
*3:
Not used because areas *4 and *5 are overlapped since full
decoding is not performed in the IBM-PC specifications.
decoding is not performed in the IBM-PC specifications.
*4:
This area is for I/O device of IBM-PC AT specifications on the
expansion slot, and the unique I/O for the ER-A850/A880 is also
located arbitrarily.
expansion slot, and the unique I/O for the ER-A850/A880 is also
located arbitrarily.
*5:
The system I/O device on the mother board of IBM-PC AT speci-
fications is located and is used as an internal I/O such as a chip
set of OAK.
fications is located and is used as an internal I/O such as a chip
set of OAK.
CONVENTIOANAL MEMORY
640KB
VRAM 128KB
BIOS ROM
128KB
*1
0FFFFFH
0C0000H
0A0000H
0H
CONVENTIOANAL MEMORY
640KB
VRAM 128KB
ADAPTER SLOT AREA
(128KB)
0FFFFFH
0C0000H
0A0000H
0H
STANDARD BIOS (64KB)
*3
*4
*5
*6
VGA BIOS (64KB)
0D0000H
0F0000H
*7
COPY
*2
COPY
When resetting
After enabling the shadow RAM
CAN'T USED
*1
CAN'T USED
*3
CAN'T USED
*2
CAN'T USED
*3
CAN'T USED
*2
CAN'T USED
*3
CAN'T USED
*2
00FFFFH
000FFFH
000D00H
000C00H
000900H
000800H
000500H
000400H
000100H
0H
IBM-PC EXPAND
I/O AREA
I/O AREA
SYSTEM I/O AREA
*4
*5
– 30 –
3. Main PWB circuit description
3-1. PC-AT section
3-1-1. Block diagram
2BANKS
DRAM
BIOS ROM
32MHz, 50MHz
SA0~23
BHE
BHE
SB0~15
GATE20
SD0~15
SD0~SD15
SA0~23 BHE
SD0~15
SA0~23 BHE
SRDY,CPUHRQ
CPUCLK,RESETCPU
CPUCLK,RESETCPU
ADS,MXIO,W/R,D/C
CPUHLDA
CPUHLDA
CPUHLDA
SD0~15
NMI
CPUBUSY,CPEREQ,
FGA20,FLUSH,INTR
CPUBUSY,CPEREQ,
FGA20,FLUSH,INTR
R
AS,
C
A
S
MA
1~
11
MW
E
GA
T
E
2
0
ROMCS RMRD
ME
MW
R
, M
R
E
F
IOW
B
, M
E
M
R
D
PC
BH
E,
I
O
R
D
PC
A0
~
1
9
, L
A
1
7
~
2
3
BU
SC
L
K
T
C
, PC
AL
E,
R
ESET
D
A
C
K
0
~
3,
5~
7
RE
F
R
Q
EN
SW
AP,
PC
EN
IN
T
A
, RM
RD
IOC
K
R
ESET
, D
A
C
K
2
PC
BH
E,
M
R
EF
M
AST
ER
, PC
A0
~
9
ME
MR
D
, M
E
MW
R
IOR
D
, IOW
R
P
CD0
~
1
5
AEN
PCD0~15
XD0~XD7 IRQ1
XD0~XD7 IRQ1
SELKBD
14.318MHz
32.768KHz
24MHz
GATE20
8.00MHz
P2
7
/D
A
C
K
P2
6
/D
R
Q
KEY CN
AT KEYBOARD
IO
C
S
1
6
, M
E
M
C
S
1
6
, IOC
H
R
D
Y
D
R
Q
0~
3
, 5~
7
, O
W
S
PC
A0
~
1
8
SEL
KBD
X
D
0~
7 I
R
Q
1
R
ESET
, PC
A2
,
IO
R
D
, I
O
WR
PC
A0
~
1
8
ME
MW
R
, M
E
M
R
D
A
E
N
,
IO
W
R
, IOR
D
R
ESET
, M
R
EF
, PC
BH
E
P
CD0
~
1
5
EN
AVEE
Contrast
OTI-021
OTI-22
AT key
controller
VG A
controller
50MHz
: ER-A850
: ER-A880
Video
RAM
MA0~8
MD0~15
CASL, RAS
WE, CASH
WE, CASH
DL1~3
DU0~3,
S, CP1, CP2
DU0~3,
S, CP1, CP2
Display
DISP CN
VEE
ISABUS CN
OSC
14.318M
ISA connector
1.843M
PSC
RS-232 CIRCUIT
RS-232 CIRCUIT
50M
OTI-021
32M
OTI-021
16M
SRN circuit
24
VGA (Only ER-A850)
CPU
– 31 –
3-1-2. CPU (TI486SL C/E)
1. Introduction
The Texas Instruments TI486 microprocessor is an advanced x86-
compatible processor offering high performance and integrated power
management on a single chip.
compatible processor offering high performance and integrated power
management on a single chip.
The 486SLC/E is 486 instruction set compatible and is backward
compatible with the 386SX pinout. The TI486SLC/E provides up to
2.4 times the performance of both the 386SL and 386SX at equal
clock frequencies. The TI486SLC/E is an ideal solution for battery-
powered applications in that it typically draws 0.4 mA supply current
while the input clock is stopped in suspend mode.
compatible with the 386SX pinout. The TI486SLC/E provides up to
2.4 times the performance of both the 386SL and 386SX at equal
clock frequencies. The TI486SLC/E is an ideal solution for battery-
powered applications in that it typically draws 0.4 mA supply current
while the input clock is stopped in suspend mode.
The TI486 supports 8-, 16-, and 32-bit data types and operates in
real, virtual 8086, and protected modes. The TI486 microprocessor
achieves high performance through use of a highly optimized, vari-
able-length pipeline combined with a RISC-like single-cycle execution
unit, an on-chip hardware multiplier, and an integrated instruction and
data cache.
real, virtual 8086, and protected modes. The TI486 microprocessor
achieves high performance through use of a highly optimized, vari-
able-length pipeline combined with a RISC-like single-cycle execution
unit, an on-chip hardware multiplier, and an integrated instruction and
data cache.
2. Pin Assignments
The pin assignments for the TI486SLC/E are shown in Fig. 1. The
signal names are shown in Table 1 sorted by pin numbers and in
Table 2 sorted by signal names.
signal names are shown in Table 1 sorted by pin numbers and in
Table 2 sorted by signal names.
Fig. 1. TI486SLC/E Pin Assignments
1
D0
2
VSS
3
HLDA
4
HOLD
5
VSS
6
NA
7
READY
8
VCC
9
VCC
10
VCC
11
VSS
12
VSS
13
VSS
14
VSS
15
CLK2
16
ADS
17
BLE
18
A1
19
BHE
20
SMADS
21
VCC
22
VSS
23
M/IO
24
D/C
25
W/R
75
A20
74
A19
73
A18
72
A17
71
VCC
70
A16
69
VCC
68
VSS
67
VSS
66
A15
65
A14
64
A13
63
VSS
62
A12
61
A11
59
A10
58
A9
57
A8
56
VCC
55
A7
54
A6
53
A5
52
A4
51
A3
50
A2
100
D1
99
D2
98
V
S
S
97
V
C
C
96
D3
95
D4
94
D5
93
D6
92
D7
91
V
C
C
90
D8
89
D9
88
D10
87
D11
86
D12
85
V
S
S
84
V
C
C
83
D13
82
D14
81
D15
80
A
2
3
79
A
2
2
78
V
S
S
77
V
S
S
76
A
2
1
26
LO
CK
27
NC
28
FL
T
29
KE
N
30
FL
U
S
H
31
A
20M
32
VC
C
33
R
ESE
T
34
BU
SY
35
VSS
36
ER
R
O
R
37
PER
EQ
38
NM
I
39
VC
C
40
IN
T
R
41
VSS
42
VC
C
43
SU
SP
44
SU
SPA
45
NC
46
NC
47
SM
I
48
VC
C
49
VSS
50
VSS
(TOP VIEW)
– 32 –
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