Sharp ER-A850 (serv.man2) Service Manual ▷ View online
Table 1. TI486SL/E Signal Names Sorted by Pin Number
PIN
NO.
SIGNAL NAME
PIN
NO.
SIGNAL NAME
1
D0
51
A2
2
V
SS
52
A3
3
HLDA
53
A4
4
HOLD
54
A5
5
V
SS
55
A6
6
NA
56
A7
7
READY
57
V
CC
8
V
CC
58
A8
9
V
CC
59
A9
10
V
CC
60
A10
11
V
SS
61
A11
12
V
SS
62
A12
13
V
SS
63
V
SS
14
V
SS
64
A13
15
CLK2
65
A14
16
ADS
66
A15
17
BLE
67
V
SS
18
A1
68
V
SS
19
BHE
69
V
CC
20
SMADS
70
A16
21
V
CC
71
V
CC
22
V
SS
72
A17
23
M/IO
73
A18
24
D/C
74
A19
25
W/R
75
A20
26
LOCK
76
A21
27
NC
77
V
SS
28
FLT
78
V
SS
29
KEN
79
A22
30
FLUSH
80
A23
31
A20M
81
D15
32
V
CC
82
D14
33
RESET
83
D13
34
BUSY
84
V
CC
35
V
SS
85
V
SS
36
ERROR
86
D12
37
PEREQ
87
D11
38
NMI
88
D10
39
V
CC
89
D9
40
INTR
90
D8
41
V
SS
91
V
CC
42
V
CC
92
D7
43
SUSP
93
D6
44
SUSPA
94
D5
45
NC
95
D4
46
NC
96
D3
47
SMI
97
V
CC
48
V
CC
98
V
SS
49
V
SS
99
D2
50
V
SS
100
D1
Table 2. TI486SLC/E Pin Numbers Sorted by Signal Name
SIGNAL
NAME
PIN NO.
SIGNAL
NAME
PIN NO.
A1
18
HLDA
3
A2
51
INTR
40
A3
52
KEN
29
A4
53
LOCK
26
A5
54
M/IO
23
A6
55
NA
6
A7
56
NC
27
A8
58
NC
45
A9
59
NC
46
A10
60
NMI
38
A11
61
PEREQ
37
A12
62
READY
7
A13
64
RESET
33
A14
65
SMADS
20
A15
66
SMI
47
A16
70
SUSP
43
A17
72
SUSPA
44
A18
73
V
CC
8
A19
74
V
CC
9
A20
75
V
CC
10
A21
76
V
CC
21
A22
79
V
CC
32
A23
80
V
CC
39
ADS
16
V
CC
42
A20M
31
V
CC
48
BHE
19
V
CC
57
BLE
17
V
CC
69
BUSY
34
V
CC
71
CLK2
15
V
CC
84
D0
1
V
CC
91
D1
100
V
SS
97
D2
99
V
SS
2
D3
96
V
SS
5
D4
95
V
SS
11
D5
94
V
SS
12
D6
93
V
SS
13
D7
92
V
SS
14
D8
90
V
SS
22
D9
89
V
SS
35
D10
88
V
SS
41
D11
87
V
SS
49
D12
86
V
SS
50
D13
83
V
SS
63
D14
82
V
SS
67
D15
81
V
SS
68
D/C
24
V
SS
77
ERROR
36
V
SS
78
FLT
28
V
SS
85
FLUSH
30
V
SS
98
HOLD
4
W/R
25
– 33 –
3. TI486SLC/E Overview
The TI486SLC/E microprocessor is implemented using Texas Instru-
ments EPIC submicron CMOS technology and is available in 25-MHz
and 33-MHz versions. Both the 5-V TI486ßLC/E is packaged in a
100-pin bumpered quad flat pack (QFP).
ments EPIC submicron CMOS technology and is available in 25-MHz
and 33-MHz versions. Both the 5-V TI486ßLC/E is packaged in a
100-pin bumpered quad flat pack (QFP).
Fig. 2 is a functional block diagram of the TI486SLC/E. The
TI486SLC/E architecture results in up to 2.4 times the performance of
conventional 386SX notebook CPUs as listed below.
TI486SLC/E architecture results in up to 2.4 times the performance of
conventional 386SX notebook CPUs as listed below.
■
Up to 2.4 times faster than 386SX at same frequency
■
Landmark 2.0 = 107 MHz, Norton SI 6.0 = 52 at 33 MHz
Fig. 2. TI486SLC/E Functional Block Diagram
Decoder
16-byte
Instruction
queue
Sequencer
Microcode ROM
Execution unit
Limit
unit
Multiplier
unit
3-Input
adder
unit
Shift
unit
Register
file
Byte
muxes &
I/O
regs
Memory
management
unit
Prefetch
unit
1K Byte
instr/data
cache
Suspend
mode
control
SMM
control
Data
buffers
Bus
control
Address
buffers
Control
Immediate
ROM
address
address
Branch control
Control
Immediate
Execution pipeline
Cache and memory
management
management
Data address bus
Instruction
address bus
address bus
Memory
data bus
data bus
Core
clock
clock
Bus
clock
clock
32
Internal
data bus
data bus
SUSP
SUSPA
CLK2
SMI
SMADS
Enhanced 386SX
compatible
bus interface
compatible
bus interface
D15-D0
16
Control
A23-A1
BHE, BLE
TI486SLC/E Microprocessor
– 34 –
Fig. 3. TI486SLC/E Logic Symbol
The TI486SLC/E includes two power management signals (SUSP
and SUSPA), two cache interface signals (FLUSH and KEN), an A20
mask input (A20M), and two SMM signals (SMADS and SMI) that are
additions to the 386SX signal set. The complete list of TI486SLC/E
signals is shown in Fig. 4.
and SUSPA), two cache interface signals (FLUSH and KEN), an A20
mask input (A20M), and two SMM signals (SMADS and SMI) that are
additions to the 386SX signal set. The complete list of TI486SLC/E
signals is shown in Fig. 4.
Fig. 4. TI486SLC/E Input and Output Signals
Fig. 5. TI486SLC/E Functional Signal Groupings
CLK2
2x clock input
RESET
Reset
NMI
Non-maskable Req.
INTR
Maskable Req.
SMI
System magmt Int.
Interrupt
control
control
FLT
Float
KEN
Cache enable
FLUSH
Cache flush
Interna l
ca ch e
interface
ca ch e
interface
PEREQ
Extension Req.
BUSY
Extension busy
ERROR
Extension error
Coprocessor
interface
interface
SUSP
Suspend Req.
SUSPA
Suspend Ack.
Po wer
management
management
A20M
Address bit 2 0 mask
D0
0
D15
15
Data
HOLD
Hold request
READY
Bus ready
HLDA
Hold Ack.
Bu s
arbitratio n
arbitratio n
NA
Next address Req.
ADS
Address strobe
SMADS
SMM address strobe
Bu s
cycle
co ntrol
cycle
co ntrol
D/C
Data/control
M/IO
Memory I/O
W/R
Write/read
LOCK
Bus lock
Bu s
cycle
de finition
cycle
de finition
BHE
Byte high En.
BLE
Byte low En.
Byte
enables
enables
A1
1
A23
23
Address
Φ
MICROPROCESSOR
TI486SLC/E
A20M
BUSY
CLK2
ERROR
FLT
FLUSH
INTR
HOLD
KEN
NA
NMI
PEREQ
SUSP
READY
RESET
A23-A1
ADS
BHE
BLE
D15-D0
D/C
HLDA
LOCK
M/IO
SUSPA
SMADS
SMI
W/R
TI486SLC/E
Microprocessor
Internal cache interface
Power management
A20 mask
System management mode
INTR
NMI
SMI
Interrupt
control
control
KEN
FLUSH
Internal
cache
interface
cache
interface
PEREQ
BUSY
ERROR
Coprpcessor
interface
interface
A20M
HOLD
HLDA
bus
arbitration
arbitration
SUSP
SUSPA
Power
management
management
FLT
CLK2
RESET
A23-A1
Address
bus
bus
BLE
BHE
D15-D0
W/R
D/C
M/IO
LOCK
Bus
cycle
definition
cycle
definition
NA
READY
ADS
SMADS
Bus
cycle
control
cycle
control
TI486SLC/E
2x clock
Reset
Data bus
Address bit
20 mask
20 mask
Float
control
control
– 35 –
SIGNAL
SIGNAL NAME
SIGNAL GROUP
A20M
Address bit 20 mask
A23-A1
Address bus lines
Address bus
ADS
Address strobe
Bus cycle control
BHE
Byte high enable
Address bus
BLE
Byte low enable
Address bus
BUSY
Processor extension busy
Coprocessor interface
CLK2
2X clock input
D15-D0
Data bus lines
D/C
Data/control
Bus cycle definition
ERROR
Processor extension error
Coprocessor interface
FLT
Float
FLUSH
Cache flush
Internal cache interface
HLDA
Hold acknowledge
Bus arbitration
HOLD
Hold request
Bus arbitration
INTR
Maskable interrupt
request
request
Interrupt control
KEN
Cache enable
Internal cache interface
LOCK
Bus lock
Bus cycle definition
M/IO
Memory/input-output
Bus cycle definition
NA
Next address request
Bus cycle control
NMI
Non-maskable interrupt
request
request
Interrupt control
PEREQ
Processor extension
request
request
Coprocessor interface
READY
Busy ready
Bus cycle control
RESET
Reset
SMADS
SMM address strobe
Bus cycle control
SMI
System management
interrupt
interrupt
Interrupt control
SUSP
Suspend request
Power management
SUSPA
Suspend acknowledge
Power management
W/R
Write/read
Bus cycle definition
Table 3. TI486SLC/E Signal Summary
The following sections describe the signals and their functional timing
characteristics. Additional signal information may be found in Chapter
5, Electrical Specifications. Chapter 5 documents the dc and ac char-
acteristics for the signals including voltage levels, propagation delays,
setup times, and hold times. Specified setup and hold times must be
met for proper operation of the TI486.
characteristics. Additional signal information may be found in Chapter
5, Electrical Specifications. Chapter 5 documents the dc and ac char-
acteristics for the signals including voltage levels, propagation delays,
setup times, and hold times. Specified setup and hold times must be
met for proper operation of the TI486.
Table 4. Terminal Functions
PIN
NAME
PIN
NO
I/O
DESCRIPTION
A1
18
O/Z
Address Bus (active high). The address
bus (A23-A1) signals are 3-state outputs
that provide addresses for physical
memory and I/O ports. All address lines
can be used for addressing physical
memory allowing a 16 MByte address
space (00 0000h to FF FFFFh). During
I/O port accesses, A23-A16 are driven
low (except for coprocessor accesses).
This permits a 64 KByte I/O address
space (00 0000h to 00 FFFFh).
bus (A23-A1) signals are 3-state outputs
that provide addresses for physical
memory and I/O ports. All address lines
can be used for addressing physical
memory allowing a 16 MByte address
space (00 0000h to FF FFFFh). During
I/O port accesses, A23-A16 are driven
low (except for coprocessor accesses).
This permits a 64 KByte I/O address
space (00 0000h to 00 FFFFh).
During all coprocessor I/O access
address lines A22-A16 are driven low
and A23 is driven high. This allows A23
to be used by external logic to generate
a coprocessor select signal.
Coprocessor command transfers occur
with address 80 00F8h and coprocessor
data transfers occur with addresses 80
00FCh and 90 00FEh. A23-A1 float
while the CPU is in a hold acknowledge
or float state.
address lines A22-A16 are driven low
and A23 is driven high. This allows A23
to be used by external logic to generate
a coprocessor select signal.
Coprocessor command transfers occur
with address 80 00F8h and coprocessor
data transfers occur with addresses 80
00FCh and 90 00FEh. A23-A1 float
while the CPU is in a hold acknowledge
or float state.
A2
51
A3
52
A4
53
A5
54
A6
55
A7
56
A8
58
A9
59
A10
60
A11
61
A12
62
A13
64
A14
65
A15
66
A16
70
A17
72
A18
73
A19
74
A20
75
A21
76
A22
79
A23
80
ADS
16
O/Z
Address Strobe (active low). This is a
3-state output that indicates the TI486
has driven a valid address (A23-A1,
BHE, BLE) and bus cycle definition
(M/IO), D/C, W/R) on the appropriate
TI486SLC/E output pins. During
non-pipelined bus cycles, ADS is active
for the first clock of the bus cycle. During
address pipelining, ADS is asserted
during the previous bus cycle and
remains asserted until READY is
returned for that cycle. ADS floats while
the TI486SLC/E is in a hold
acknowledge or float state.
3-state output that indicates the TI486
has driven a valid address (A23-A1,
BHE, BLE) and bus cycle definition
(M/IO), D/C, W/R) on the appropriate
TI486SLC/E output pins. During
non-pipelined bus cycles, ADS is active
for the first clock of the bus cycle. During
address pipelining, ADS is asserted
during the previous bus cycle and
remains asserted until READY is
returned for that cycle. ADS floats while
the TI486SLC/E is in a hold
acknowledge or float state.
A20M
31
I
Address Bit 20 Mask (active low). This
input cases the TI486SLC/E to mask
(force low) physical address bit 20 when
driving the external address bus or
performing an internal cache access.
When the processor is in real mode,
asserting A20M emulates the 1 MByte
address wrap around that occurs on the
8086. The A20 signal is never masked
when paging is enabled regardless of
the state of the A20M input. The A20M
input is ignored following reset and can
be enabled using the A20M bit in the
CCR0 configuration register.
input cases the TI486SLC/E to mask
(force low) physical address bit 20 when
driving the external address bus or
performing an internal cache access.
When the processor is in real mode,
asserting A20M emulates the 1 MByte
address wrap around that occurs on the
8086. The A20 signal is never masked
when paging is enabled regardless of
the state of the A20M input. The A20M
input is ignored following reset and can
be enabled using the A20M bit in the
CCR0 configuration register.
A20M is internally connected to a pullup
resistor to prevent it from floating active
when left unconnected.
resistor to prevent it from floating active
when left unconnected.
– 36 –
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