Sharp ER-A850 (serv.man2) Service Manual ▷ View online
PIN
NAME
PIN
NO
I/O
DESCRIPTION
BHE
19
O/Z
Byte Enables (active low). Byte Low
Enable (BLE) and Byte High Enable
(BHE) are 3-state outputs that indicate
which byte(s) of the 16-bit data bus will
be selected for data transfer during the
current bus cycle. BLE selects the low
byte (D7-D0) and BHE selects the high
byte (D15-D8).
Enable (BLE) and Byte High Enable
(BHE) are 3-state outputs that indicate
which byte(s) of the 16-bit data bus will
be selected for data transfer during the
current bus cycle. BLE selects the low
byte (D7-D0) and BHE selects the high
byte (D15-D8).
When BHE and BLE are asserted, both
bytes (all 16 bits) of the data bus are
selected. BLE and BHE float while the
CPU is in a hold acknowledge or float
state.
bytes (all 16 bits) of the data bus are
selected. BLE and BHE float while the
CPU is in a hold acknowledge or float
state.
BHE = BLE = 1 never occurs during a
bus cycle.
bus cycle.
BLE
17
BUSY
34
I
Coprocessor Busy (active low). This is
an input from the coprocessor that
indicates to the TI486SLC/E that the
coprocessor is currently executing an
instruction and is not yet able to accept
another opcode. When the TI486SLC/E
processor encounters a WAIT
instruction or any coprocessor
instruction that operates on the
coprocessor stack (i.e., load, pop,
arithmetic operation), BUSY is sampled.
BUSY is continually sampled and must
be recognized as inactive before the
CPU will supply the coprocessor with
another instruction. However, the
following coprocessor instructions are
allowed to execute even if BUSY is
active since these instructions are used
for coprocessor initialization and
exception clearing: FNINIT, FNCLEX.
an input from the coprocessor that
indicates to the TI486SLC/E that the
coprocessor is currently executing an
instruction and is not yet able to accept
another opcode. When the TI486SLC/E
processor encounters a WAIT
instruction or any coprocessor
instruction that operates on the
coprocessor stack (i.e., load, pop,
arithmetic operation), BUSY is sampled.
BUSY is continually sampled and must
be recognized as inactive before the
CPU will supply the coprocessor with
another instruction. However, the
following coprocessor instructions are
allowed to execute even if BUSY is
active since these instructions are used
for coprocessor initialization and
exception clearing: FNINIT, FNCLEX.
BUSY is internally connected to a pullup
resistor to prevent it from floating active
when left unconnected.
resistor to prevent it from floating active
when left unconnected.
CLK2
15
I
2X Clock Input (active high). This signal
is the basic timing reference for the
TI486SLC/E microprocessor. The CLK2
input is internally divided by two to
generate the internal processor clock.
The external CLK2 is synchronized to a
known phase of the internal processor
clock by the falling edge of the RESET
signal. External timing parameters are
defined with respect to the rising edge of
CLK2.
is the basic timing reference for the
TI486SLC/E microprocessor. The CLK2
input is internally divided by two to
generate the internal processor clock.
The external CLK2 is synchronized to a
known phase of the internal processor
clock by the falling edge of the RESET
signal. External timing parameters are
defined with respect to the rising edge of
CLK2.
PIN
NAME
PIN
NO
I/O
DESCRIPTION
D0
1
I/O/Z
Data Bus (active high). The Data Bus
(D15-D0) signals are 3-state
bidirectional signals that provide the
data path between the TI486SLC/E and
external memory and I/O devices. The
data bus inputs data during memory
read, I/O read and interrupt
acknowledge cycles and outputs data
during memory and I/O write cycles.
Data read operations require that
specified data setup and hold times be
met for correct operation. The data bus
signals are high active and float while
the CPU is in a hold acknowledge or
float state.
(D15-D0) signals are 3-state
bidirectional signals that provide the
data path between the TI486SLC/E and
external memory and I/O devices. The
data bus inputs data during memory
read, I/O read and interrupt
acknowledge cycles and outputs data
during memory and I/O write cycles.
Data read operations require that
specified data setup and hold times be
met for correct operation. The data bus
signals are high active and float while
the CPU is in a hold acknowledge or
float state.
D1
100
D2
99
D3
96
D4
95
D5
94
D6
93
D7
92
D8
90
D9
89
D10
88
D11
87
D12
86
D13
83
D14
82
D15
81
D/C
24
O/Z
Data/Control. This signal is low during
control cycles and is high during data
cycles. Control cycles are issued during
functions such as a halt instruction,
interrupt servicing and code fetching.
Data bus cycles include data access
from either memory or I/O.
control cycles and is high during data
cycles. Control cycles are issued during
functions such as a halt instruction,
interrupt servicing and code fetching.
Data bus cycles include data access
from either memory or I/O.
ERROR
36
I
Coprocessor Error (active low). This is
an input used to indicate that the
coprocessor generated an error during
execution of a coprocessor instruction.
ERROR is sampled by the TI486SLC/E
processor whenever a coprocessor
instruction is executed. If ERROR is
sampled active, the processor generates
exception 16 which is then serviced by
the exception handling software.
an input used to indicate that the
coprocessor generated an error during
execution of a coprocessor instruction.
ERROR is sampled by the TI486SLC/E
processor whenever a coprocessor
instruction is executed. If ERROR is
sampled active, the processor generates
exception 16 which is then serviced by
the exception handling software.
Certain coprocessor instructions do not
generate an exception 16 even if
ERROR is active. These instructions,
which involve clearing coprocessor error
flags and saving the coprocessor state,
are listed as follows: FNINIT, FNCLEX,
FNSTSW, FNSTCW, FNSTENV,
FNSAVE. ERROR is internally
connected to a pullup resistor to prevent
it from floating active when left
unconnected.
generate an exception 16 even if
ERROR is active. These instructions,
which involve clearing coprocessor error
flags and saving the coprocessor state,
are listed as follows: FNINIT, FNCLEX,
FNSTSW, FNSTCW, FNSTENV,
FNSAVE. ERROR is internally
connected to a pullup resistor to prevent
it from floating active when left
unconnected.
ERROR is internally connected to a
pullup resistor to prevent it from floating
active when left unconnected.
pullup resistor to prevent it from floating
active when left unconnected.
FLT
28
I
Float (active low). This input forces all
bidirectional and output signals to a
3-state condition. Floating the signals
allows the TI486SLC/E signals to be
externally driven without physically
removing the device from the circuit.
The TI486SLC/E CPU must be reset
following assertion or deassertion of
FLT. It is recommended that FLT be
used only for test purposes.
bidirectional and output signals to a
3-state condition. Floating the signals
allows the TI486SLC/E signals to be
externally driven without physically
removing the device from the circuit.
The TI486SLC/E CPU must be reset
following assertion or deassertion of
FLT. It is recommended that FLT be
used only for test purposes.
FLT is internally connected to a pullup
resistor to prevent it from floating active
when left unconnected.
resistor to prevent it from floating active
when left unconnected.
– 37 –
PIN
NAME
PIN
NO
I/O
DESCRIPTION
FLUSH
30
I
Cache Flush (active low). This is an
input that invalidates (flushes) the entire
cache. Use of FLUSH to maintain cache
coherency is optional. the cache may
also be invalidated during each hold
acknowledge cycle by setting the BARB
bit in the CCR0 configuration register.
The FLUSH input is ignored following
reset and can be enabled using the
FLUSH bit in the CCR0 configuration
register.
input that invalidates (flushes) the entire
cache. Use of FLUSH to maintain cache
coherency is optional. the cache may
also be invalidated during each hold
acknowledge cycle by setting the BARB
bit in the CCR0 configuration register.
The FLUSH input is ignored following
reset and can be enabled using the
FLUSH bit in the CCR0 configuration
register.
FLUSH is internally connected to a
pullup resistor to prevent it from floating
active when left unconnected.
pullup resistor to prevent it from floating
active when left unconnected.
HOLD
4
I
Hold Request (active high). This input is
used to indicate that another bus master
requests control of the local bus. The
bus arbitration (HOLD, HLDA) signals
allow the TI486SLC/E to relinquish
control of its local bus when requested
by another bus master device. Once the
processor has relinquished its bus
(3-stated), the bus master device can
then drive the local bus signals.
used to indicate that another bus master
requests control of the local bus. The
bus arbitration (HOLD, HLDA) signals
allow the TI486SLC/E to relinquish
control of its local bus when requested
by another bus master device. Once the
processor has relinquished its bus
(3-stated), the bus master device can
then drive the local bus signals.
After recognizing the HOLD request and
completing the current bus cycle or
sequence of locked bus cycles, the
TI486SLC/E responds by floating the
local bus and asserting the hold
acknowledge (HLDA) output.
completing the current bus cycle or
sequence of locked bus cycles, the
TI486SLC/E responds by floating the
local bus and asserting the hold
acknowledge (HLDA) output.
Once HLDA is asserted, the bus
remains granted to the requesting bus
master until HOLD becomes inactive.
When the TI486SLC/E recognizes
HOLD is inactive, it simultaneously
drives the local bus and drives HLDA
inactive. External pullup resistors may
be required on some of the TI486SLC/E
3-state outputs to guarantee that they
remain inactive while in a hold
acknowledge state.
remains granted to the requesting bus
master until HOLD becomes inactive.
When the TI486SLC/E recognizes
HOLD is inactive, it simultaneously
drives the local bus and drives HLDA
inactive. External pullup resistors may
be required on some of the TI486SLC/E
3-state outputs to guarantee that they
remain inactive while in a hold
acknowledge state.
The HOLD input is not recognized while
RESET is active. If HOLD is asserted
while RESET is active, RESET has
priority and the TI486SLC/E places the
bus into an idle state instead of a hold
acknowledge state. The HOLD input is
also recognized during suspend mode
provided that the CLK2 input has not
been stopped. HOLD is level-sensitive
and must meet specified setup and hold
times for correct operation.
RESET is active. If HOLD is asserted
while RESET is active, RESET has
priority and the TI486SLC/E places the
bus into an idle state instead of a hold
acknowledge state. The HOLD input is
also recognized during suspend mode
provided that the CLK2 input has not
been stopped. HOLD is level-sensitive
and must meet specified setup and hold
times for correct operation.
PIN
NAME
PIN
NO
I/O
DESCRIPTION
HLDA
3
O
Hold Acknowledge (active high). This
output indicates that the TI486SLC/E is
in a hold acknowledge state and has
relinquished control of its local bus.
While in the hold acknowledge state, the
TI486SLC/E drives HLDA active and
continues to drive SUSPA, if enabled.
The other TI486SLC/E outputs are in a
high-impedance state allowing the
requesting bus master to drive these
signals. If the on-chip cache can satisfy
bus requests, the TI486SLC/E continues
to operate during hold acknowledge
states. A20M is internally recognized
during this time.
output indicates that the TI486SLC/E is
in a hold acknowledge state and has
relinquished control of its local bus.
While in the hold acknowledge state, the
TI486SLC/E drives HLDA active and
continues to drive SUSPA, if enabled.
The other TI486SLC/E outputs are in a
high-impedance state allowing the
requesting bus master to drive these
signals. If the on-chip cache can satisfy
bus requests, the TI486SLC/E continues
to operate during hold acknowledge
states. A20M is internally recognized
during this time.
The processor deactivates HLDA when
the HOLD request is driven inactive. The
TI486SLC/E stores an NMI rising edge
during a hold acknowledge state for
processing after HOLD is inactive. The
FLUSH input is also recognized during a
hold acknowledge state. If SUSP is
asserted during a hold acknowledge
state, the TI486SLC/E may or may not
enter suspend mode depending on the
state of the internal execution pipeline.
Table 3-3 summarizes the state of the
TI486SLC/E signals during hold
acknowledge.
the HOLD request is driven inactive. The
TI486SLC/E stores an NMI rising edge
during a hold acknowledge state for
processing after HOLD is inactive. The
FLUSH input is also recognized during a
hold acknowledge state. If SUSP is
asserted during a hold acknowledge
state, the TI486SLC/E may or may not
enter suspend mode depending on the
state of the internal execution pipeline.
Table 3-3 summarizes the state of the
TI486SLC/E signals during hold
acknowledge.
INTR
40
I
Maskable Interrupt Request. This is a
level-sensitive input that causes the
processor to suspend execution of the
current instruction stream and begin
execution of an interrupt service routine.
The INTR input can be masked
(ignored) through the flags Register IF
bit. When unmasked, the TI486SLC/E
responds to the INTR input by issuing
two locked interrupt acknowledge
cycles. To assure recognition of the
INTR request, INTR must remain active
until the start of the first interrupt
acknowledge cycle.
level-sensitive input that causes the
processor to suspend execution of the
current instruction stream and begin
execution of an interrupt service routine.
The INTR input can be masked
(ignored) through the flags Register IF
bit. When unmasked, the TI486SLC/E
responds to the INTR input by issuing
two locked interrupt acknowledge
cycles. To assure recognition of the
INTR request, INTR must remain active
until the start of the first interrupt
acknowledge cycle.
– 38 –
PIN
NAME
PIN
NO
I/O
DESCRIPTION
KEN
29
I
Cache Enable (active low). This is an
input which indicates that the data being
returned during the current cycle is
cacheable. When KEN is active and the
TI486SLC/E is performing a cacheable
code fetch or memory data read cycle,
the cycle is transformed into a cache fill.
Use of the KEN input to control
cacheability is optional. The
non-cacheable region registers can also
be used to control cacheability. Memory
addresses specified by the
non-cacheable region registers are not
cacheable regardless of the state of
KEN. I/O accesses, locked reads, SMM
address space accesses, and interrupt
acknowledge cycles are never cached.
input which indicates that the data being
returned during the current cycle is
cacheable. When KEN is active and the
TI486SLC/E is performing a cacheable
code fetch or memory data read cycle,
the cycle is transformed into a cache fill.
Use of the KEN input to control
cacheability is optional. The
non-cacheable region registers can also
be used to control cacheability. Memory
addresses specified by the
non-cacheable region registers are not
cacheable regardless of the state of
KEN. I/O accesses, locked reads, SMM
address space accesses, and interrupt
acknowledge cycles are never cached.
During cached code fetches, two
contiguous read cycles are performed to
completely fill the 4-byte cache line.
KEN must be asserted during both read
cycles in order to cause a cache line fill.
During cached data reads, the
TI486SLC/E performs only those bus
cycles necessary to supply the required
data to complete the current operation.
Valid bits are maintained for each byte
in the cache line, thus allowing data
operands of less than 4 bytes to reside
in the cache.
contiguous read cycles are performed to
completely fill the 4-byte cache line.
KEN must be asserted during both read
cycles in order to cause a cache line fill.
During cached data reads, the
TI486SLC/E performs only those bus
cycles necessary to supply the required
data to complete the current operation.
Valid bits are maintained for each byte
in the cache line, thus allowing data
operands of less than 4 bytes to reside
in the cache.
During any cache fill cycle with KEN
asserted, the TI486SLC/E ignores the
state of the byte enables (BHE and BLE)
and always writes two bytes of data into
the cache. The KEN input is ignored
following reset and can be enabled
using the KEN bit in the CCR0
configuration register.
asserted, the TI486SLC/E ignores the
state of the byte enables (BHE and BLE)
and always writes two bytes of data into
the cache. The KEN input is ignored
following reset and can be enabled
using the KEN bit in the CCR0
configuration register.
KEN is internally connected to a pullup
resistor to prevent it from floating active
when left unconnected.
resistor to prevent it from floating active
when left unconnected.
LOCK
26
I
LOCK (active low). LOCK is asserted to
deny control of the CPU bus to other
bus masters. The LOCK signal may be
explicitly activated during bus operations
by including the LOCK prefix on certain
instructions. LOCK is always asserted
during descriptor and page table
updates, interrupt acknowledge
sequences and when executing the
XCHG instruction. The TI486SLC/E
does not enter the hold acknowledge
state in response to HOLD while the
LOCK input is active.
deny control of the CPU bus to other
bus masters. The LOCK signal may be
explicitly activated during bus operations
by including the LOCK prefix on certain
instructions. LOCK is always asserted
during descriptor and page table
updates, interrupt acknowledge
sequences and when executing the
XCHG instruction. The TI486SLC/E
does not enter the hold acknowledge
state in response to HOLD while the
LOCK input is active.
M/IO
23
O/Z
Memory/IO. This signal is low during I/O
read and write cycles and is high during
memory cycles.
read and write cycles and is high during
memory cycles.
PIN
NAME
PIN
NO
I/O
DESCRIPTION
NA
6
I
Next Address Request (active low).
This is an input used to request address
pipelining by the system hardware.
When asserted, the system indicates
that it is prepared to accept new bus
cycle definition and address signals
(M/IO, D/C, W/R, A23-A1, BHE, and
BLE) from the microprocessor even if
the current bus cycle has not been
terminated by assertion of READY. If the
TI486SLC/E has an internal bus request
pending and the NA input is sampled
active, the next bus cycle definition and
address signals are driven onto the bus.
This is an input used to request address
pipelining by the system hardware.
When asserted, the system indicates
that it is prepared to accept new bus
cycle definition and address signals
(M/IO, D/C, W/R, A23-A1, BHE, and
BLE) from the microprocessor even if
the current bus cycle has not been
terminated by assertion of READY. If the
TI486SLC/E has an internal bus request
pending and the NA input is sampled
active, the next bus cycle definition and
address signals are driven onto the bus.
NC
27,
45,
45,
46
—
No connection. Should be left
disconnected.
disconnected.
NMI
38
I
Non-maskable Interrupt Request. This
is a rising-edge-sensitive input that
causes the processor to suspend
execution of the current instruction
stream and begin execution of an NMI
interrupt service routine. The NMI
interrupt service request cannot be
masked by software. Asserting NMI
causes an interrupt which internally
supplies interrupt vector 2h to the CPU
core. External interrupt acknowledge
cycles are not necessary since the NMI
interrupt vector is supplied internally.
is a rising-edge-sensitive input that
causes the processor to suspend
execution of the current instruction
stream and begin execution of an NMI
interrupt service routine. The NMI
interrupt service request cannot be
masked by software. Asserting NMI
causes an interrupt which internally
supplies interrupt vector 2h to the CPU
core. External interrupt acknowledge
cycles are not necessary since the NMI
interrupt vector is supplied internally.
The TI486SLC/E samples NMI at the
beginning of each phase 2. To assure
recognition, NMI must be inactive for at
least eight CLK2 periods and then be
active for at least eight CLK2 periods.
Additionally, specified setup and hold
times must be met to guarantee
recognition at a particular clock edge.
beginning of each phase 2. To assure
recognition, NMI must be inactive for at
least eight CLK2 periods and then be
active for at least eight CLK2 periods.
Additionally, specified setup and hold
times must be met to guarantee
recognition at a particular clock edge.
PEREQ
37
I
Coprocessor Request (active high).
This is an input that indicates the
coprocessor is ready to transfer data to
or from the CPU. The coprocessor may
assert PEREQ in the process of
executing a coprocessor instruction. The
TI486SLC/E internally stores the current
coprocessor opcode and performs the
correct data transfers to support
coprocessor operations using PEREQ to
synchronize the transfer of required
operands.
This is an input that indicates the
coprocessor is ready to transfer data to
or from the CPU. The coprocessor may
assert PEREQ in the process of
executing a coprocessor instruction. The
TI486SLC/E internally stores the current
coprocessor opcode and performs the
correct data transfers to support
coprocessor operations using PEREQ to
synchronize the transfer of required
operands.
PEREQ is internally connected to a
pulldown resistor to prevent this signal
from floating active when left
unconnected.
pulldown resistor to prevent this signal
from floating active when left
unconnected.
– 39 –
PIN
NAME
PIN
NO
I/O
DESCRIPTION
READY
7
I
Ready. This is an input generated by
the system hardware that indicates the
current bus cycle can be terminated.
During a read cycle, assertion of
READY indicates that the system
hardware has presented valid data to
the CPU. when READY is sampled
active, the TI486SLC/E latches the input
data and terminates the cycle. During a
write cycle, READY assertion indicates
that the system hardware has accepted
the TI486SLC/E output data. READY
must be asserted to terminate every bus
cycle, including halt and shutdown
indication cycles.
the system hardware that indicates the
current bus cycle can be terminated.
During a read cycle, assertion of
READY indicates that the system
hardware has presented valid data to
the CPU. when READY is sampled
active, the TI486SLC/E latches the input
data and terminates the cycle. During a
write cycle, READY assertion indicates
that the system hardware has accepted
the TI486SLC/E output data. READY
must be asserted to terminate every bus
cycle, including halt and shutdown
indication cycles.
RESET
33
I
Reset (active high). When asserted,
RESET suspends all operations in
progress and places the TI486SLC/E
into a reset state. RESET is a
level-sensitive synchronous input and
must meet specified setup and hold
times to be properly recognized by the
TI486SLC/E. The TI486SLC/E begins
executing instructions at physical
address location FF FFF0h
approximately 400 CLK2s after RESET
is driven inactive (low).
RESET suspends all operations in
progress and places the TI486SLC/E
into a reset state. RESET is a
level-sensitive synchronous input and
must meet specified setup and hold
times to be properly recognized by the
TI486SLC/E. The TI486SLC/E begins
executing instructions at physical
address location FF FFF0h
approximately 400 CLK2s after RESET
is driven inactive (low).
While RESET is active all other input
pins, except FLT, are ignored. The
remaining signals are initialized to their
reset state during the internal processor
reset sequence. The reset signal states
for the TI486SLC/E are shown in Table
3-3.
pins, except FLT, are ignored. The
remaining signals are initialized to their
reset state during the internal processor
reset sequence. The reset signal states
for the TI486SLC/E are shown in Table
3-3.
SMADS
20
O/Z
SMM Address Strobe (active low).
SMADS is asserted instead of the ADS
during SMM bus cycles and indicates
that SMM memory is being accessed.
SMADS floats while the CPU is in a hold
acknowledge or float state. The SMADS
output is disabled (floated) following
reset and can be enabled using the SMI
bit in the CCR1 configuration register.
SMADS is asserted instead of the ADS
during SMM bus cycles and indicates
that SMM memory is being accessed.
SMADS floats while the CPU is in a hold
acknowledge or float state. The SMADS
output is disabled (floated) following
reset and can be enabled using the SMI
bit in the CCR1 configuration register.
SMI
47
I/O
System Management Interrupt (active
low). This is a bidirectional signal and
level sensitive interrupt with higher
priority than the NMI interrupt. SMI must
be active for at least four CLK2 clock
periods to be recognized by the
TI486SLC/E. After the SMI interrupt is
acknowledged, the SI pin is driven low
by the TI486SLC/E for the duration of
the SMI service routine. The SMI input is
ignored following reset and can be
enabled using the SMI bit in the CCR1
configuration register.
low). This is a bidirectional signal and
level sensitive interrupt with higher
priority than the NMI interrupt. SMI must
be active for at least four CLK2 clock
periods to be recognized by the
TI486SLC/E. After the SMI interrupt is
acknowledged, the SI pin is driven low
by the TI486SLC/E for the duration of
the SMI service routine. The SMI input is
ignored following reset and can be
enabled using the SMI bit in the CCR1
configuration register.
SMI is internally connected to a pullup
resistor to prevent it from floating active
when left unconnected.
resistor to prevent it from floating active
when left unconnected.
PIN
NAME
PIN
NO
I/O
DESCRIPTION
SUSP
43
I
Suspend Request (active low). This is
an input that requests the TI486SLC/E
enter suspend mode. After recognizing
SUSP active, the processor completes
execution of the current instruction, any
pending decoded instructions and
associated bus cycles. In addition, the
TI486SLC/E waits for the coprocessor to
indicate a not busy status (BUSY = 1)
before entering suspend mode and
asserting suspend acknowledge
(SUSPA).
an input that requests the TI486SLC/E
enter suspend mode. After recognizing
SUSP active, the processor completes
execution of the current instruction, any
pending decoded instructions and
associated bus cycles. In addition, the
TI486SLC/E waits for the coprocessor to
indicate a not busy status (BUSY = 1)
before entering suspend mode and
asserting suspend acknowledge
(SUSPA).
SUSP is internally connected to a pullup
resistor to prevent it from floating active
when left unconnected.
resistor to prevent it from floating active
when left unconnected.
SUSPA
44
O
Suspend Acknowledge (active low).
This output indicates that the
TI486SLC/E has entered the suspend
mode as a result of SUSP assertion or
execution of a HALT instruction.
This output indicates that the
TI486SLC/E has entered the suspend
mode as a result of SUSP assertion or
execution of a HALT instruction.
V
CC
8
I
5-V Power Supply. All pins must be
connected and used.
connected and used.
9
10
21
32
39
42
48
57
69
71
84
91
97
V
SS
2
I
Ground Pins. All pins must be
connected and used.
connected and used.
5
11
12
13
14
22
35
41
49
50
63
67
68
77
78
85
98
W/R
25
O/Z
Write/Read. W/R is low during read
cycles (data is read from memory or I/O)
and is high during write bus cycles (data
is written to memory or I/O).
cycles (data is read from memory or I/O)
and is high during write bus cycles (data
is written to memory or I/O).
– 40 –
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