Sharp UP-600 / UP-700 (serv.man25) Service Manual ▷ View online
13-2. MRS, SRV reset
The UP-600/700 does not have the mode switch. The procedure for
resetting MRS, SRV is different from that of conventional cash regis-
ters.
in the UP-600/700, MRS, SRV resetting is selected and executed by
the key which has bee depressed when the CKDC reset is released
to start the system.
resetting MRS, SRV is different from that of conventional cash regis-
ters.
in the UP-600/700, MRS, SRV resetting is selected and executed by
the key which has bee depressed when the CKDC reset is released
to start the system.
(In the case of MRS, security is added by a key operation equivalent
to a pass word.)
to a pass word.)
Flow chart
14. Drawer
The UP-600/700 can use up to 2 optional external drawers.
14-1. Drawer solenoid drive
P34
∼
P37 inside the CPU are allocated for the port output of the
drawer solenoid drive.
Built-in port
Signal name
Remarks
P34
DR0
Drawer 1 (optional drawer)
P35
DR1
Drawer 2 (optional drawer)
P36
DR2
Reserved
P37
DR3
Reserved
One port corresponds to one drawer. Theoretically, it is possible to
drive multiple drawers at the same time, but this processing must be
inhibited softwarewisely because of power supply capacity and driver
hardware factors. If a power failure is detected, the drawer solenoid
drive must be stopped as soon as possible.
drive multiple drawers at the same time, but this processing must be
inhibited softwarewisely because of power supply capacity and driver
hardware factors. If a power failure is detected, the drawer solenoid
drive must be stopped as soon as possible.
The drawer solenoid drive time must controlled in the range of 40
ms to 50 ms by the timer.
ms to 50 ms by the timer.
14-2. Drawer open/close sense
The drawer open/close sense signal is input into the built-in port of
the CPU. the sense signal of an optional drawer sensor is also wired
ORed before inputting.
the CPU. the sense signal of an optional drawer sensor is also wired
ORed before inputting.
•
P33=1: Any of the drawers is open.
15. TCP/IP STACK
The LAN of the UP-600/700 uses as a protocol Ethernet, which sup-
ports TCP/IP.
ports TCP/IP.
The interface with the TCP/IP board is achieved through 2 interrupt
signals and dual-port RAM.
signals and dual-port RAM.
The decode of dual-port RAM is located in the following space:
DP-RAM: F20000H - F2FFFFH (max. 64 KB)
The interruption from the TCP/IP is allocated as follows:
EXINTO: INTSW (SLAVE WRITE interrupt) bit 6 of 00FF81H
EXINT1: INTSR (SLAVE READ interrupt) bit 0 of 00FF80H
<TCP/IP connector terminals>
Signal Name
Pin No.
Pin No.
Signal Name
+5V
2
1
+5V
+5V
4
3
+5V
A14
6
5
A15
A12
8
7
A13
HWR
10
9
DPCS
A10
12
11
A11
A0
14
13
RD
A2
16
15
A1
A4
18
17
A3
A6
20
19
A5
A8
22
21
A7
D7
24
23
A9
D5
26
25
D6
D3
28
27
D4
D1
30
29
D2
LRES
32
31
D0
INTSW
34
33
INTSR
-
36
35
-
GND
38
37
GND
GND
40
39
GND
16. RS232
Two standard RS232 channels are compatible with the ER-A5RS.
However, while the ER-A5RS uses the IRQ2 terminal of the CPU for
interruption of the RS232, the UP-600/700 cannot use the IRQ1 ter-
minal instead of it. (The IRQ2 terminal is used for IR as the SCK1
terminal.)
The standard RS232 is fixed to the logic channels 1 and 8. Use the
channels 2, 3, 4, 5, 6 and 7 for the ER-A5RS.
However, while the ER-A5RS uses the IRQ2 terminal of the CPU for
interruption of the RS232, the UP-600/700 cannot use the IRQ1 ter-
minal instead of it. (The IRQ2 terminal is used for IR as the SCK1
terminal.)
The standard RS232 is fixed to the logic channels 1 and 8. Use the
channels 2, 3, 4, 5, 6 and 7 for the ER-A5RS.
17. MCR
This paragraph describes MCR option (UP-E13MR) control defined
by UP-600/700 hardware architecture.
3 channels of the serial port (interchangeable with 8251) built in the
MPCA9 are used. 3 tracks of data are read simultaneously. Supports
the first and second tracks MCR of ISO. (UP-E13MR)
by UP-600/700 hardware architecture.
3 channels of the serial port (interchangeable with 8251) built in the
MPCA9 are used. 3 tracks of data are read simultaneously. Supports
the first and second tracks MCR of ISO. (UP-E13MR)
Yes
No
*Slide Switch
operation
operation
MRS1 key
ON?
MRS2 key
ON?
CKDC start
SRV reset
MRS reset
Start
Normal
start?
condition read
Recovery
No
Yes
OK?
OK?
SRV reset
SRV reset
No
Yes
Yes
No
Yes
Yes
No
Hard reset
start?
PASSWORD
judgement
judgement
judgement
10-key position
input sequence
input sequence
MRS reset
PASSWORD
17-1. CPU interface
The CPU interface for the USART (8251) and magnet card reader
(MCM-21) in the UP-600/700 system is shown below.
(MCM-21) in the UP-600/700 system is shown below.
Signal description
RCP1
TRACK 1 CLOCK PULSE
RDD1
TRACK 1 DATA SIGNAL
RCP2
TRACK 2 CLOCK PULSE
RDD2
TRACK 2 DATA SIGNAL
RCP3
TRACK 3 CLOCK PULSE
RCD3
TRACK 3 DATA SIGNAL
CLS1
TRACK 1 CARD DETECTION SIGNAL
CLS2
TRACK 2 CARD DETECTION SIGNAL
CLS3
TRACK 3 CARD DETECTION SIGNAL
RCVRDY1
TRACK 1 DATA RECEIVING SIGNAL
RCVRDY2
TRACK 2 DATA RECEIVING SIGNAL
RCVRDY3
TRACK 3 DATA RECEIVING SIGNAL
INTMCR
INTERRUPT SIGNAL OR-SYNTHESIZED from
RCVRDY and SYNC input
RCVRDY and SYNC input
2 chip select signals for 8251 are generated inside MPCA8.
17-2. MCR interface
The operating timing of the MCR interface signals is given below.
(1) Example of timing
(2) Detailed timing (relation between DATA and CLOCK PULSE)
The "NULL" CODE is basically written prior to the opening code. The
opening code detection algorithm is considered because data may
become corrupt before and after the CARD detection signal due to a
worn magnet stripe.
opening code detection algorithm is considered because data may
become corrupt before and after the CARD detection signal due to a
worn magnet stripe.
18. 1-HOLE CLERK
On the UP-600/700, 1-hole clerk key with up to 8 bits can be used.
The 1-hole clerk switch is controlled through the CKDC9 on the main
board.
board.
CPU
ICI
INTMCR
RCVRDY1
RCVCLK2
RDD1
RCP2
RDD2
CLS1
RCVDT1
RCP1
/DSR1
CLS2
RCVDT2
8251 x 2
Integrated as MPCA8
in the ER-A770 system.
in the ER-A770 system.
RCVCLK1
/DSR2
CLS1,
CLS2
RCVRDY1
RCVRDY2
INTMCR
SYNC
MPCA7
RCP1
CLS2
RCVRDY3
RCVRDY2
RDD3
RCVDT3
/DSR3
RCVCLK3
CLS3
RCP3
RDD1/RDD2
RCP1/RCP2
CLS1/CLS2
RDD3
RCP3
CLS3
"0" "1" "1"
Approx. 16µ s
Min. 5 µ s
RDD1/RDD2
RCP1/RCP2
RDD3
RCP3
CKDC9
ST0 ST3
LS138
X2
/S2 /S9
/CFSR
2001 BY SHARP CORPORATION
All rights reserved.
Printed in Japan.
SHARP CORPORATION
Digital Document Systems Group
Quality & Reliability Control Center
Yamatokoriyama, Nara 639-1186, Japan
Digital Document Systems Group
Quality & Reliability Control Center
Yamatokoriyama, Nara 639-1186, Japan
2001 February Printed in Japan
>>>>> USE FONT <<<<<
Helvetica/ Helvetica-Condensed/ Century-Schoolbook/ Symbol & OriginalFonts: (RingWorld2/RingFont2/Pa
Symbol/PartsCod)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2001 BY SHARP CORPORATION
All rights reserved.
Printed in Japan.
SHARP CORPORATION
Digital Document Systems Group
Quality & Reliability Control Center
Yamatokoriyama, Nara 639-1186, Japan
Digital Document Systems Group
Quality & Reliability Control Center
Yamatokoriyama, Nara 639-1186, Japan
2001 February Printed in Japan
>>>>> USE FONT <<<<<
Helvetica/ Helvetica-Condensed/ Century-Schoolbook/ Symbol & OriginalFonts: (RingWorld2/RingFont2/Pa
Symbol/PartsCod)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
