Sharp UP-600 / UP-700 (serv.man20) Service Manual ▷ View online
TCP/IP INLINE I/F
MODEL
UP-E10IN
CHAPTER 1. GENERAL DESCRIPTION......................................................... 1
CHAPTER 2. BLOCK DIAGRAM ..................................................................... 1
CHAPTER 3. CONFIGURATION ..................................................................... 1
CHAPTER 4. MAIN LSI DESCRIPTION .......................................................... 2
CHAPTER 5. MEMORY MAP .......................................................................... 6
CHAPTER 6. INTERFACE WITH HOST CPU ................................................. 7
CHAPTER 7. LAN CONTROL.......................................................................... 8
CHAPTER 8. PORT SETTING......................................................................... 8
CHAPTER 9. CONNECTOR PIN TABLE......................................................... 8
CHAPTER 10. SWITCH SETTING................................................................... 9
CHAPTER 11. WRITING/READING
THE MAC ADDRESS/FIRMWARE PROGRAM..................... 10
CHAPTER 12. CIRCUIT DIAGRAM ............................................................... 13
CHAPTER 13. PWB LAYOUT........................................................................ 17
CONTENTS
Parts marked with "
" are important for maintaining the safety of the set. Be sure to replace these parts with specified
ones for maintaining the safety and performance of the set.
SHARP CORPORATION
This document has been published to be used
for after sales service only.
The contents are subject to change without notice.
for after sales service only.
The contents are subject to change without notice.
SERVICE MANUAL
CHAPTER 1. GENERAL DESCRIPTION
This control board is an Ethernet board that supports TCP/IP proto-
col.
col.
CHAPTER 2. BLOCK DIAGRAM
When writing data into FLASH, switch /CS0to EP-ROM and /CS3
to FLASH Memory.
to FLASH Memory.
CHAPTER 3. CONFIGURATION
CPU :
[HitachiSH-2 Series SH7014 (20MHz)]
[HitachiSH-2 Series SH7014 (20MHz)]
As external memory spaces, CS0 - CS3 and DRAM space are pro-
vided. This board assigns FLASH Memory to CS0, SRAM to CS1,
dual-port SRAM to CS2, and LAN controller to CS3.
vided. This board assigns FLASH Memory to CS0, SRAM to CS1,
dual-port SRAM to CS2, and LAN controller to CS3.
LAN Controller : [RealtekRTL8019AS(20MHz)]
LAN controller is assigned to CS space.
Because of pseudo ISA connection, each register is assigned to ad-
dresses of H00C00300 and after.
dresses of H00C00300 and after.
ROM(FLASH Memory) :
[SharpLH28F004BVT(4Mbits)]
[SharpLH28F004BVT(4Mbits)]
<Access Time = 90ns>
ROM (FLASH Memory) is assigned to CS0 space.
Data is written onto FLASH Memory from UV-EPROM by switching
the CSO space to UV-EPROM and the CS3 space to FALSH Mem-
ory.
the CSO space to UV-EPROM and the CS3 space to FALSH Mem-
ory.
MAC Address is written on FLASH Memory.
•
Company code is assigned to "08001FH".
•
The serial number and adjustment byte are stored in an area of 4
bytes from the address H’0007C000.
<The serial number is acquired according to Sharp’s in-house
specification(SS).>
bytes from the address H’0007C000.
<The serial number is acquired according to Sharp’s in-house
specification(SS).>
RAM : [S-RAM 1Mbits]
<Access Time=70ns>
Assigned to CS1 space.
[IDT Dual-Port SRAM IDT7134]<Access Time=55ns>
Assigned to CS2 space.
The IDT7134 does not have any LOGICiBusy or Semaphorej, access
to the same address from both sides is inhibited.
to the same address from both sides is inhibited.
Pulse Trans : [Pulse78Z034]
It is used for the 10Base-T standard and has a choke coil built in at
the output side.
the output side.
Dual-Port
RAM
4k byte
CN
RJ-45
Data Bus
Address Bus
Da
ta
ta
Bus
LOGIC
/CS1
/CS2
/INTHR
/INTHW
/INTSR
/INTSW
10MHz
/CS0
/CS0
/CS3
/CS3
/CS2
/CS1
/CS0
/HWACK
/HRACK
/SWRQ
/SRRQ
CPU
(SH-2)
/DPCS,
/WR,/RD
/WR,/RD
Address
Bus
LD0~LD7
LA0~LA11
FLASH
512k byte
LD0~LD7
LA0~LA18
LD0~LD7
LA0~LA18
SRAM
128k byte
LD0~LD7
LA0~LA19
LD0~LD7
LA0~LA18
LAN Cnt.
(8bit-Bus)
EP-ROM
(Writing in
to FLASH)
512k byte
>>>>> USE FONT <<<<<
Helvetica/ Helvetica-Condensed/ Century-Schoolbook/ Symbol & OriginalFonts: (RingWorld2/RingFont2/Pa
Symbol/PartsCod)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
CHAPTER 4. MAIN LSI DESCRIPTION
(1) CPU (SH7014)
(1) -1. SH7014 Overview
The SH7014 CMOS single-chip microprocessors integrate a Hitachi-
original architecture, high-speed CPU with peripheral functions re-
quired for system configuration.
original architecture, high-speed CPU with peripheral functions re-
quired for system configuration.
The CPU has a RISC-type instruction set. Most instructions can be
executed in one clock cycle, which greatly improves instruction exe-
cution speed. In addition, the 32-bit internal-bus architecture en-
hances data processing power. With this CPU, it has become possi-
ble to assemble low cost, high performance/high-functioning systems,
even for applications that were previously impossible with microproc-
essors, such as real-time control, which demands high speeds. In
particular, the SH7040 series has a 1-kbyte on-chip cache, which
allows an improvement in CPU performance during external memory
access.
executed in one clock cycle, which greatly improves instruction exe-
cution speed. In addition, the 32-bit internal-bus architecture en-
hances data processing power. With this CPU, it has become possi-
ble to assemble low cost, high performance/high-functioning systems,
even for applications that were previously impossible with microproc-
essors, such as real-time control, which demands high speeds. In
particular, the SH7040 series has a 1-kbyte on-chip cache, which
allows an improvement in CPU performance during external memory
access.
In addition, this LSI includes on-chip peripheral functions necessary
for system configuration, such as large-capacity ROM (except the
SH7014, which is ROMless) and RAM, timers, a serial communica-
tion interface (SCI), an A/D converter, an interrupt controller, and I/O
ports. Memory or peripheral LSIs can be connected efficiently with an
external memory access support function.
This greatly reduces system cost.
for system configuration, such as large-capacity ROM (except the
SH7014, which is ROMless) and RAM, timers, a serial communica-
tion interface (SCI), an A/D converter, an interrupt controller, and I/O
ports. Memory or peripheral LSIs can be connected efficiently with an
external memory access support function.
This greatly reduces system cost.
(1) -1-1. SH7014 Features
CPU:
•
Original Hitachi architecture
•
32-bit internal data bus
•
General-register machine
–
Sixteen 32-bit general registers
–
Three 32-bit control registers
–
Four 32-bit system registers
•
RISC-type instruction set
–
Instruction length: 16-bit fixed length for improved code effi-
ciency
ciency
–
Load-store architecture (basic operations are executed be-
tween registers)
tween registers)
–
Delayed branch instructions reduce pipeline disruption during
branch
branch
–
Instruction set based on C language
•
Instruction execution time: one instruction/cycle (35 ns/instruction
at 28.7-MHz operation)
at 28.7-MHz operation)
•
Address space: Architecture supports 4 Gbytes
•
On-chip multiplier: multiplication operations (32 bits x 32 bits
64
bits) and multiplication/accumulation operations (32 bits x 32 bits +
64 bits
64 bits
64 bits) executed in two to four cycles
•
Five-stage pipeline
Cache Memory:
•
1-kbyte instruction cache
•
Caching of instruction codes and PC relative read data
•
4-byte line length (1 longword: 2 instruction lengths)
•
256 entry cache tags
•
Direct map method
•
On-chip RAM, and on-chip I/O areas not objects of cache
•
Used in common with on-chip RAM; 2 kbytes of on-chip RAM used
as address array/data array when cache is enabled
as address array/data array when cache is enabled
Interrupt Controller (INTC):
•
Seven external interrupt pins (NMI, IRQ x 6)
•
Twenty-eight internal interrupt sources
•
Sixteen programmable priority levels
Bus State Controller (BSC):
•
Supports external extended memory access
–
8-bit, or 16-bit external data bus
•
Memory address space divided into five areas (four areas of
SRAM space, one area of DRAM space) with the following settable
features:
SRAM space, one area of DRAM space) with the following settable
features:
–
Number of wait cycles
–
Outputs chip-select signals for each area
–
During DRAM space access:
•
Outputs RAS and CAS signals for DRAM
•
Can generate a RAS precharge time assurance Tp cycle
•
DRAM burst access function
–
Supports high-speed access mode for DRAM
•
DRAM refresh function
–
Programmable refresh interval
–
Supports CAS-before-RAS refresh and self-refresh modes
•
Wait cycles can be inserted using an external WAIT signal
•
Address data multiplex I/O devices can be accessed
Note: No bus release
Direct Memory Access Controller (DMAC) (2 Channels):
•
Supports cycle-steal and burst transfers
•
Supports single address mode and dual address mode transfers
•
Priority order: fixed at channel 0 > channel 1
•
Transfer counter: 16 bits
•
Transfer request sources: external DREQ input, auto-request, and
on-chip supporting modules
on-chip supporting modules
•
Address space: 4 Gbytes
•
Choice of 8-, 16-, or 32-bit transfer data size
Multifunction Timer/Pulse Unit (MTU) (3 Channels):
•
Maximum 8 types of waveform output or maximum 16 types of
pulse I/O processing possible based on 16-bit timer, 3 channels
pulse I/O processing possible based on 16-bit timer, 3 channels
•
8 dual-use output compare/input capture registers
•
8 independent comparators
•
8 types of counter input clock
•
Input capture function
•
Pulse output mode
–
One shot, toggle, PWM
•
Phase calculation mode
–
2-phase encoder calculation processing
Compare Match Timer (CMT) (Two Channels):
•
16-bit free-running counter
•
One compare register
•
Generates an interrupt request upon compare match
Watchdog Timer (WDT) (One Channel):
•
Watchdog timer or interval timer
•
Count overflow can generate an internal reset, external signal, or
interrupt
interrupt
Serial Communication Interface (SCI) (Two Channels):
(Per Channel):
•
Asynchronous or clock-synchronous mode is selectable
•
Can transmit and receive simultaneously (full duplex)
•
On-chip dedicated baud rate generator
•
Multiprocessor communication function
I/O Ports:
•
SH7014
–
Input/output: 35
–
Input: 8
–
Total: 43
A/D Converter:
•
10 bits 8 channels
•
The SH7014 has a high-speed A/D converter.
On-Chip Memory:
•
ROM
–
SH7014: ROMless
•
RAM: SH7014: 3 kbytes (1 kbyte when cache is used)
Operating Modes:
•
Operating modes
–
Non-extended ROM mode
•
Processing states
–
Program execution state
–
Exception processing state
•
Power-down modes
–
Sleep mode
–
Software standby mode
Clock Pulse Generator (CPG):
•
On-chip clock pulse generator
–
On-chip clock-doubling PLL circuit
(1) -2. Block Diagram
Figure 1. is a block diagram of the SH7014.
(1) -3. Pin Arrangement and Pin Functions
(1) -3-1. Pin Arrangment
Figure 2. shows the pin arrangement for the SH7014 (top view).
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MD3
MD2
MD1
MD0
MD2
MD1
MD0
NMI
EXTAL
XTAL
V
CC
V
CC
V
CC
PLLVCC
PLLCAP
PLLVSS
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
AV
CC
AV
SS
RES
WDTOVR
PB9/IR
Q7/
A
2
1
PB8/IR
Q6/
A
2
0/WAIT
PB7/A19
PB6/A18
PB5/IR
Q3/
RDWR
PB4/IR
Q2/
C
ASH
PB3/IR
Q1/
C
ASL
PB2/IR
Q0/
R
AS
A17
A16
PA15/CK
RD
WRH
WRL
CS1
CS0
PA9/TCLKD/I
RQ3
PA8/TCLKC/I
RQ2
PA7/TCLKB/CS3
PA6/TCLKA/CS2
PA5/SCK1/D
REQ1/IR
Q1
PA4/TX
D
1
PA3/RXD1
PA2/SCK0/D
REQ0/IR
Q0
PA1/TX
D
0
PA0/RXD0
PE15/DAC
K1
PE14/DAC
K0/AH
PE13
PE12
PE11
PE10
PE9
PE8
PE7/TIOC
2
B
PE6/TIOC
2
A
PE5/TIOC
1
B
PE4/TIOC
1
A
PE3/TIOC
0
D/D
R
AK1
PE2/TIOC
0
C/D
R
EQ1
PE1/TIO
C0B/DRAK
0
PE0/TIO
C0A/DREQ
0
: Peripheral address bus
: Peripheral data bus
: Internal address bus
: Internal upper data bus
: Internal lower data bus
PLL
PF7/AN7
PF6/AN6
PF5/AN5
PF4/AN4
PF3/AN3
PF2/AN2
PF1/AN1
PF0/AN0
RAM (3 kB)/
cache (1 kB)
cache (1 kB)
CPU
Direct memory
access controller
Interrupt
controller
Bus state controller
Serial communi-
cation interface
(• 2 channels)
Multifunction timer/
pulse unit
Compare match
timer (• 2 channels)
A/D
converter
Watch-
dog
timer
V
SS
V
SS
V
SS
Figure 1. Block Diagram of the SH7014
PB13
PE12
PE11
V
SS
PE10
PE9
PE8
PE7/TIOC2B
PE6/TIOC2A
V
CC
PE5/TIOC1B
V
SS
AV
CC
PF7/AN7
PF6/AN6
AV
SS
PF5/AN5
PF4/AN4
PF3/AN3
PF2/AN2
PF1/AN1
PF0/AN0
V
SS
PE4/TIOC1A
PE3/TIOC0D/DRAK1
PE2/TIOC0C/DREQ1
PE1/TIOC0B/DRAK0
PE0/TIOC0A/DREQ0
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
PB6/A18
PB7/A19
PB8/IRQ6/A20/WAIT
PB9/IRQ7/A21
V
SS
RD
WDTOVF
WRH
VCC
WRL
V
SS
CS0
PA9/TCLKD/IRQ3
PA7/TCLKB/CS3
PA6/TCLKA/CS2
PA5/SCK1/DREQ1/IRQ1
PA4/TXD1
PA3/RXD1
PA2/SCK0/DREQ0/IRQ0
PA1/TXD0
PA0/RXD0
D15
D14
D13
V
SS
D12
RES
PA
15/
CK
PLLV
SS
PLLCA
P
PLLV
CC
MD0
MD1
V
CC
NMI
MD2
EX
TA
L
MD3
XT
AL
V
SS
D0
D1
D2
D3
D4
V
CC
D5
D6
D7
V
SS
D8
D9
D10
D11
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
CS1
PA8/TCLKC/IRQ2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PE
14/
DA
CK0/
A
H
PE
15/
DA
CK1
V
SS
A0
A1
A2
A3
A4
A5
A6
A7
A11
A12
A13
A14
A15
A16
V
CC
A17
P
B
2/
IRQ0/
R
AS
P
B
3/
IRQ1/
C
AS
L
P
B
4/
IRQ2/
C
AS
H
V
SS
PB
5/
IRQ3/
RDWR
A8
A9
A10
V
SS
QFP-112
Figure 2. SH7014 Pin Arrangement (QFP-112 Top View)
