Sharp UP-600 / UP-700 (serv.man25) Service Manual ▷ View online
Pin
No.
Name
IN/OUT
Description
109
DSR5#
I
RS-232 ch1 DSR signal
110
CTS5#
I
RS-232 ch1 CTS signal
111
RXD5
I
RS-232 ch1 RXD signal
112
TXD5
O
RS-232 ch1 TXD signal
113
DTR5#
O
RS-232 ch1 DTR signal
114
RTS5#
O
RS-232 ch1 RTS signal
115
INT4#
I
Shift enable for option display
116
HTS2
O
8 bit serial port output (for option display)
117
SCK2#
O
Serial port shift clock output
(for option display)
(for option display)
118
STH2
I
8 bit serial port input (for option display)
119
DSR4#
I
MCR track 3 CLS signal
120
RXD4
I
MCR track 3 RDD signal
121
RXC4
I
MCR track 3 RCP signal
122
DSR2#
I
MCR track 2 CLS signal
123
RXD2
I
MCR track 2 RDD signal
124
RXC2
I
MCR track 2 RCP signal
125
DSR1#
I
MCR track 1 CLS signal
126
RXD1
I
MCR track 1 RDD signal
127
RXC1
I
MCR track 1 RCP signal
128
IPLON
O
IPL switch 0 ON signal to CPU
129
OPTCS#
O
Chip select base signal for expansion
option
option
130
VDD
-
+3.3V
131
GND
-
GND
132
VMEMC#
O
VRAM chip select signal
133
VIOC#
O
LCDC chip select signal
134
VWAIT#
I
LCDC wait signal
135
DSF2#
O
DPRAM chip select signal
136 EXWAIT#
I
External wait signal
137
EXINT0#
I
External interrupt signal 0
138
EXINT1#
I
External interrupt signal 1
139
EXINT2#
I
External interrupt signal 2
140
EXINT3#
I
External interrupt signal 3
141
BUSY3#
I
Fiscal memory BUZY signal (NU)
142
RXD3
I
Fiscal memory RXD signal (NU)
143
TRXC3
I
Fiscal memory CLOCK signal (NU)
144
TXD3
O
Fiscal memory TXD signal (NU)
145
TXRDY3
O
NU
146 TRXRDY3
O
NU
147
RXRDY3
O
Fiscal memory READY signal (NU)
148
DTR3#
O
Fiscal memory DTR signal (NU)
149
RTS3#
O
Fiscal memory RTS signal (NU)
150
DBTST
I
MPCA test pin (GND)
151
VRESC
O
NU
152
ST1#
O
Thermal head drive strobe signal 1
153
ST2#
O
Thermal head drive strobe signal 2
154
ST3#
O
Thermal head drive strobe signal 3
155
GND
-
GND
156
GND
-
GND
157
VDD
-
+3.3V
158
ST4#
O
Thermal head drive strobe signal 4
159
ST5#
O
Thermal head drive strobe signal 5 (NU)
160
GND
-
GND
161
ST6#
O
Thermal head drive strobe signal 6 (NU)
162
LATCH#
O
Thermal head latch signal
Pin
No.
Name
IN/OUT
Description
163
SO
O
Thermal head serial output data
164
GND
-
GND
165
CLOCK
O
Thermal head clock signal
166
SI
I
Thermal head serial return data
167
DTCS
O
Printer control select signal (GND)
168
LCDWT
I
Wait request signal to CPU (+3.3V)
169
DTST#
I
MPCA test pin (+3.3V)
170
INHDEC
I
CSEN# enable signal (GND)
171
CSEN#
I
TPRC chip select (GND)
172
TTST2#
I
MPCA test pin (+3.3V)
173
TTST1#
I
MPCA test pin (+3.3V)
174
TIRQ#
O
TPRC interrupt request
175
INH#
I
Thermal head drive inhibit
176
RPE
I
Receipt paper end signal
177
JPE
I
Journal paper end signal
178
PHUP
I
Printer head up signal
179
PCRES
I
Auto cutter unit reset signal
180
PFP
I
Auto cutter unit FP signal
181
VHCOM
I
Head drive common power control
182
GND
-
GND
183
VDD
-
+3.3V
184
RVPON
O
Receipt side paper feed pulse motor
common power control signal
common power control signal
185
JVPON
O
Journal side paper feed pulse motor
common power control signal (NU)
common power control signal (NU)
186
CTBO
O
Cutter motor control signal
187
CTAO
O
Cutter motor control signal
188
RDS
O
Receipt side paper feed pulse motor
drive signal, phase D
drive signal, phase D
189
RCS
O
Receipt side paper feed pulse motor
drive signal, phase C
drive signal, phase C
190
RBS
O
Receipt side paper feed pulse motor
drive signal, phase B
drive signal, phase B
191
RAS
O
Receipt side paper feed pulse motor
drive signal, phase A
drive signal, phase A
192
JDS
O
Journal side paper feed pulse motor
drive signal, phase D
drive signal, phase D
193
JCS
O
Journal side paper feed pulse motor
drive signal, phase C
drive signal, phase C
194
JBS
O
Journal side paper feed pulse motor
drive signal, phase B
drive signal, phase B
195
JAS
O
Journal side paper feed pulse motor
drive signal, phase A
drive signal, phase A
196
PTRM
I
Receipt motor connector sens signal
197
PTJM
I
Journal motor connector sense signal
198
POPI
I
GND
199
BA15
O
Address bus 15 for PB-RAM
200
BA14
O
Address bus 14 for PB-RAM
201
GND
-
GND
202
BA13
O
Address bus 13 for PB-RAM
203
BA12
O
Address bus 12 for PB-RAM
204
BA11
O
Address bus 11 for PB-RAM
205
BA10
O
Address bus 10 for PB-RAM
206
BA9
O
Address bus 9 for PB-RAM
207
BA8
O
Address bus 8 for PB-RAM
208
VDD
-
+3.3V
2-3. CKDC9 (HD404728B02FS)
1) General description
The CKDC9 is a 4-bit microcomputer developed for the UP-600/700
and provides functions to control the real-time clock, keys, and dis-
plays. The basic functions of the CKDC7 are shown below.
and provides functions to control the real-time clock, keys, and dis-
plays. The basic functions of the CKDC7 are shown below.
Keys:
The CKDC9 is capable of controlling a maximum of 256
momentary keys. (Sharp 2-key rollover control)
Simultaneous scanning of key and switch
(When a key is scanned, the state of a mode and clerk
switch is also buffered. The host can scan the state of
switch together with the key entry data at the same time
the key is scanned.)
momentary keys. (Sharp 2-key rollover control)
Simultaneous scanning of key and switch
(When a key is scanned, the state of a mode and clerk
switch is also buffered. The host can scan the state of
switch together with the key entry data at the same time
the key is scanned.)
Switches:
Mode switch with 14 positions maximum
8-bit clerk (cashier) switch
2-bit feed switch
1-bit receipt on/off switch
1-bit option switch
4-bit general-purpose switch (1-bit is used for keyboard
select)
8-bit clerk (cashier) switch
2-bit feed switch
1-bit receipt on/off switch
1-bit option switch
4-bit general-purpose switch (1-bit is used for keyboard
select)
Displays:
16-column dot display
12-column 7-segment display (column digit selectable)
All column blink controlled for the dot and 7-segment dis-
play decimal point and indicators
Programmable patterns for 7-segment display:
Four patterns
Internal driver for 7-segment display
12-column 7-segment display (column digit selectable)
All column blink controlled for the dot and 7-segment dis-
play decimal point and indicators
Programmable patterns for 7-segment display:
Four patterns
Internal driver for 7-segment display
Buzzer:
Single tone control
Clock:
Year, month, day of month, day of week, hour, minute
Alarm:
Hour, minute
Interrupt request (event control):
Detection of key input, switch position change, alarm is-
sue, and counter overflow
sue, and counter overflow
2) Pin description
Pin
No.
Symbol
Signal
name
In/
Out
Function
1
SB
SB
Out
Segment B
2
SC
SC
Out
Segment C
3
SD
SD
Out
Segment D
4
SE
SE
Out
Segment E
5
SF
SF
Out
Segment F
6
SG
SG
Out
Segment G
7
P4
AP
Out
8
P0
NC
—
NC
9
P1
NC
—
NC
10
P2
DP
Out
Decimal point
11
P3
ID
Out
Indicator
12
MODR
VCC
—
+5V
13
CFSR
CFSR
In
Clerk key, Feed key, Switch
return signal
return signal
14
KEX0
NC
Out
NC
15
KEX1
NC
Out
NC
16
RQ
GND
—
GND
17
SKR0
VCC
—
+5V
18
ST0
ST0
Out
Key strobe signal
19
ST1
ST1
Out
Key strobe signal
20
ST2
ST2
Out
Key strobe signal
21
ST3
ST3
Out
Key strobe signal
22
POFF
POFF
In
Power off signal
23
STOP
STOP
In
STOP signal
24
DDIG
VCC
—
+5V
Pin
No.
Symbol
Signal
name
In/
Out
Function
25
DCS
DCS
—
Dot display controller chip select
DCS
DCS
26
VCC
VCKDC
—
+5V
27
SCK
SCK
In
Clock signal
28
HTS
HTS
In
Key data from host
29
STH
STH
Out
Key data to host
30
SDISP
GND
—
GND
31
BUZZ
BUZZ
Out
Buzzer
32
DSCK
DSCK
—
Dot display controller SCK
33
SRES
RESET
Out
Reset signal
34
DS0
DSO
—
Dot display controller SO
35
SHEN
SHEN
Out
Shift enable signal
36
IRQ
KRQ
Out
Key request signal
37
KR0
KR0
In
Key return signal
38
KR1
KR1
In
Key return signal
39
KR2
KR2
In
Key return signal
40
KR3
KR3
In
Key return signal
41
RESET
CKDCR
In
CKDC reset signal
42
OSC2
OSC2
—
Clock
43
OSC1
OSC1
—
Clock
44
GND
GND
—
GND
45
CL1
CL1
—
Time clock
46
CL2
CL2
—
Time clock
47
TEST
VCKDC
—
+5V
48
G0
G1
Out
Display digit signal
49
G1
G2
Out
Display digit signal
50
G2
G3
Out
Display digit signal
51
G3
G4
Out
Display digit signal
52
G4
G5
Out
Display digit signal
53
G5
G6
Out
Display digit signal
54
G6
G7
Out
Display digit signal
55
G7
G8
Out
Display digit signal
56
G8
G9
Out
Display digit signal
57
G9
G10
Out
Display digit signal
58
G10
G11
Out
Display digit signal
59
G11
NC
Out
NC
60
PO0
NC
NC
61
PO1
NC
NC
62
PO2
NC
—
NC
63
PO3
NC
—
NC
64
SA
SA
—
Segment A
2-4. LCD controller (M66271FB)
1) Pin configration
9
78
66
67
69
70
71
72
68
11
7
6
5
4
3
2
78
66
67
69
70
71
72
68
11
7
6
5
4
3
2
31
30
29
28
27
26
22
21
20
19
18
17
16
15
62
61
30
29
28
27
26
22
21
20
19
18
17
16
15
62
61
14
60
59
58
57
56
55
54
53
50
49
48
47
46
45
44
43
77
63
52
42
34
23
8
12
79
76
74
73
75
32
39
38
37
36
33
51
80
65
1
40
35
24
13
25
64
41
10
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
M
LCDENB
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
M
LCDENB
MPUCLK
OSC1
CP
LP
UD0
UD1
UD2
UD3
FLM
UD1
UD2
UD3
FLM
RESET
WAIT
MCS
RD
LWR
HWR
IOCS
MP
USEL
OSC2
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
BH
E
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VD
D
VD
D
VD
D
VD
D
VD
D
VD
D
VD
D
2) Pin configration
Pin
No.
Name
Description
1
VSS
GND
2
IOCS#
Chip select input for control register
3
HWR#
High write strobe input
4
LWR#
Low write strobe input
5
RD#
Read strobe input
6
MCS#
Chip select input for VRAM
7
WAIT#
WAIT output to MPU
8
VDD
+5V
9
MPUCLK
MPU clock
10
VSS
GND
11
RESET#
Reset input
12
MPUSEL
8/16-bit selective input to MPU
13
VSS
GND
14
BHE#
Bus high enable input
15
A0
MPU address bus 0
16
A1
MPU address bus 1
17
A2
MPU address bus 2
18
A3
MPU address bus 3
19
A4
MPU address bus 4
20
A5
MPU address bus 5
21
A6
MPU address bus 6
22
A7
MPU address bus 7
23
VDD
+5V
24
VSS
GND
25
VSS
GND
26
A8
MPU address bus 8
27
A9
MPU address bus 9
28
A10
MPU address bus 10
29
A11
MPU address bus 11
30
A12
MPU address bus 12
31
A13
MPU address bus 13
32
N.C
33
N.C
34
VDD
+5V
35
VSS
GND
36
N.C
37
N.C
38
N.C
39
N.C
40
VSS
GND
41
VSS
GND
42
VDD
+5V
43
D0
MPU data bus 0
44
D1
MPU data bus 1
45
D2
MPU data bus 2
46
D3
MPU data bus 3
47
D4
MPU data bus 4
48
D5
MPU data bus 5
49
D6
MPU data bus 6
50
D7
MPU data bus 7
51
VSS
GND
52
VDD
+5V
53
D8
MPU data bus 8
54
D9
MPU data bus 9
Pin
No.
Name
Description
55
D10
MPU data bus 10
56
D11
MPU data bus 11
57
D12
MPU data bus 12
58
D13
MPU data bus 13
59
D14
MPU data bus 14
60
D15
MPU data bus 15
61
LCDENB
LCD (ON/OFF) control signal input
62
M
LCD AC-conversion signal output
63
VDD
+5V
64
VSS
GND
65
VSS
GND
66
CP
Display data transfer clock
67
LP
Display data clutch pulse
68
FLM
FIRST LINE MARKER signal output
69
UD0
LCD display data bus 0
70
UD1
LCD display data bus 1
71
UD2
LCD display data bus 2
72
UD3
LCD display data bus 3
73
N.C
74
N.C
75
N.C
76
N.C
77
VDD
+5V
78
OSC1
Oscillation input terminal
79
OSC2
Oscillation output terminal
80
VSS
GND
3. Address map
3-1. Total memory space
The address map of the total memory space is shown below. As you
can see, the memory space is divided into the following 5 blocks:
can see, the memory space is divided into the following 5 blocks:
0page area (including the I/O area)
•
VRAM
•
RAM
•
ROM
•
Extended I/O area
3-2. 0page area
The 0page area consists of four spaces: the ROM mapped area,
internal and external I/O areas.
The ROM mapped space have been devised for the following pur-
poses:
internal and external I/O areas.
The ROM mapped space have been devised for the following pur-
poses:
Simplifying the procedure for booting the IPL program
Achieving high-speed accessing, and accessing by abbreviated
instructions.
instructions.
3-3. I/O areas
The addresses from 00FF80h to 00FFFFh are called the internal I/O
area.
The internal I/O area is a space where the control registers and
built-in ports inside the CPU are addressed.
The external I/O area is a space where the peripheral devices outside
the CPU or devices on an optional card are addressed.
area.
The internal I/O area is a space where the control registers and
built-in ports inside the CPU are addressed.
The external I/O area is a space where the peripheral devices outside
the CPU or devices on an optional card are addressed.
000000h
0 page area
(64KB)
00FFFFh
200000h
600000h
800000h
C00000h
C20000h
F00000h
FFFFFFh
Extended I/O area
(1MB)
(2MB)
Flash
EXTEND RAM
(4MB)
STD RAM (2MB)
(4MB)
VRAM (128KB)
EP-ROM
D00000h
* The expanded I/O area means
the space for the I/O device
addressed in the area excluding
the 0 page one.
MPCA8 uses FFFF00h to
FFFFFFh for the addressed
register (BAR) of SSP.
The I/O register for VGAC is
included.
the space for the I/O device
addressed in the area excluding
the 0 page one.
MPCA8 uses FFFF00h to
FFFFFFh for the addressed
register (BAR) of SSP.
The I/O register for VGAC is
included.
* In the 0 page area, lower 64KB
or less of the flash area is
mapped.
By mapping the ROM area, the
reset start and other vectors
become addressable.
or less of the flash area is
mapped.
By mapping the ROM area, the
reset start and other vectors
become addressable.
000000h
00FFFFh
00FF80h
00FE80h
Internal I/O area
External I/O area
ROM mapping area
I/O area
* The ROM area 200000h to
20FFFFh (ROS1 lower 64KB)
is mapped on the ROMmapping
area.
20FFFFh (ROS1 lower 64KB)
is mapped on the ROMmapping
area.
* The internal I/O area is used
for peripheral modules inside
the CPU; the external I/O area
is used for peripheral modules
outside the CPU.
For more information, refer to
the H8/510 hardware manual
and peripheral device
specification.
for peripheral modules inside
the CPU; the external I/O area
is used for peripheral modules
outside the CPU.
For more information, refer to
the H8/510 hardware manual
and peripheral device
specification.
00FE80h
00FF80h
00FFA0h
00FFB0h
00FFB4h
00FFB8h
00FFBCh
00FFC0h
00FFD0h
00FFE0h
00FFF0h
00FFFFh
Internal I/O area
MPCCS
MCR1Z
MCR2Z
OPCCS2
OPCCS1
T/PZ
OPTCSZ
Expanded MPC
(not used)
MCR3Z
CPCSZ (not used)
TPRC1
* CPCSZ is CPC select for
Centronics Interface.
Centronics Interface.
* MPCCS and expanded MPC
signals are base signals for
MPCA9 internal register
decode. There is no external
signal.
signals are base signals for
MPCA9 internal register
decode. There is no external
signal.
* MCR1Z, MCR2Z and MCR3Z
* MCR1Z and MCR2Z are chip
are chip select signals for the
magnet card reader.
(Use lower 2bytes.)
(Use lower 2bytes.)
* T/PZ is the internal decode
signal for USART built in
MPCA9. Thereis no external
signal. (Use lower 2bytes.)
signal for USART built in
MPCA9. Thereis no external
signal. (Use lower 2bytes.)
* OPCCS1 and OPCCS2
signals are decoded inside
the OPC (OPTION PERIP-
HERAL CONTROLLER)
using the option decode
signal OPTCS. There is no
external signal.
signals are decoded inside
the OPC (OPTION PERIP-
HERAL CONTROLLER)
using the option decode
signal OPTCS. There is no
external signal.
TPRC1 is built in by
MPCA9.
MPCA9.
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