DOWNLOAD Sharp UP-600 / UP-700 (serv.man25) Service Manual ↓ Size: 2.63 MB | Pages: 51 in PDF or view online for FREE

Model
UP-600 UP-700 (serv.man25)
Pages
51
Size
2.63 MB
Type
PDF
Document
Service Manual
Brand
Device
ECR / UP600-700 Service Manual
File
up-600-up-700-sm25.pdf
Date

Sharp UP-600 / UP-700 (serv.man25) Service Manual ▷ View online

3) Pin description
Pin
No.
Symbol
Signal
name
In/
Out
Function
1
/RES
/RESET
In
Reset signal 
2
NMI
NMI
In
Non-maskable interrupt input
for SSP interrupt input. 
3
VSS
GND
In
GND
4
D0
D0
I/O
Data bus 
5
D1
D1
I/O
Data bus 
6
D2
D2
I/O
Data bus 
7
D3
D3
I/O
Data bus 
8
D4
D4
I/O
Data bus 
9
D5
D5
I/O
Data bus 
10
D6
D6
I/O
Data bus 
11
D7
D7
I/O
Data bus 
12
D8
D8
I/O
Data bus 
13
D9
D9
I/O
Data bus 
14
D10
D10
I/O
Data bus 
15
D11
D11
I/O
Data bus 
16
D12
D12
I/O
Data bus 
17
D13
D13
I/O
Data bus 
18
D14
D14
I/O
Data bus 
19
D15
D15
I/O
Data bus 
20
VSS
GND
In
GND
21
A0
A0
Out
Address bus 
22
A1
A1
Out
Address bus 
23
A2
A2
Out
Address bus 
24
A3
A3
Out
Address bus 
25
A4
A4
Out
Address bus 
26
A5
A5
Out
Address bus 
27
A6
A6
Out
Address bus 
28
A7
A7
Out
Address bus 
29
A8
A8
Out
Address bus 
30
A9
A9
Out
Address bus 
31
A10
A10
Out
Address bus 
32
A11
A11
Out
Address bus 
33
A12
A12
Out
Address bus 
34
A13
A13
Out
Address bus 
35
A14
A14
Out
Address bus 
36
A15
A15
Out
Address bus 
37
VSS
GND
In
GND
38
A16
A16
Out
Address bus 
39
A17
A17
Out
Address bus 
40
A18
A18
Out
Address bus 
41
A19
A19
Out
Address bus 
42
A20
A20
Out
Address bus 
43
A21
A21
Out
Address bus 
44
A22
A22
Out
Address bus
45
A23
A23
Out
Address bus 
46
VSS
GND
In
GND
47
P30
/WAIT
In
Wait signal 
48
P31
/BACK
Out
Bus control request
acknowledge signal 
49
P32
/BREQ
In
Bus control request signal  
50
P33
DOPS
In
Drawer open signal 
51
P34
/DR0
Out
Option drawer open signal 
52
P35
/DR1
Out
Option drawer open signal 
53
P36
NC
NC
NC
54
P37
NC
NC
NC 
55
VCC
VCC
In
+5V 
56
P40
VCC
In
+5V 
57
P41
GND
In
GND 
58
P42
GND
In
GND 
Pin
No.
Symbol
Signal
name
In/
Out
Function
59
P43
GND
In
GND 
60
P44
MCRINT
In
MCR interrupt signal 
61
P45
GND
In
GND 
62
P46
/SHEN
In
CKDC interface shift enable
signal 
63
P47
GND
In
GND 
64
VSS
GND
In
GND 
65
P50
Out
/DTR2 : Data Terminal Ready2
66
P51
In
/DSR2 : Data Set Ready2
67
P52
In
/CTS2 : Clear To Send2
68
P53
In
/DCD2 : Carriar Detect2
69
P54
In
NC
70
P55
NC
Out
/RTS2:Request To Send2
71
P56
In
/CI2:Calling Indicator2
72
P57
/STOP
Out
System reset output signal 
73
P60
/IPLON0
In
From IPL SW
74
P61
/IPLON1
In
From IPL SW
75
P62
GND
In
GND 
76
P63
NORDY
In
Flash Memory ready ("H" active)
77
P64
FVPON
Out
Flash Memory write protect ("L"
active)
78
P65
BANK
Out
For IPL ROM
79
P66
GND
In
GND
80
P67
GND
In
GND
81
VSS
GND
In
GND
82
AVSS
GND
In
GND
83
P70
GND
In
GND
84
P71
GND
In
GND
85
P72
GND
In
GND
86
P73
GND
In
GND
87
AVCC
VCC
In
+5V
88
VCC
VCC
In
+5V
89
/IRQ0
/IRQ0
In
Interrupt signal 0
90
/IRQ1
/IRQ1
In
Interrupt signal 1 
91
/IRQ2
UASCK
In
Synchronizing shift clock signal
for USART
92
/IRQ3
SCKI
Out
CKDC interface synchronizing
shift clock 
93
RXD1
/RCVDT2
In
RXD signal for RS232
94
TXD1
TXD2
Out
TXD signal for RS232
95
RXD2
RXDI
In
CKDC interface shift input data 
96
TXD2
TXDI
Out
CKDC interface shift output
data 
97
VSS
GND
In
GND
98
EXTAL
EXTAL
In
Crystal oscillator connection
19.6MHz 
99
XTAL
XTAL
In
Crystal oscillator connection
19.6MHz 
100
VSS
GND
In
GND
101
X
#
Out
System clock
102
E
NC
NC
NC
103
/AS
/AS
Out
Address strobe
104
RD
/RD
Out
Read signal
105
/HWR
/HWR
Out
Write signal (HIGH)
106
/LWR
/LWR
Out
Write signal (LOW) 
107
/RFSH
/RFSH
Out
Refresh cycle signal
108
VCC
VCC
In
+5V
109
MD0
IPLON0
In
From IPL SW
110
MD1
IPLON0
In
From IPL SW
111
MD2
/IPLON0
In
From IPL SW
112
/STBY
VCC
In
+5V
2-2. G.A.(MPCA9)
1) Pin configuration
VDD
ST4# DOT4
ST5# DOT5
GND
ST6# DOT6
LATCH# DOT7
SO
 DOT8
GND
CLOCK DOT
9
SI
DTCS
WO LCDWT
DTST#
INHDEC
CSEN#
TTST2#
TTST1#
TIRQ#
INH#
RPE
JPE
PHUP PE
PCRES
PFP
VHCOM
GND
VDD
RVPON TRG#
JVPON TRG
CTBO PCUT#
CTAO F
CUT#
RDS PRST#
RCS PTMG#
RBS RJMTD
RAS RJMTS
JDS STA
M
P#
JCS VF#
JBS RF#
JAS JF#
PTRM RJTMG
PTJM TRGI
PO
PI RJRST
BA
15
BA
14
GND
BA
13
BA
12
BA
11
BA
10
BA
9
BA
8
VDD
GND
GND
BA7
BA6
BA5
BA4
BA3
BA2
BA1
GND
BA0
BWR#
BRD#
BRAS
BRAS#
BD7
BD6
BD5
GND
BD4
BD3
GND
BD2
BD1
BD0
GND
VDD
INT3#
INT2#
INT1#
INT0#
HTS1
SCK1#
STH1
IPLON#
RESET#
UTST#
USEL0
USEL1
USEL2
MCRINT
WAIT#
FROS1#
RASPN1
RASPN2
EPROM1#
DSEX#
RXDH
TXDH
SCKH
GND
GND
15
7
15
8
15
9
16
0
16
1
16
2
16
3
16
4
16
5
16
6
16
7
16
8
16
9
17
0
17
1
17
2
17
3
17
4
17
5
17
6
17
7
17
8
17
9
18
0
18
1
18
2
18
3
18
4
18
5
18
6
18
7
18
8
18
9
19
0
19
1
19
2
19
3
19
4
19
5
19
6
19
7
19
8
19
9
20
0
20
1
20
2
20
3
20
4
20
5
20
6
20
7
20
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
VDD
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
GND
VDD
D7
D6
D5
GND
D4
D3
GND
D2
D1
D0
GND
SS
PRQ
#
IRQ1
#
IRQ0
#
WR#
RD#
AS
#
PHA
I
MD0
MD1
UASCK
GND
OS
I1
OS
O1
VDD
GND
GND
ST3# DOT3
ST2# DOT2
ST1# DOT1
NC
TTHR
RTS3#
DTR3#
RXRDY3
TRXRDY3
TXD3
TXRDY3
TRXC3
RXD3
BUSY3#
EXINT3#
EXINT2#
EXINT1#
EXINT0#
EXWAIT#
DSF2#
VWAIT#
DSF1#
DSCX#
GND
VDD
OPTCS#
IPLON
RXC1
RXD1
DSR1#
RXC2
RXD2
DSR2#
RXC4
RXD4
DSR4#
STH2
SCK2#
HTS2
INT4#
RTS5#
DTR5#
TXD5
RXD5
CTS5#
DSR5#
CI5#
CD5#
GND
GND
10
4
10
3
10
2
10
1
10
0
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
2) Block diagram
A23~A0
D7~D0
/AS,/RD,/WR
PHAI,/RESET
MPCA9
MPCA
TPRC1
OPC
INT4#~INT0#
MCRINT
WAIT#
FROS1#,EPROM1#
RASPN1,2
DSEX#
RXDH,TXDH,SCKH
OSO1,OSI1
USACK
MD1,MD2
IRQ0#
SSPRQ#
HTS2,SCK2,STH2
RXD4,RXC4,DSR4#
RXD2,RXC2,DSR2#
RXD1,RXC1,DSR1#
IPLON
OPTCS#
VMEMC#,VIOC#
DSF2#
VWAIT#,EXWAIT#
EXINT0#,EXINT1#
EXINT2#,EXINT3#
BUSY3#,RXD3,TXD3
TRXC3,TXRDY3
TRXRDY3,RXRDY3
DTR3#,RTS3#
VRESC
DTCS,DTST#
LCDWT
USEL2~USEL0, UTST#,
BA15~BA0
BD7~BD0
BWR#,BRD#
BRAS,BRAS#
ST1#~ST6#
LATCH#
SI,SO,CLOCK
PHUP,VHCOM
CSEN#,INH#
TIRQ#
RPE,JPE
PCRES,PFP
RVPON,JVPON
CTBO,CTAO
RAS,RBS,RCS,RDS
JAS,JBS,JCS,JDS
PTRM,PTJM
POPI
TTST1#,TTST2#
IRQ1#
TXD5,RXD5
DTR5#,RTS5#
DSR5#,CTS5#
CD5#,CI5#
DBTST
3) Pin description
Pin
No.
Name
IN/OUT
Description 
1
GND
-
GND
2
GND
-
GND
3
BA7
O
Address bus 7 for PB-RAM
4
BA6
O
Address bus 6 for PB-RAM
5
BA5
O
Address bus 5 for PB-RAM
6
BA4
O
Address bus 4 for PB-RAM
7
BA3
O
Address bus 3 for PB-RAM
8
BA2
O
Address bus 2 for PB-RAM
9
BA1
O
Address bus 1 for PB-RAM
10
GND
-
GND
11
BA0
O
Address bus 0 for PB-RAM
12
BWR#
O
PB-RAM write strobe signal
13
BRD#
O
PB-RAM read strobe signal
14
BRAS
O
PB-RAM chip select : Active High (NU)
15
BRAS#
O
PB-RAM chip select : Active Low
16
BD7
I/O
Data Bus 7 for PB-RAM
17
BD6
I/O
Data Bus 6 for PB-RAM
18
BD5
I/O
Data Bus 5 for PB-RAM
19
GND
-
GND
20
BD4
I/O
Data Bus 4 for PB-RAM
21
BD3
I/O
Data Bus 3 for PB-RAM
22
GND
-
GND
23
BD2
I/O
Data Bus 2 for PB-RAM
24
BD1
I/O
Data Bus 1 for PB-RAM
25
BD0
I/O
Data Bus 0 for PB-RAM
26
GND
-
GND
27
VDD
-
+3.3V
28
INT3#
I
Interrupt signal 3 (NU)
29
INT2#
I
Shift enable for CKDC9
30
INT1#
I
Keyboard request for CKDC9
31
INT0#
I
Power off signal input
32
HTS1
O
8 bit serial port output (for CKDC9)
33
SCK1#
O
Serial port shift clock output (for CKDC9)
34
STH1
I
8 bit serial port input (for CKDC9)
35
IPLON#
I
IPL switch 0 ON signal
36
RESET#
I
MPCA reset
37
UTST#
I
MPCA test pin (+3.3V)
38
USEL0
I
MPCA test pin (GND)
39
USEL1
I
MPCA test pin (GND)
40
USEL2
I
MPCA test pin (GND)
41
MCRINT
O
MCR interrupt signal
42
WAIT#
O
Wait request signal
43
FROS1#
O
Flash ROM 1 chip select signal
44
RASPN1
O
RAM 1 chip select signal
45
RASPN2
O
RAM 2 chip select signal
46
EPROM1#
O
EP-ROM 1 chip select signal
47
DSEX#
O
EP-ROM 2 chip select signal
48
RXDH
O
8 bit serial port output to CPU
49
TXDH
I
8 bit serial port input from CPU
50
SCKH
I
Serial port shift clock input from CPU
51
GND
-
GND
52
GND
-
GND
53
VDD
-
+3.3V
54
OSO1
O
System clock (7.37MHz)
Pin
No.
Name
IN/OUT
Description 
55
OSI1
I
System clock (7.37MHz)
56
GND
-
GND
57
UASCK
O
USAT clock to CPU
58
MD1
I
MPCA test pin (GND)
59
MD0
I
MPCA test pin (GND)
60
PHAI
I
System clock (9.83MHz)
61
AS#
I
Address strobe
62
RD#
I
Read Strobe
63
WR#
I
Write Strobe
64
IRQ0#
O
Interrupt request 0 to CPU
65
IRQ1#
O
Interrupt request 1 to CPU
66
SSPRQ#
O
SSP interrupt request to CPU
67
GND
-
GND
68
D0
I/O
Data Bus 0
69
D1
I/O
Data Bus 1
70
D2
I/O
Data Bus 2
71
GND
-
GND
72
D3
I/O
Data Bus 3
73
D4
I/O
Data Bus 4
74
GND
-
GND
75
D5
I/O
Data Bus 5
76
D6
I/O
Data Bus 6
77
D7
I/O
Data Bus 7
78
VDD
-
+3.3V
79
GND
-
GND
80
A0
I
Address bus 0
81
A1
I
Address bus 1
82
A2
I
Address bus 2
83
A3
I
Address bus 3
84
A4
I
Address bus 4
85
A5
I
Address bus 5
86
A6
I
Address bus 6
87
A7
I
Address bus 7
88
A8
I
Address bus 8
89
A9
I
Address bus 9
90
A10
I
Address bus 10
91
A11
I
Address bus 11
92
A12
I
Address bus 12
93
A13
I
Address bus 13
94
A14
I
Address bus 14
95
A15
I
Address bus 15
96
A16
I
Address bus 16
97
A17
I
Address bus 17
98
A18
I
Address bus 18
99
A19
I
Address bus 19
100
A20
I
Address bus 20
101
A21
I
Address bus 21
102
A22
I
Address bus 22
103
A23
I
Address bus 23
104
VDD
-
+3.3V
105
GND
-
GND
106
GND
-
GND
107
CD5#
I
RS-232 ch1 CD signal
108
CI5#
I
RS-232 ch1 CI signal
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