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Fig.5 shows the ROM space. The UP-600/700 uses 2MB of NOR-
type flash memory instead of conventional ROM, so that the FROS1#
from the MPCA9 is input into the chip enable of the flash memory.

The VRAM is the display memory of the LCD.

The addresses from F00000h to FFFFFFh are called an extended I/O
area. The UP-600/700 uses the following addresses as the break
address register (BAR) for SSP.

•

FFFF00h 

∼

 FFFFFFh

The UP-600/700 uses a 320 x 240 dot monochromatic LCD for the
main display and VGAC (M66271) for the display controller which is
connected to H8/510 in the ISA bus connection mode.

Here is the block diagram of the LCD and its allied components.

The LCD panel uses a dot-matrix liquid crystal module with mono-
chromatic STN and CCFT backlight. The resolution is 320 x 240.

Matsushita VGAC (M66271) is used for display controller.

VRAM is present on the address space of the CPU and it is possible
to write and read data from the CPU side through the lower 9600 byte
address of 128 KB size in addresses C00000H ~ C1FFFFH.
C00000H - C1FFFH:

The LCD is turned on and off by controlling the bias power supply for
the LCD using the terminal LCDENB of the M66271.
LCDENB is in low level when resetting. When bit 0 of the mode
resistor of the M66271 by software is set to high level, the power is
supplied to the LCD, thus turning on the LCD.

The backlight ON/OFF is controlled by the same LCDENB as used for
controlling the LCD ON.

•

Luminance: Luminance is adjusted with an inverter which has dim-

ming function. (Fixed)

•

Contrast:

Contrast is adjusted by controlling the contrast adjust-
ment voltage (VO) of the LCD.

The UP-600/700 can incorporate a UP-P16DP for the customer dis-
play.

The device is HYUNDAI 4MB SRAM (HY628400ALLT2-70 512K 8bit)
with access time of 70ns.

200000h

(MAX4MB)

ROS1

5FFFFF

* Lower 64KB of the ROS1 is
  mapped on the 0 page area.

* ROS1 is decoded by
  MPCA9.

600000h

C00000h

800000h

A00000h

CFFFFFh

RASPN1

VRAM

(2MB)

RASPN2

(4MB)

(1MB)

* All the decode signals in the
  area in the figure are supported
  by MPCA9.

* RAS1 signals from MPCA9
  correspond to 2MB 600000h to
  7FFFFFh.

* OPTION RAM board (2MB and
  4MB) interfaces using RAS2
  as the base signal.

* The actual VRAM is 128KB,
  but it is accessed by every 
 128KB of bank according to
  VGAC specification.

CPU  H8/510

SD0-7 

A0-13 

RD#

RD# 

HWR#

LWR# 

PHAI

CLK 

WAIT#

UD0-3

LD0-3 

WAIT#      

LCD (320 x 240)

MPCA8

LP

LP 

LCDWT

FLM

FP 

 VIO#

IOCS# 

DCLK

DCLK 

VMEM# MCS# 

VEE

BACKLIGHT

M66271

M

BIAS 

POWER

LCDENB

8bitMPU connection setting 

HWR# : "H"

BHE# : "H"

MPUSEL : "L"

The figure below shows a typical pseudo SRAM interface in the UP-
600/700.

Standard SRAM is decoded as follows by the RASPN1 signal.

780000h 

∼

 7FFFFFh

The base signal is 2MB. It thus wraparounds with 600000H 

∼

7FFFFFH 1.5MB.

Here is the explanation for the interface of NOR-type flash memory.
The device is Sharp’s LH28F016SU flash memory which consists of
512 K words 

×

 16 or 1 MB 

×

 8, with 32 blocks of 64 KB.

The figure below shows a typical interface for the LH28F016SU of the
UP-600/700 system.

After resetting, the device automatically enters the array read mode
and perform the same action as the usual ROM, thus requiring no
special consideration when reading data.

Data can be written at high speed by using the page buffer.

The UP-600/700 uses flash memory in the place of EPROM, so it is
possible to rewrite the contents of the flash memory in changing the
program. However, since the existing gate array MPCA8 is used, it is
also possible to use the conventional SSP.

Like the MPCA5 ~ 8, the MPCA9 adopts the break address register
comparison method for detecting addresses. The operation of this
method is briefly explained below.

The gate array always compares the break address register (BAR)
built in the gate array, with the address bus to monitor the address
bus.

If both agree, the gate array outputs the NMI signal to the CPU, which
in turn shifts from normal handling to exception handling.

In both the MPCA5 ~ 8 and the MPCA9, SSP is achieved by the
above operation.

The setting of the break address register (BAR) is directly written in
the addresses from FFFF00h to FFFFFFh.

There are roughly two types of interrupts:

•

Internal interrupts: Controlled inside the CPU

•

External interrupts: Input into the CPU from outside

Device interrupts built in the CPU are used for the following applica-
tions:

Event factor

Application

SC11

Interrupt source as RS232 : CH8

SC12

Not used (SC1 is used for CKDC interface.)

FRT1

(ICI)
(OCRA)
(OCRB)
(OVF)

INTMCR 

∼

 MCR interrupt (to FT11 terminal)

FRT2

(ICI)

Standard SHEN event (for CKDC)

(OCRA)

Simple IRC timer event

(OCRB)

RS232 timer event

(OVF)

System timer (53 ms)

TMR

(CMA)
(CMB)
(OVF)

WDT

(OVF)

Drawer open timer

A/D

Not used

NMI

SSP request

The following types of external interrupts are available:

•

NMI (SSP)

•

IRQ0 (Standard I/O interrupt)

•

IRQ1 (RS232 interrupt)

•

IRQ2 (Not Used)

•

IRQ3 (Used as SCK terminal)

S RAM(Standard)

A0~A18

A0~A18

A0~A21

D0~D7

D8~D15

/RD

/RD

MPCA9

/WR

/HWR

/CE

S RAM(Option)

A0~
A18

RASPN2

74LV138

A19~
A21

A,B,C

Y

/G

/RESET

RASPN1

The weight control function built in the MPCA9 is used to provide an
interface with low-speed devices.

The block diagram of the wait control function is shown.

In the figure, the decoder, wait enabling register, AND-OR sections
are the same as those in the MPCA6 or 7, but other components are
newly incorporated in the MPCA5.

EXWAITZ and WAITZ are external weight signals which are to be
ORed inside the MPCA9 and output to the WAITZ. The EXWAITZ is a
general-purpose wait request terminal, and WAITZ is the wait request
signal from the VGA controller.

The UP-600/700 on CKDC9 for the CKDC PWB and one CKDC9 for
POLE display (option) to carry out the following control operations.

CKDC PWB CKDC9:

•

Clock (second data readable)

•

Buzzer

•

System reset

•

Key/Clerk switch

POLE CKDC9(UP-P16DP)

•

Customer display tube

CKDC9 is connected through the MPCA8.

Selector

/AS

 

CLK    WAIT RESET Counter

START

/RESET

/EXWAIT

/VWAIT

/LCDWAIT

/WAITZ

φ

WAIT

enable

For

RASP-

/RESET for 1,2,3WAIT

WAIT

enable

For

MISC

WAIT

Count

For

RASP

D

/Q

Selector

Selector

/RESET

/RESET
for 
1WAIT

/RESET

WAIT

Count

For

MISC

WAIT

Count

For

RASPN

WAIT

Count

For

RASPN

D

/Q

D

/Q

WAIT

enable

For

VRAM

•

VGA

I/O

D

/Q

Terminal autoweight signal

TXD2(P87)
SCK2(P83)

RXD2(P84)

TXDI
SCKI

RXDI

INT1

IRQ0

IRQ0

RES

STOP

(P57)

RESET

RESET

STH

HTS
SCK

KRQ
SHEN

STOP

HTS2
SCK2
STH2

HTS
SCK
STH

SRES

RESET

SW

FTI2

HTS1
SCK1
STH1

HTS
SCK
STH

INT4

SHEN

RESET

reset from MAIN

UP-P16DP/UP-I16DP

Key

Buzzer

The expanded RAM connector terminals are shown in the table.

The 40-pin RAM is used for the connector.

Extension RAM connector terminals

Signal Name

Pin No.

Pin No.

Signal Name

+5V

1

2

N.C.

HWR

3

4

N.C.

GND

5

6

A21

A20

7

8

A19

A18

9

10

A17

A16

11

12

A15

A14

13

14

A13

A12

15

16

A11

A10

17

18

A9

A8

19

20

A7

A6

21

22

A5

A4

23

24

A3

A2

25

26

A1

A0

27

28

RD

D7

29

30

D6

D5

31

32

D4

D3

33

34

D2

D1

35

36

D0

RASPN2

37

38

VCKDC

GND

39

40

GND

The reset sequence block diagram is shown below. Note that RESET
signal (system reset) and CKDCR signal (CKDC reset) are different
from each other.

The flow of signal processing at the time of the power supply turning
On/Off is as follows:

<Power OFF>

Power supply

MPCA9

CPU

CKDC9

1

POFF 

 L

2

IRQ0 

 L

3

STOP 

 L

4

RESET 

 L

(System reset)

<Power ON>

Power supply

MPCA9

CPU

CKDC9

1

POFF 

 H

2

STOP 

 H

3

RESET 

 H

(System reset)

The table below shows the timing chart.

POFF 

CKDCR 

(CKDC reset) 

VCC 

POFF 

INT0 

IRQ0 

STOP 

RESET 

(System reset) 

SLIDE 
SW 

PG GOOD

RESET

STOP

SHEN

SCK

+5V,+12V

(POFF)

10ms MIN

8 PULSE

 

(System)

Power supply On

Power supply Off