Sharp LC-42XL2E (serv.man5) Service Manual ▷ View online
LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
5 – 37
2.19. IC8702 (RH-iXC0150WJQZY)
2.19.1 Block Diagram
2.19.2 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
1
VIN
I
Voltage input to VCXO. Zero to 3.3V signal which controls the VCXO frequency.
2
S0
I
Select pin 0. Internal pull-up resistor.
3
S1
I
Select pin 1. Internal pull-up resistor.
4
VDD
—
Connect to +3.3 V.
5
CLK1
O
Output clock 1. Weak internal pull-down when tri-state.
6
CLK2
O
Output clock 2. Weak internal pull-down when tri-state.
7
GND
—
Connect to ground.
8
X1
I
Crystal input. Connect this pin to a crystal.
9
X2
O
Crystal Output. Connect this pin to a crystal.
10
VDD
—
Connect to +3.3 V.
11
CLK3
O
Output clock 3. Weak internal pull-down when tri-state.
12
CLK4
O
Output clock 4. Weak internal pull-down when tri-state.
13
GND
—
Connect to ground.
14
PDTS
I
Power-down tri-state. Powers down entire chip and tri-states clock outputs when low. Internal pull-up resistor.
15
VDD
—
Connect to +3.3 V.
16
S2
I
Select pin 2. Internal pull-up resistor.
LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
5 – 38
2.20. IC9101 (RH-iXC121WJN8Q)
2.20.1 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
1
D3.3V
—
Power supply(+3.3V)
2
N_CPLD_CS0
I
HiDTV CS0
⋅⋅⋅ Flash
3
XERE
I
HiDTV PCI_BUS OE#
4
ROM_CE
I
BOOT ROM CE input
5
N_CPLD_CS1
I
HiDTV CS1
⋅⋅⋅ CPLD
6
XEWE
I
HiDTV PCI_BUS WE#
7
NC
O
HiDTV PCI_BUS ACK#
8
D3.3V
—
Power supply (+3.3V)
9
FRDA_0
I/O
For HiDTV PCI_BUS DATA0/CPLD control
10
FRDA_1
I/O
For HiDTV PCI_BUS DATA1/CPLD control
11
FRDA_2
I/O
For HiDTV PCI_BUS DATA2/CPLD control
12
FRDA_3
I/O
For HiDTV PCI_BUS DATA3/CPLD control
13
FRDA_4
I/O
For HiDTV PCI_BUS DATA4/CPLD control
14
FRDA_5
I/O
For HiDTV PCI_BUS DATA5/CPLD control
15
FRDA_6
I/O
For HiDTV PCI_BUS DATA6/CPLD control
16
FRDA_7
I/O
For HiDTV PCI_BUS DATA7/CPLD control
17
FRAA_0
I
HiDTV PCI_BUS ADDRESS0
18
GND_B
—
Ground
19
FRAA_1
I
For HiDTV PCI_BUS ADDRESS1/CPLD control
20
FRAA_2
I
For HiDTV PCI_BUS ADDRESS2/CPLD control
21
FRAA_3
I
For HiDTV PCI_BUS ADDRESS3/CPLD control
22
FRAA_4
I
For HiDTV PCI_BUS ADDRESS4/CPLD control
23
FRAA_5
I
For HiDTV PCI_BUS ADDRESS5/CPLD control
24
N_CPLD2_CNF_DONE
I
FPGA Config
25
FRAA_6
I
For HiDTV PCI_BUS ADDRESS6/CPLD control
26
FRAA_22
I
HiDTV PCI_BUS ADDRESS22
27
FRAA_23
I
HiDTV PCI_BUS ADDRESS23
28
FRAA_24
I
HiDTV PCI_BUS ADDRESS24
29
GND_B
—
Ground
30
SBCLK_27M
I
HiDTV PCI_BUS CLOCK (27MHz)
31
3.3V_DPOW_DETECT
I
DPOW system 3.3V detection
32
NACE_N
I
NAND-FLASH CE output
33
CODEC_RST
O
CODEC reset
34
N_VCCH_RST
O
HiDTV standby reset
35
N_COLD_RST
O
HiDTV main reset
36
GND_B
—
Ground
37
D3.3V
—
Power supply (+3.3V)
38
CPLD_33M
I
System clock (33MHz)
39
N_FLS_RST
O
On-Board Flash reset
40
N_EXT_RST
O
External Flash reset
41
N_EXT_BOOT
I
Flash start-up discrimination (H = On-Board, L = External)
42
D3.3V
—
Power supply(+3.3V)
43
ROM_ADD22
O
On-Board/External Flash ADDRESS22
44
ROM_ADD23
O
On-Board/External Flash ADDRESS23
45
ROM_ADD24
O
On-Board/External Flash ADDRESS24
46
N_ROM_OE
O
On-Board/External Flash OE#
47
GND_B
—
Ground
48
N_ROM_WE
O
On-Board/External Flash WE#
49
N_EXT_CE
O
External Flash CE#
50
N_FLS_CS0
O
On-Board Flash CE0#
51
N_CPLD_INT0
O
HiDTV (Level interrupt, Active Low)
52
N_CPLD_INT1
O
SVP_WX (Level interrupt, Active Low)
53
DSP_RST
O
DSP reset
54
N_TUNER_INT
INT
CE6353 (Level interrupt, Active Low)
55
D3.3V
—
Power supply (+3.3V)
56
VON
O
Inverter ON/OFF control
57
PE
O
PANEL controller control signal
58
A_MUTE_ADIF
I
HDMI_MUTE control signal
59
BUS_SPLIT
O
Slow bus/video bus enable (Isplation supported)
60
I2C_EXT
O
I2C bus enable (Isolation supported)
61
STB
O
Inverter ON/OFF control
LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
5 – 39
62
GND_B
—
Ground
63
CPLD_TDI
I
64
PNL_WP
O
VCOM Write Protect control signal
65
CPLD_TMS
O
66
FE_RST
O
CE6353 reset
67
CPLD_TCK
O
68
FEPG0_COMP
O
Sleep signal
69
FEPG1_LOCK
I
Signal LOCK detection
70
FERR_UNCOR
I
Error flag
71
N_TS1_DEMORST
O
TS1 demodulator reset
72
GND_B
—
Ground
73
D3.3V
—
Power supply (+3.3V)
74
EXTRG
O
Partner
75
DRSTMSK
O
Partner
76
N_IRS_INT
I
IrSS interrupt request
77
CLON_RC
O
For controlling clone remote control
78
DTM_RST
O
Reset signal for DTM
79
N_IRS_RST
O
IrSS reset signal
80
DTM_GPIO0
I
Control signal for DTM (GPIO0)
81
DTM_GPIO1
O
Control signal for DTM (GPIO1)
82
DTM_UART_INT
I
Interrupt request of UART-I2C conversion IC for DTM
83
DTM_UART_RST
O
Reset of UART-I2C conversion IC for DTM
84
D3.3V
—
Power supply (+3.3V)
85
AGC_SEL
O
Digital/Analog AGC switching control
86
HP_MUTE
O
HP audio mute control
87
HP_PLUG
I
HP connection detection
88
CION
O
VCC/ON signal for PCMCIA
89
GND_B
—
Ground
90
GND_B
—
Ground
91
SC2_MUTE
O
SCART2 audio mute control
92
SPDIF_MUTE
O
SPDIF audio mute control
93
SC_MUTE
O
SCART1 audio mute control
94
S_STBY
O
Audio AMP shutdown control
95
DU_LINK_ACK0
I
ACK from IEEE1394 chip
96
SIF_SW
O
I2C line SW control of sound multiplex decoder
97
DU_LINK_IRQ
I
IEEE1394 chip interrupt request
98
CNVSS
O
Monitor microprocessor write mode control
99
GND_B
—
Ground
100
N_PCI_RST
O
PCI reset
101
RS_BUF_CNT
O
Monitor microprocessor UART mode switching
102
PNL_I2C_EN
O
VCOM/I2C switch control
103
AUDIO_SEL2
O
DTV/HDMI analog audio switching control 2
104
PCHD_AUDIO_SEL
O
PC/HDMI external audio input switching
105
N_DVOUT_EN
O
DTV/AD YPbPr switching
106
MSP_RESET
O
MSP reset
107
HDMI_RESET
O
HDMI-TMDS_SW reset
108
GND_B
—
Ground
109
D3.3V
—
Power supply(+3.3V)
110
SVP_RESET
O
SVP_WX reset
111
N_PHY_RESET
O
i.Link PHY reset
112
N_LINK_RESET
O
i.Link LINK reset
113
FL_VPP0
O
Flash WP
114
GND_B
—
Ground
115
AREA_4
I
Destination setting (L: Europe/H: Asia)
116
DIG_AD
I
DTV add-on Unit presence/absence setting
117
HDMI_SEL1
O
HDMI_Select_1
118
HDMI_SEL2
O
HDMI_Select_2
119
HDMI_SEL3
O
HDMI_Select_3
120
HDMI_HPG1
I
HDMI_HotPlug_1
121
HDMI_HPG2
I
HDMI_HotPlug_2
122
CPLD_TDO
O
123
GND_B
—
Ground
124
HDMI_HPG3
I
HDMI_HotPlug_3 (for temporary insertion)
125
HDMI_SW_EMP
O
HDMI output waveform adjustment
Pin No.
Pin Name
I/O
Pin Function
LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
5 – 40
2.21. IC9601, 9603, 9604, 9606 (VHiTPS40055-1Y)
2.21.1 Block Diagram
126
HDMI_PLG_EN
O
HDMI output control
127
D3.3V
—
Power supply(+3.3V)
128
MUTE_HDMI
O
HDMI_MUTE initial value Low
129
HPLUGOUT_A
I
HDMI Plug Out detection
130
HDMIKEY_WP
O
EDIT_Write Protect
131
N_CPLD2_RST
O
CPLD2 reset
132
PNL_POW
O
Panel power control
133
HDMI_SW_INT
INT
HDMI SW IC interrupt request
134
HDELAY_DOUT
O
HDMI Data Delay Serial_Data_OUTPUT
135
N_MICOM_FLSW
O
Monitor microprocessor write control
136
N_MICOM_RST
O
Monitor microprocessor reset control
137
SMPOWHOLD
O
Power holding signal
138
PM_REQ
INT
Panel Maicon REQ
139
N_DBOOTS
I
Microprocessor write request
140
CBOOTS
I
SD card activation detection
141
D3.3V
—
Power supply(+3.3V)
142
N_DBG_RST
I
Debugger (Partner) reset
143
N_SRESET
I
System reset
144
GND_B
—
Ground
Pin No.
Pin Name
I/O
Pin Function
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