Sharp LC-42XL2E (serv.man5) Service Manual ▷ View online
LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
5 – 5
2. Detailed ICs Information
2.1. IC402 (VHiBD9305AF-1Y)
2.1.1 Pin Connections and short description
2.2. IC506 (VHiMM3151XQ-1Q)
2.2.1 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
1
RT
—
Timing resistor external terminal
2
CT
—
Timing capacitor external terminal
3
ENB
I
Control input terminal
4
GD
O
Gate drive output terminal
5
VCC
—
Power terminal
6
GND
—
Ground terminal
7
COMP
O
Error amplifier output terminal
8
FB
I
Error amplifier inversion input terminal
Pin No.
Pin Name
I/O
Pin Function
69
C1
I
Chroma signal input
75
C2
I
1
C3
I
7
C4
I
70
S1
I
The terminal which detects the connection state of S-connector.
76
S2
I
2
S3
I
65
V1
I
Composite signal input.
71
V2
I
77
V3
I
3
V4
I
9
V5
I
15
V6
I
68
S2-1
I
The terminal which detects the aspect ratio information of S-connector.
74
S2-2
I
80
S2-3/ FS3
I
The terminal which detects the aspect ratio information of S-connector, or which detects
the voltage of FS pin of a scart connector.
the voltage of FS pin of a scart connector.
67
Y1
I
Luminance signal input.
73
Y2
I
79
Y3
I
5
Y4
I
14
ADR
I
Slave address select pin.
16
BIAS
I
BIAS
32
L13
I
The terminal which detects the number of scanning lines information on D-connector.
20
L11/ FS1
I
The terminal which detects the number of scanning lines information on D-connector, or
which detects the voltage of FS pin of a scart connector.
which detects the voltage of FS pin of a scart connector.
26
L12/ FS2
I
21
CY1
I
Component Y-signal input.
27
CY2
I
33
CY3
I
22
L21
I
The terminal which detects the I/P information of D-connector.
28
L22
I
34
L23
I
24
L31
I
The terminal which detects the aspect ratio information of D-connector.
30
L32
I
36
L33
I
23
PB1
I
Colour difference PB-signal input.
29
PB2
I
35
PB3
I
25
PR1
I
Colour difference PR-signal input.
31
PR2
I
37
PR3
I
38
SW1
I
The terminal which detects the connection state of D-connector.
40
SW2
I
42
SW3
I
45
SDA
I/O
Data I/O of I2C bus
46
SCL
I
Clock input of I2C bus
LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
5 – 6
2.3. IC803 (VHiSii9181+-1Q)
2.3.1 Block Diagram
2.3.2 Pin Connections and short description
49
DCOUT
O
DC output for S-terminal.
51
VOUT3
O
Monitor output (composit signal)
50
COUT3/VOUT6
O
Monitor output (Chroma or composite signal)
52
YOUT3/ VOUT5
O
Monitor output (Luminance or composite signal)
54
PROUT2
O
Colour difference PR-signal output.
58
PROUT1
O
55
PBOUT2/ COUT2
O
Colour difference PB-signal or chroma signal output.
59
PBOUT1/ COUT1
O
56
CYOUT2/ YOUT2/ VOUT2
O
Colour difference signal, Luminance or composite signal output.
60
CYOUT1/ YOUT1/ VOUT1
O
64
O1
O
Output port.
66
O2
O
72
O3
O
78
O4
O
53, 57
VDD1
—
Power supply (+9V)
8, 47
VDD2
—
Power supply (+5V)
18, 44, 62
GND
—
Ground
4, 6, 10, 11, 12, 13,
17, 19, 39, 41, 43,
48, 61, 63
17, 19, 39, 41, 43,
48, 61, 63
NC
—
Unconnected pins.
Pin No.
Pin Name
I/O
Pin Function
System Switching
Pin No.
Pin Name
I/O
Pin Function
LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
5 – 7
37
DSDA
I/O
DDC I2C Data for respective port.
38
DSCL
I
DDC I2C Clock.
39
RPWR
I
5V Port detection input. Connect to 5V signal from HDMI input connector.
25
HPD
O
Hot Plug Detect Output. Connect to HOTPLUG of HDMI input connector.
51
HPDIN
I
Hot Plug Detect Input.
53
TSCL
O
Master DDC I2C Clock (Open Drain Output) to HDMI receiver.
I2C transactions required for HDCP operation are performed over this I2C bus.
I2C transactions required for HDCP operation are performed over this I2C bus.
52
TSDA
I/O
Master DDC Data (Open drain output.) to HDMI receiver.
I2C transactions required for HDCP operation are performed over this I2C bus.
I2C transactions required for HDCP operation are performed over this I2C bus.
Configuration
54
54
I2CADDR/TPWR
I/O
I2C Slave Address input/Transmit Power Sense output pin.
When RESET# is low, this pin is used as an input to latch the I2C sub-address.
The level on this pin is latched when the RESET# pin transitions from low to high.
When RESET# is high, this pin is used as the TPWR output, indicating that the Rx-port has 5V
present.
When RESET# is low, this pin is used as an input to latch the I2C sub-address.
The level on this pin is latched when the RESET# pin transitions from low to high.
When RESET# is high, this pin is used as the TPWR output, indicating that the Rx-port has 5V
present.
24
I2CSEL/INT#
I/O
I2C Selection input/ Interrupt output pin.
The SiI9181 has two modes of operation: Local I2C control and Standalone.
The mode is determined by the level of the I2CSEL/INT pin at the rising edge of RESET#.
A high indicates I2C mode, and a low indicates Standalone mode.
In Local I2C mode, all functions are controlled and observed with I2C registers using the pins
LSCL/EPSEL1 and LSDA/EPSEL0 as the local I2C bus.
In Standalone mode, the external pins LSCL/ EPSEL1 and LSDA/ EPSEL0 are use to determine
whether the SiI9181 is in Normal mode or Standby mode.
After reset, this pin becomes the Interrupt output.
This is an open-drain output and requires an external pull-up.
The SiI9181 has two modes of operation: Local I2C control and Standalone.
The mode is determined by the level of the I2CSEL/INT pin at the rising edge of RESET#.
A high indicates I2C mode, and a low indicates Standalone mode.
In Local I2C mode, all functions are controlled and observed with I2C registers using the pins
LSCL/EPSEL1 and LSDA/EPSEL0 as the local I2C bus.
In Standalone mode, the external pins LSCL/ EPSEL1 and LSDA/ EPSEL0 are use to determine
whether the SiI9181 is in Normal mode or Standby mode.
After reset, this pin becomes the Interrupt output.
This is an open-drain output and requires an external pull-up.
50
RSVDL
—
Reserved for use by Silicon Image and must be tied low.
Control Pins
11
11
RESET#
I
Reset Pin (Active LOW). Certain configuration inputs are latched when RESET# transitions from
low to high.
low to high.
13
LSCL/EPSEL1
I
Local I2C Clock / External Port Select 1. When I2CSEL is high, this becomes the Local I2C bus
clock pin, LSCL. When I2CSEL is low, this becomes the external port select pin, EPSEL1.
True open drain, so does not pull to ground if power not applied.
An external pull-up is required.
clock pin, LSCL. When I2CSEL is low, this becomes the external port select pin, EPSEL1.
True open drain, so does not pull to ground if power not applied.
An external pull-up is required.
12
LSDA/EPSEL0
I/O
Local I2C Data / External Port Select 0. When I2CSEL is high, this becomes the Local I2C bus
data pin, LSDA. When I2CSEL is low, this becomes the external port select pin, EPSEL0.
True open drain, so does not pull to ground if power not applied.
An external pull-up is required.
data pin, LSDA. When I2CSEL is low, this becomes the external port select pin, EPSEL0.
True open drain, so does not pull to ground if power not applied.
An external pull-up is required.
CEC Pins
41
41
CEC_A
I/O
HDMI compliant CEC I/O used to interface to CEC devices.
CEC electrically compliant signal. This pin connects to the CEC signal of all HDMI connectors in
the system.
As an input, the pad acts as a LVTTL Schmitt triggered input and is 5V tolerant. As an output, the
pad acts as an NMOS driver with resistive pull-up. This pin has an internal pull-up resistor.
CEC electrically compliant signal. This pin connects to the CEC signal of all HDMI connectors in
the system.
As an input, the pad acts as a LVTTL Schmitt triggered input and is 5V tolerant. As an output, the
pad acts as an NMOS driver with resistive pull-up. This pin has an internal pull-up resistor.
40
CEC_D
I/O
CEC interface to local system. True open-drain. An external pull-up is required. This pin typically
connects to the local CPU.
connects to the local CPU.
Differential Signal Data Pins
30
30
RX0+
I
TMDS input data pairs.
29
RX0-
I
33
RX1+
I
32
RX1-
I
35
RX2+
I
34
RX2-
I
28
RXC+
I
TMDS input clock pair.
27
RXC-
I
6
TX0+
O
TMDS output data pairs.
7
TX0-
O
3
TX1+
O
4
TX1-
O
1
TX2+
O
2
TX2-
O
8
TXC+
O
TMDS output clock pair.
9
TXC-
O
10
EXT_SWING
O
Voltage Swing Adjust. A resistor tied from this pin to AVCC18 determines the amplitude of the volt-
age swing. The recommended value is 750
age swing. The recommended value is 750
Ω.
Power and Ground Pins
Pin No.
Pin Name
I/O
Pin Function
LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
5 – 8
2.4. IC1301 (VHiYDA147SZ-1Y)
2.4.1 Block Diagram
2.4.2 Pin Connections and short description
14, 15, 16, 17,
18, 19, 20, 21,
43, 44, 45, 46,
47, 55, 56
18, 19, 20, 21,
43, 44, 45, 46,
47, 55, 56
AGND
—
Analog GND.
5, 26, 36
AVCC18
—
Analog VCC. Connect to 1.8V supply.
22, 48
DVCC18
—
Digital VCC. Connect to 1.8V supply.
23, 49
DGND
—
Digital GND.
31, 42
AVCC33
—
Analog VCC. Connect to 3.3V supply.
Pin No.
Pin Name
I/O
Pin Function
1, 2, 12, 25, 35, 36
NC
—
No connection
3
PVDDREG
—
Power terminal for regulator (PVDD)
4
AVDD
—
Output terminal for 3.3V regulator
5
INLP
I
Analog input terminal (Lch+)
6
INLM
I
Analog input terminal (Lch-)
7
VREF
VREF terminal
8
INRM
I
Analog input terminal (Rch-)
9
INRP
I
Analog input terminal (Rch+)
10
AVSS
—
GND terminal for analog
11
PLIMIT
I
Power limit setting terminal
13, 14
PVDDPR
—
Power terminal for digital amplifier output (Rch+)
Pin No.
Pin Name
I/O
Pin Function
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