Sharp LC-42XL2E (serv.man5) Service Manual ▷ View online
LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
5 – 17
2.10. IC3301 (RH-iXC010WJQZQ)
2.10.1 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
Ball Assignments for CPU Host Interface.
K20, K19, K18, K17, L20,
L19, L18, L17
K20, K19, K18, K17, L20,
L19, L18, L17
A_D[7:0]
I/O
Multiplexed address and data bus powered by VDDH/VSS.
M17, M18, M119, M20,
N20, N19, N18, N17
N20, N19, N18, N17
ADDR[7:0]
I
CPU Address. (Not connected)
J18
ALE
I
Address latch enables.
J19
WR#
I
CPU Write.
J20
RD#
I
CPU Read.
H17
SDA
I/O
I2C data.
H18
SCL
I
I2C clock.
J17
CPU_CS
I
UX chip select pin from MCU. Active Low.
Ball Assignments for Analog Support Interface.
W1
W1
XTALI
I
Input for Clock Synthesizer. Supports 24MHz Oscillator or crystal powered by ana-
log PLL.
log PLL.
Y1
XTALO
O
Used in conjunction with XTALI for 24MHz crystal output powered by analog PLL.
U2
MLF1
I
Low pass filter node for memory clock PLL powered by analog PLL.
R4
PLF2
I
Low pass filter node for video clock PLL powered by analog PLL.
Ball Assignments for Analog Input Interface.
Y4
Y4
CVBS1
I
Composite video input 1.
V6
Y_G1
I
Y input 1 of component or G input 1 of PC RGB.
W6
Y_G2
I
Y input 2 of component or G input 2 of PC RGB.
Y6
Y_G3
I
Y input 3 of component or G input 3 of PC RGB.
W2
CVBS_OUT1
I
CVBS Output 1. (Not connected)
V2
CVBS_OUT2
I
CVBS Output 2. (Not connected)
V9
C
I
C input of S-Video.
W9
PB_B1
I
PB input 1 of component.
Y9
PB_B2
I
PB input 2 of component.
Y10
PB_B3
I
PB input 3 of component.
Y8
PR_R1
I
PR input 1 of component.
W8
PR_R2
I
PR input 2 of component.
V8
PR_R3
I
PR input 3 of component.
W4, V4
FS2, FS1
I
SCART function select 2, 1.
U4, Y5
FB2, FB1
I
SCART FB input for Port 2, Port 1.
V10
AIN_H
I
Hsync input (PC RGB input)
U10
AIN_V
I
Vsync input (PC RGB input)
U8
PC_R
I
PC Red input.
Y7
PC_G
I
PC Green input.
W10
PC_B
I
PC Blue INPUT.
Ball Assignments for Capture Interface (TV & RGB).
U18, U19, U20, T20, T18,
T17, R19, R20
U18, U19, U20, T20, T18,
T17, R19, R20
DPB[15:8] (DP_B[15:8])
I/O
Digital input port [15:8] (Output reserved)
Y12, U13, V13, W13,
Y13, Y14, W14, V14,
U14, U15, V15, W15,
Y16, W16, V16, U16,
U17, V17, W17, Y17,
Y18, W18, V18, W19
Y13, Y14, W14, V14,
U14, U15, V15, W15,
Y16, W16, V16, U16,
U17, V17, W17, Y17,
Y18, W18, V18, W19
DPA[23:0] (DP_A[23:0])
I/O
Digital input/output port [23:0]
T19
DPB_CLK (CLK_B)
I/O
Digital port B CLK input/output. (Not connected)
Y15
DPA_CLK (CLK_A)
I/O
Digital port A CLK input/output.
W20
DPE_DE (DE_B)
I/O
DE input/output of Digital port B.
Y20
DPA_VS (VS_A)
I/O
Vsync input/output of Digital port A.
Y19
DPA_HS (HS_A)
I/O
Hsync input/output of Digital port A.
V20
DPB_VS (VS_B)
I/O
Vsync input/output of Digital port B. (Not connected)
V19
DPB_HS (HS_B)
I/O
Hsync input/output of Digital port B. (Not connected)
P19
HS
I/O
Hsync output for Digital port.
P17
VS
I/O
Vsync output for Digital port.
LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
5 – 18
Pin No.
Pin Name
I/O
Pin Function
Ball Assignments for Frame Buffer Memory.
D3, C3, C2, C1, A1, A2,
A3, C5, A4, B5, A5, D6,
A7, B7, C7, D7, D8, C8,
B8, A8, D9, D10, C10,
B10, A10, A11, B11, C11,
D12, A13, B13, C13
D3, C3, C2, C1, A1, A2,
A3, C5, A4, B5, A5, D6,
A7, B7, C7, D7, D8, C8,
B8, A8, D9, D10, C10,
B10, A10, A11, B11, C11,
D12, A13, B13, C13
MD[31:0]
I/O
Memory data.
F1, F2, F3, F4, G4, G3,
G2, G1, H1, H2, H3, H4
G2, G1, H1, H2, H3, H4
MA[11-0]
I/O
Memory Address.
J2
RAS#
O
RAS# signal powered by VDDH/VSS.
J1
CAS#
O
CAS# signal powered by VDDH/VSS.
K1
WE#
O
WE#, write enable signal powered by VDDH/VSS.
J3
CS1#
O
Chip select 0 for the first 2/4 Mbyte of SGRAM/SDRAM powered by VDDH/VSS.
J4
CS0#
O
Chip select 1 for the first 2/4 Mbyte of SGRAM/SDRAM powered by VDDH/VSS.
D1
MCK0
O
Memory clock+.
E1
MCK0#
O
Memory clock-.
B1, A6, A9, A12
DQM[3:0]
O
Read/Write bytes enable powered by VDDH/VSS.
K2
CLKE
O
Memory clock enable.
B2, B6, B9, B12
DQS[3:0]
I/O
Memory data strobe.
E3
MVREF
—
DDR voltage reference.
K3
BA0
O
Bank address select.
K4
BA1
O
Bank address select.
Ball Assignments for Power and Ground.
C14, C15, D13, D14,
D15, E13, E14, E15,
G16, H5, H16, J5, J16,
K5, K16, R16, T14, T15
C14, C15, D13, D14,
D15, E13, E14, E15,
G16, H5, H16, J5, J16,
K5, K16, R16, T14, T15
VDDC
—
1.2V Digital core power.
E4, E7
VSSR
—
Digital memory reference Ground.
E2, E8
VDDR
—
2.5V Digital power for Memory.
B4, C4, D4, D5, D11, E5,
E6, E9, E10, E11, E12,
F5, G5
E6, E9, E10, E11, E12,
F5, G5
VDDM
—
2.5V Memory interface power. Output driver.
L16, M16, N16, P16, T12,
T13, R17, R18
T13, R17, R18
VDDH
—
3.3V Digital I/O power.
B3, C6, C9, C12, D2, H8,
H9, H10, H11, H12, H13,
J8, J9, J10, J11, J12, J13,
K8, K9, K10, K11,K12,
K13, L5, L8, L9, L10, L11,
L12, L13, M8, M9, M10,
M11, M12, M13, N8, N9,
N10, N11, N12, N13,
P18, T16, H20
H9, H10, H11, H12, H13,
J8, J9, J10, J11, J12, J13,
K8, K9, K10, K11,K12,
K13, L5, L8, L9, L10, L11,
L12, L13, M8, M9, M10,
M11, M12, M13, N8, N9,
N10, N11, N12, N13,
P18, T16, H20
VSS
—
Core and Digital IO ground.
W3
AVSS_BG_ASS
—
ADC ground.
V3
AVDD3_BG_ASS
—
3.3V ADC power.
T3
PAVDD1
—
3.3V power for MCLK PLL.
T2
PAVSS1
—
Ground for MCLK PLL.
R3
PAVSS2
—
Ground for PCLK PLL.
T4
PAVDD2
—
3.3V power for PCLK PLL.
U6, T8, U7, U5
AVDD_ADC[4, 3, 2, 1]
—
1.2V power for analog ADC.
T6, T9, T7, T5
AVSS_ADC[4, 3, 2, 1]
—
Ground for analog ADC.
U9, Y3
AVDD3_ADC[2, 1]
—
3.3V ADC power.
U3
AVDD3_OUTBUF
—
3.3V power for output buffer.
Y2
AVSS_OUTBUF
—
3.3V ground for output buffer.
C18, C19
LVDS_VSSO
—
LVDS out buffer ground.
C16
LVDS_VSSD
—
LVDS Digital ground.
E16
LVDS_VSSA
—
LVDS analog ground.
E18
LVDS_VSSP
—
LVDS PLL GND.
D18
LVDS_VDDP
—
LVDS PLL VDD.
E17
LVDS_VDDA
—
LVDS analog VDD.
D16
LVDS_VDDD
—
LVDS Digital VDD.
C17, D17
LVDS_VDDO
—
LVDS out buffer VDD.
P20
NC
—
Not connected.
U1
AVDDAPLL
—
1.2V analog PLL power.
V1
AVSSAPLL
—
1.2V analog GND.
R2
AVDDLLPLL
—
1.2V Line Lock PLL power.
LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
5 – 19
T1
AVSSLLPLL
—
1.2V Line Lock PLL GND.
Miscellaneous Ball Assignments.
F18
F18
RESET
I
System reset forces the chip to a known state. Active High.
G18
INTN
I/O
Interrupt signal (active low).
G17
PWM0
I/O
PWM I/O. (Not connected)
F16
V5SF
I
5V reference voltage (must be connected to 5V even in standby mode, when CPU
I/O is 5V)
I/O is 5V)
F17
TESTMODE
I
Reserved (Connected to ground).
LVDS Output Ball Assignments.
A14
A14
TA1P
O
LVDS 1st Channel Differential positive data out.
B14
TA1M
O
LVDS 1st Channel Differential negative data out.
A15
TB1P
O
LVDS 1st Channel Differential positive data out.
B15
TB1M
O
LVDS 1st Channel Differential negative data out.
A16
TC1P
O
LVDS 1st Channel Differential positive data out.
B16
TC1M
O
LVDS 1st Channel Differential negative data out.
A18
TD1P
O
LVDS 1st Channel Differential positive data out.
B18
TD1M
O
LVDS 1st Channel Differential negative data out.
A19
TE1P
O
LVDS 1st Channel Differential positive data out.
B19
TE1M
O
LVDS 1st Channel Differential negative data out.
B17
TCLK1M
O
LVDS 1st Channel Differential positive CLK out.
A17
TCLK1P
O
LVDS 1st Channel Differential negative CLK out.
F19
TCLK2M
O
LVDS 2st Channel Differential positive CLK out.
E20
TCLK2P
O
LVDS 2st Channel Differential negative CLK out.
H19
TE2P
O
LVDS 2st Channel Differential positive data out.
G20
TE2M
O
LVDS 2st Channel Differential negative data out.
G19
TD2P
O
LVDS 2st Channel Differential positive data out.
F20
TD2M
O
LVDS 2st Channel Differential negative data out.
E19
TC2P
O
LVDS 2st Channel Differential positive data out.
D20
TC2M
O
LVDS 2st Channel Differential negative data out.
B20
TB2P
O
LVDS 2st Channel Differential positive data out.
A20
TB2M
O
LVDS 2st Channel Differential negative data out.
D19
TA2P
O
LVDS 2st Channel Differential positive data out.
C20
TA2M
O
LVDS 2st Channel Differential negative data out.
HDMI Interface Ball Assignments.
L4
L4
PVCC
—
TMDS PLL supply voltage.
M5
ANTSTO
O
Test pin. (Not connected)
M4, N4, N5, P4
AVCC
—
TMDS analog supply voltage.
L2
RXC-
I
TMDS differential CLK-.
L1
RXC+
I
TMDS differential CLK+.
L3, M3, N3, P3, R1
TMDS_GND
—
TMDS GND.
M2
RX0-
I
HDMI Differential input pair 0-
M1
RX0+
I
HDMI Differential input pair 0+
N2
RX1-
I
HDMI Differential input pair 1-
N1
RX1+
I
HDMI Differential input pair 1+
P2
RX2-
I
HDMI Differential input pair 2-
P1
RX2+
I
HDMI Differential input pair 2+
R5
REGVCC
—
ACR PLL Regulator supply voltage.
P5
DGND
—
ACR PLL GND.
T10
PWR5V
I
TMDS port Transmitter Detect (5V tolerant).
T11
DSCL
I/O
DDC I2C clock for DDC (5V tolerant).
U11
DSDA
I/O
DDC I2C data for DDC (5V tolerant).
U12
WS
O
I2S Word select output.
V11
SCDT
O
Indicates Active video at HDMI input port.
V12
SD0
O
I2S serial data output.
W11
AUDIOCLK
I
Audio master clock input reference.
W12
SPDIF
O
S/PDIF audio output.
Y11
SCK
O
I2S serial clock output.
Pin Assignments for Reference Voltage.
V5
V5
VREFN1
—
ADC1 voltage reference-.
W5
VREFP1
—
ADC1 voltage reference+.
V7
VREFN2
—
ADC2 voltage reference-.
W7
VREFP2
—
ADC2 voltage reference+.
Pin No.
Pin Name
I/O
Pin Function
LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
5 – 20
2.11. IC3501-2 (RH-iXC163WJQZQ)
2.11.1 Block Diagram
2.11.2 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
62, 63
CK, CK
I
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except DQ’s and DM’s that are
sampled on both edges of the DQS.
All of the inputs are sampled on the rising edge of the clock except DQ’s and DM’s that are
sampled on both edges of the DQS.
22
CKE
I
Activates the CK signal when high and deactivates the CK signal when low. By deactivating
the clock, CKE low indicates the Power down mode or Self refresh mode.
the clock, CKE low indicates the Power down mode or Self refresh mode.
12
CS
I
CS enables the command decoder when low and disabled the command decoder when high.
When the command decoder is disabled, new commands are ignored but previous operations
continue.
When the command decoder is disabled, new commands are ignored but previous operations
continue.
11
RAS
I
Latches row addresses on the positive going edge of the CK with RAS low.
Enables row access & precharge.
Enables row access & precharge.
10
CAS
I
Latches column addresses on the positive going edge of the CK with CAS low.
Enables column access.
Enables column access.
53
WE
I
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Latches data in starting from CAS, WE active.
1, 28, 7, 34
DQS0-3
I/O
Data input and output are synchronized with both edge of DQS.
44, 67, 50, 35
DM0-3
I
Data In mask. Data In is masked by DM Latency=0 when DM is high in burst write. DM0 for
DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31.
DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31.
40, 78, 41, 42, 2, 46, 3, 4,
26, 65, 27, 66, 29, 68, 30,
69, 48, 5, 49, 6, 51, 8, 9,
52, 31, 32, 71, 33, 37, 38,
75, 39
26, 65, 27, 66, 29, 68, 30,
69, 48, 5, 49, 6, 51, 8, 9,
52, 31, 32, 71, 33, 37, 38,
75, 39
DQ0-31
I/O
Data inputs/Outputs are multiplexed on the same pins.
14, 56
BA0, BA1
I
Selects which bank is to be active.
15, 16, 57, 17, 18, 60, 19,
20, 21, 59, 90, 58
20, 21, 59, 90, 58
A0-11
I
Row/Column addresses are multiplexed on the same pins.
Row addresses: RA0 ~ RA11, Column addresses: CA0 ~ CA7.
Column address CA8 is used for auto precharge.
Row addresses: RA0 ~ RA11, Column addresses: CA0 ~ CA7.
Column address CA8 is used for auto precharge.
82, 88, 91, 92, 95, 101,
105, 106
105, 106
VDD
—
Power for the input buffers and core logic.
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