DOWNLOAD Sharp LC-42XL2E (serv.man5) Service Manual ↓ Size: 2.32 MB | Pages: 42 in PDF or view online for FREE

Model
LC-42XL2E (serv.man5)
Pages
42
Size
2.32 MB
Type
PDF
Document
Service Manual
Brand
Device
TV / LCD / Major IC Informations
File
lc-42xl2e-sm5.pdf
Date
PREV: Sharp LC-42XL2E (serv.man4) Service Manual

Sharp LC-42XL2E (serv.man5) Service Manual ▷ View online

LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
5 – 25
AP7
TD1P
O
LVDS Positive Output. (Not used)
AN7
TD1M
O
LVDS Negative Output. (Not used)
AP8
TCLK1P
O
LVDS Positive clock Output. (Not used)
AN8
TCLK1M
O
LVDS Negative clock Output. (Not used)
AP9
TC1P
O
LVDS Positive Output. (Not used)
AN9
TC1M
O
LVDS Negative Output. (Not used)
AJ4
LVDS_VDDO
—
LVDS Output buffer VDD (+3.3V).
AP10
TB1P
O
LVDS Positive Output. (Not used)
AN10
TB1M
O
LVDS Negative Output. (Not used)
AP11
TA1P
O
LVDS Positive Output. (Not used)
AN11
TA1M
O
LVDS Negative Output. (Not used)
AL5
LVDS_VSSO
—
LVDS Output buffer VSS.
AM5
LVDS_VDDO
—
LVDS Output buffer VDD (+3.3V).
AL3
LVDS_VSSA
—
LVDS Analog VSS.
AL4
LVDS_VDDA
—
LVDS Analog VDD (+3.3V).
AK3
LVDS_VSSD
—
LVDS Digital VSS.
AM3
LVDS_VDDD
—
LVDS Digital VDD (+3.3V).
PLL Interface
B7
DVSS22
—
PLL ground related to DVDD22; supply for VCO circuit.
A7
DVDD22
—
PLL power= 1.2V; supply for VCO circuit.
A6
DVSS21
—
PLL ground related to DVDD21; supply for digital circuit.
B6
DVDD21
—
PLL power= 1.2V; supply for digital circuit.
C6
AVSS7
—
PLL ground related to AVDD7.
D6
MCLK2LF
—
Low pass filter for MCLK2PLL.
E6
AVDD7
—
PLL analog power= 3.3V; supply for MCLK2PLL.
D5
AVSS6
—
PLL ground related to AVSS6.
C5
MPEGCLK2LF
—
Low pass filter for MPEGCLK2PLL.
B5
AVDD6
—
PLL analog power= 3.3V; supply for MPEGCLK2PLL.
A5
AVSS5
—
PLL ground related to AVSS5.
A4
MPEGCLK1LF
—
Low pass filter for MPEGCLK1PLL.
B4
AVDD5
—
PLL analog power= 3.3V; supply for MPEGCLK1PLL.
C4
AVSS2
—
PLL ground related to AVSS2.
D4
PLF
—
Low pass filter for PCLKPLL.
C3
AVDD2
—
PLL analog power= 3.3V; supply for PCLKPLL.
B3
AVSS1
—
PLL ground related to AVSS1.
A3
MLF
—
Low pass filter for MCLKPLL.
A2
AVDD1
—
PLL analog power= 3.3V; supply for MCLKPLL.
B2
AVSS4
—
PLL ground related to AVSS4.
A1
IDELF
—
Low pass filter for IDECLKPLL.
B1
AVDD4
—
PLL analog power= 3.3V; supply for IDECLKPLL.
C1
AVDD3
—
PLL analog power= 3.3V; supply for CK48MPLL.
C2
CK48MLF
—
Low pass filter for CK48MPLL.
D3
AVSS3
—
PLL ground related to AVSS3.
D2
XTLI
—
24MHz_PLL crystal input.
D1
XTLO
—
24MHz_PLL crystal output.
E1
DVSS12
—
PLL ground related to DVDD12; supply for VCO circuit.
E2
DVDD12
—
PLL power= 1.2V; supply for VCO circuit.
E3
DVSS11
—
PLL ground related to DVDD11; supply for digital circuit.
E4
DVDD11
—
PLL power= 1.2V; supply for digital circuit.
FLASH Interface
E25
AD30_FRA14
I/O
Flash address 14/PCI AD bus bit 30.
D24
AD28_FRA12
I/O
Flash address 12/PCI AD bus bit 28.
E24
AD26_FRA10
I/O
Flash address 10/PCI AD bus bit 26.
A23
AD29_FRA13
I/O
Flash address 13/PCI AD bus bit 29.
B23
AD31_FRA15
I/O
Flash address 15/PCI AD bus bit 31.
D23
AD24_FRA8
I/O
Flash address 8/PCI AD bus bit 24.
E23
AD22_FRA6
I/O
Flash address 6/PCI AD bus bit 22.
A22
CBE3#_FRA19
I/O
Flash address 19/PCI CBE#[3].
B22
AD25_FRA9
I/O
Flash address 9/PCI AD bus bit 25.
C22
AD27_FRA11
I/O
Flash address 11/PCI AD bus bit 27.
D22
AD20_FRA4
O
Flash address 4/PCI AD bus bit 20/POD host interface Card access register selec-
tion.
E22
AD18_FRA2
O
Flash address 2/PCI AD bus bit 18/POD host interface Card I/O output enable.
A21
AD19_FRA3
O
Flash address 3/PCI AD bus bit 19/POD host interface Card I/O Write enable.
B21
AD21_FRA5
O
Flash address 5/PCI AD bus bit 21.
Ref No.
Pin Name
I/O
Pin Function
LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
5 – 26
C21
AD23_FRA7
O
Flash address 7/PCI AD bus bit 23.
D21
AD16_FRA0
O
Flash address 0/PCI AD bus bit 16/POD host interface Card I/O output enable.
A20
IRDY_PCAS
I/O
PCI bus IRDY# signal/M68K CPU interface address strobe signal.
B20
CBE2#_FRA18
O
Flash address 18/PCI CBE#[2].
C20
AD17_FRA1
O
Flash address 1/PCI AD bus bit 17/POD host interface Card I/O Write enable.
A19
CBE1#_FRA17
O
Flash address 17/PCI CBE#[1].
E19
AD15_FRD15
I/O
Flash Data bus bit 15/PCI AD bus bit 15.
A18
AD7_FRD7
I/O
Flash Data bus 7/PCI AD bus bit 7.
B18
AD10_FRD10
I/O
Flash Data bus bit 10/PCI AD bus bit 10/POD host interface address bit 2.
C18
AD12_FRD12
I/O
Flash Data bus bit 12/PCI AD bus bit 12/POD host interface address bit 10.
D18
AD13_FRD13
I/O
Flash Data bus bit 13/PCI AD bus bit 13/POD host interface address bit 13.
E18
AD11_FRD11
I/O
Flash Data bus bit 11/PCI AD bus bit 11/POD host interface address bit 3.
A17
AD8_FRD8
I/O
Flash Data bus bit 8/PCI AD bus bit 8/POD host interface address bit 0.
B17
AD14_FRD14
I/O
Flash Data bus bit 14/PCI AD bus bit 14/POD host interface address bit 12.
C17
AD9_FRD9
I/O
Flash Data bus bit 9/PCI AD bus bit 9/POD host interface address bit 1.
D17
AD6_FRD6
I/O
Flash Data bus bit 6/PCI AD bus bit 6/POD host interface Data bus bit 6.
E17
CBE0#_FRA16
O
Flash address 16/PCI CBE#[0].
A16
AD5_FRD5
O
Flash Data bus bit 5/PCI AD bus bit 5/POD host interface Data bus bit 5.
B16
AD1_FRD1
I/O
Flash Data bus bit 1/PCI AD bus bit 1/POD host interface Data bus bit 1.
C16
AD3_FRD3
I/O
Flash Data bus bit 3/PCI AD bus bit 3/POD host interface Data bus bit 3.
D16
AD2_FRD2
I/O
Flash Data bus bit 2/PCI AD bus bit 2/POD host interface Data bus bit 2.
E16
AD4_FRD4
I/O
Flash Data bus bit 4/PCI AD bus bit 4/POD host interface Data bus bit 4.
E15
AD0_FRD0
I/O
Flash Data bus bit 0/PCI AD bus bit 0/POD host interface Data bus bit 0.
D15
FRA25
I/O
Flash address bit 25.
C15
FRA24
I/O
Flash address bit 24.
B15
FRA23
I/O
Flash address bit 23.
A15
FRA22
I/O
Flash address bit 22.
A14
FRA21
I/O
Flash address bit 21.
B14
FRA20
I/O
Flash address bit 20.
C14
GCS3
I/O
Flash chip select (0:Active).
D14
GCS2
I/O
Flash chip select (0:Active).
E14
GCS1
I/O
Flash chip select (0:Active).
E13
GCS0
I/O
Flash chip select (0:Active).
D13
BOOTCS
O
EPPROM chip select (0:Active).
C13
FWE#
O
Write enable signal of Flash Rom.
B13
FOE#
O
Read enable signal of Flash Rom.
A13
NAND_CE#
O
Chip select signal of NAND Flash Rom.
A12
NAND_RDY
I
Ready signal of NAND Flash Rom.
PCI Interface
A27
INTA
I
PCI interrupt A.
C25
INTB
I
PCI interrupt B.
B27
INTC
I
PCI interrupt C.
B25
INTD
I
PCI interrupt D.
D27
GNT0
O
PCI gnt signal. (Not used)
D26
GNT1
O
PCI gnt signal. (Not used)
E26
GNT2
O
PCI gnt signal. (Not used)
D25
GNT3
O
PCI gnt signal. (Not used)
C27
PCIRST#
O
PCIRSTN/68K clock output.
A25
PCICLK
O
PCI clock.
C24
REQ0
I
PCI req signal.
B24
REQ1
I
PCI req signal.
A24
REQ2
I
PCI req signal.
C23
REQ3
I
PCI req signal.
E21
FRAME#_SIZI
I/O
PCI bus FRAME# signal/68K Transfer size bit 1. (analog with Transfer size bit 0 to 
indicate the number byte to be transferred during a bus cycle M68K CPU bus.)
A20
IRDY_PCAS
I/O
PCI bus IRDY# signal/68K address strobe signal.
B20
CBE2#_FRA18
I/O
PCI bus CBE#[2]/Flash address bit 18.
D20
TRDY#_SIZ0
I/O
PCI bus TRDY# signal/68K Transfer size bit 0.
B19
SEPR#_DSACK1
I/O
PCI bus SERR# signal/68K Data and Size acknowledge signal bit 1.
C19
DVSEL_PCDS
I/O
PCI bus DEVSEL# signal/68K Data Strobe signal.
D19
PAR_DSACK0
I/O
PCI bus PAR signal/68K Data and Size acknowledge signal bit 0.
E20
STOP#_PCRW
I/O
Flash, 3.3V CMOS IF, 16mA output pad.
POD Interface
B12
POD_ITX
I
POD OOB TXI Channel.
C12
POD_WAIT
I
POD WAIT# signal to expand bus cycle.
Ref No.
Pin Name
I/O
Pin Function
LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
5 – 27
D12
POD_CE1
O
Card enable.
E12
POD_CTX
O
POD OOB TX Gapped Symbol clock.
A11
POD_DRX
O
POD OOB RX data.
B11
POD_CD1
I
Card Detect.
C11
POD_IREQ
I
Ready/IRQ
D11
POD_CRX
O
POD OOB RX Gapped clock.
E11
POD_RESET
O
POD Card reset signal.
A10
POD_QTX
I
POD OOB TX Q Channel.
B10
POD_VS1
I
Card voltage Sense.
C10
POD_ETX
I
POD OOB TX enable.
D10
POD_CD2
I
Card Detect.
E10
POD_CE2
O
Card enable.
A9
POD_VPP_EN
O
Slot VPP enable.
B9
POD_OVERLOAD
I
Current overload detect.
C9
POD_VPP_EN#
O
Slot VPP enable.
D9
POD_VCC_EN#
O
Slot VCC enable.
E9
POD_VCC_EN
O
Slot VCC enable.
A8
POD_A9
O
POD Host interface address bit 9.
B8
POD_A8
O
POD Host interface address bit 8.
C8
POD_A7
I/O
POD Host interface address bit 7.
D8
POD_A6
I/O
POD Host interface address bit 6.
D7
POD_A5
I/O
POD Host interface address bit 5.
C7
POD_A4
O
POD Host interface address bit 4.
VDA Interface
AP13, AN13, AM13, AL13, 
AK13, AP14, AN14, AM14, 
AL14, AK14
VDA_R[9:0]
I
Video input, R channel. (Not used)
AP15, AN15, AM15, AL15, 
AK15, AM16, AL16, AK16, 
AP17, AN17
VDA_B[9:0]
I
Video input, B channel. (Not used)
AM17, AL17, AK17, AP18, 
AN18, AM18, AL18, AK18, 
AP19, AN19
VDA_G[9:0]
I
Video input, G channel. (Not used)
AP16
VDA_CLK
I
Video input, Clock. (Not used)
AM19
VDA_VS
I
Video input, Vertical sync. (Not used)
AL19
VDA_HS
I
Video input, Horizontal sync. (Not used)
AK19
VDA_DE
I
Video input, Data enable. (Not used)
VDB Interface, EJTAG, IDE and POD2 share with VDB
AK20
VDB_DE
I/O
Video input/output; data enable;
IDE: IDE bus interrupt.
EJTAG: NOP
POD2: POD_CE2B#, the second POD Card enable.
AL20
VDB_HS
I/O
Video input/output; Horizontal sync;
IDE: PDLAGCBLID, Passed diagnostics, cable assembly type identifier.
EJTAG: TDI2, TDI EJTAG input of slave CPU.
POD2: POD_A_B5, the second POD host interface address bit 5.
AM20
VDB_VS
I/O
Video input/output; Vertical sync;
IDE: DMAREQ, IDE bus DMA request.
EJTAG: NOP
POD2: POD_A_B4, the second POD host interface address bit 4.
AN20
VDB_G0
I/O
Video input/output; Green channel bit 0;
IDE: IDE data bus bit 0.
EJTAG: TDO2, TDO EJTAG input of slave CPU CPU.
POD2: POD_A_B6, the second POD host interface address bit 6.
AP20
VDB_G1
I/O
Video input/output; Green channel bit 1;
IDE: IDE data bus bit 1.
EJTAG: TMS2, TMS EJTAG input of slave CPU CPU.
POD2: POD_A_B7, the second POD host interface address bit 7.
AK21
VDB_G2
I/O
Video input/output; Green channel bit 2;
IDE: IDE data bus bit 2.
EJTAG: TCK2, TCK EJTAG input of slave CPU CPU.
POD2: POD_A_B8, the second POD host interface address bit 8.
AL21
VDB_G3
I/O
Video input/output; Green channel bit 3;
IDE: IDE data bus bit 3.
EJTAG: DCLK EJTAG output of both CPU CPUs.
POD2: POD_A_B8, the second POD host interface address bit 9.
Ref No.
Pin Name
I/O
Pin Function
LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
5 – 28
AM21
VDB_G4
I/O
Video input/output; Green channel bit 4;
IDE: IDE data bus bit 4.
EJTAG: TPC[0], output as EJTAG PC Trace bus, bit 0.
POD2: POD_CD2B#, the second POD interface card detect.
AN21
VDB_G5
I/O
Video input/output; Green channel bit 5;
IDE: IDE data bus bit 5.
EJTAG: TPC[1], output as EJTAG PC Trace bus, bit 1.
POD2: POD_CD1B#, the second POD interface card detect.
AP21
VDB_G6
I/O
Video input/output; Green channel bit 6;
IDE: IDE data bus bit 6.
EJTAG: TPC[2], output as EJTAG PC Trace bus, bit 2.
POD2: POD_RSTB, the second POD host interface reset.
AK22
VDB_G7
I/O
Video input/output; Green channel bit 7;
IDE: IDE data bus bit 7.
EJTAG: TPC[3], output as EJTAG PC Trace bus, bit 3.
POD3: POD_A_B14, the second POD host interface address bit 14.
AL22
VDB_G8
I/O
Video input/output; Green channel bit 8;
IDE: IDE data bus bit 8.
EJTAG: TPC[4], output as EJTAG PC Trace bus, bit 4.
POD3: POD2_TS2_D0, the second POD_TS2 data[0].
AM22
VDB_G9
I/O
Video input/output; Green channel bit 9;
IDE: IDE data bus bit 9.
EJTAG: TPC[5], output as EJTAG PC Trace bus, bit 5.
POD3: POD2_TS2_D2, the second POD_TS2 data[1].
AN22
VDB_B0
I/O
Video input/output; Blue channel bit 0;
IDE: IDE data bus bit 10.
EJTAG: TPC[6], output as EJTAG PC Trace bus, bit 6.
POD3: POD2_TS2_D2, the second POD_TS2 data[2].
AP22
VDB_B1
I/O
Video input/output; Blue channel bit 1;
IDE: IDE data bus bit 11.
EJTAG: TPC[7], output as EJTAG PC Trace bus, bit 7.
POD3: POD2_TS2_D3, the second POD_TS2 data[3].
AK23
VDB_B2
I/O
Video input/output; Blue channel bit 2;
IDE: IDE data bus bit 12.
EJTAG: PCST[0], output as EJTAG PC Trace bus, bit 0.
POD3: POD2_TS2_D4, the second POD_TS2 data[4].
AL23
VDB_B3
I/O
Video input/output; Blue channel bit 3;
IDE: IDE data bus bit 13.
EJTAG: PCST[1], output as EJTAG PC Trace bus, bit 1.
POD3: POD2_TS2_D5, the second POD_TS2 data[5].
AM23
VDB_B4
I/O
Video input/output; Blue channel bit 4;
IDE: IDE data bus bit 14.
EJTAG: PCST[2], output as EJTAG PC Trace bus, bit 2.
POD3: POD2_TS2_D6, the second POD_TS2 data[6].
AP23
VDB_CLK
I/O
Video input/output; Clock;
IDE: IDE data bus IO access complete.
EJTAG: NOP
POD3: POD_CE1B#, the second POD interface card enable.
AK24
VDB_B5
I/O
Video input/output; Blue channel bit 5;
IDE: IDE data bus bit 15.
EJTAG: PCST[3], output as EJTAG PC Trace bus, bit 3.
POD3: POD2_TS2_D7, the second POD_TS2 data[7].
AL24
VDB_B6
I/O
Video input/output; Blue channel bit 6;
IDE: Chip Select 0 for IDE interface.
EJTAG: PCST[4], output as EJTAG PC Trace bus, bit 4.
POD3: POD2_TS2_DEN, the second POD_TS2 data valid.
AM24
VDB_B7
I/O
Video input/output; Blue channel bit 7;
IDE: Chip Select 1 for IDE interface.
EJTAG: PCST[5], output as EJTAG PC Trace bus, bit 5.
POD2: POD2_TS2_CLK, the second POD_TS2 clock.
AN24
VDB_B8
I/O
Video input/output; Blue channel bit 8;
IDE: IDE address bus bit 0.
EJTAG: PCST[6], output as EJTAG PC Trace bus, bit 6.
POD2: POD2_TS2_SYNC, the second POD_TS2 SYNC.
AP24
VDB_B9
I/O
Video input/output; Blue channel bit 9;
IDE: IDE address bus bit 1.
EJTAG: PCST[7], output as EJTAG PC Trace bus, bit 7.
POD2: POD2_TS1_D0, the second POD_TS1 data[0].
Ref No.
Pin Name
I/O
Pin Function
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