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LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU

5 – 21

89, 94, 109, 115, 116, 
117, 118, 124, 126, 127, 
129, 130, 131, 132, 133, 
134, 135, 136, 137, 138, 
139, 140, 141, 142, 143, 
144

VSS

—

Ground for the input buffers and core logic.

45, 47, 70, 72, 74, 76, 77, 
79, 83, 84, 86, 87, 96, 97, 
99, 100

VDDQ

—

Isolated power supply for the output buffers to provide improved noise immunity.

36, 43, 81, 102, 103, 104, 
107, 108, 110, 111, 112, 
113, 114, 119, 120, 121, 
122, 123, 125, 128

VSSQ

—

Isolated ground for the output buffers to provide improved noise immunity.

23

VREF

—

Reference voltage for inputs, used for SSTL interface.

93, 61

RFU1/RFU2

—

Reserved for Future Use.

13, 24, 25, 54, 55, 64, 73, 
80, 85, 98

NC

—

No Connection.

LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU

5 – 22

MPEG pins
47

MOSTRT

O

MPEG packet start

48

MOVAL

O

MPEG data valid

49-53, 56-58

MDO[0:4]/ MDO[5:7]

O

MPEG data bus

61

MOCLK

O

MPEG clock out

62

BKERR

O

Block  error

63

MICLK

I

MPEG clock in

11

STATUS

O

Status output

6

IRQ

O

Interrupt output

Control pins
4

CLK1

I

Serial clock

5

DATA1

I/O

Serial data

23

XTI

I

Low phase noise oscillator

24

XTO

O

10

SLEEP

I

Device power down

12, 15-18

SADD[4:0]

I

Serial address set

44

SMTEST

I

Production test (only set low)

35

CLK2/GPP0

I/O

Serial clock tuner

36

DATA2/GPP1

I/O

Serial data tuner

42

AGC1

O

Primary AGC

41

AGC2/GPP2

I/O

Secondary AGC

43

GPP3

I/O

General purpose I/O

9

RESET

I

Device  reset

27

OSCMODE

I

Crystal oscillator mode

26

PLLTEST

O

PLL analog test

Analog inputs
30

VIN

I

positive input

31

VIN

I

negative input

34

RFLEV

I

RF level

Supply pins
21

PLLVdd

—

PLL supply

22

PLLGND

—

GND

7, 19, 37, 39, 59, 64

CVdd

—

Core logic power

2, 13, 45, 54

Vdd

—

I/O ring power

1, 3, 8, 14, 20, 25, 38, 
40, 46, 55, 60

Vss

—

Core and I/O ground

28

Avdd

—

ADC analog supply

29, 32

AGnd

—

GND

33

Vdd

—

2nd ADC supply

1

Css

I

Soft start timing capacitor.

2

Rfstart

—

Soft start frequency setting-low impedance voltage source-see also Cf.

3

Cf

—

Oscillator frequency setting-see also Rfmin, Rfstart.

4

Rfmin

I

Minimum oscillation frequency setting-low impedance voltage source-see also Cf.

5

OPOUT

O

Sense OP Amp output-low impedance.

6

OPIN-

I

Sense OP Amp inverting input-high impedance.

7

OPIN+

I

Sense OP Amp non inverting input-high impedance.

8

EN1

I

Half bridge latched enable.

9

EN2

I

Half bridge unlatched enable.

10

GND

—

Ground.

11

LVG

O

Low side driver output.

12

Vss

—

Supply voltage with internal zener clamp.

13

N.C.

—

Not connected.

14

OUT

O

High side driver reference.

15

HVG

O

High side driver output.

16

VBOOT

I

Bootstrapped supply voltage.

LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU

5 – 23

1

INV

I

Inverting input of the error amplifier. The information on the output voltage of the PFC preregulator is fed 
into the pin through a resistor divider.

2

COMP

O

Output of the error amplifier. A compensation network is placed between this pin and INV (pin #1) to 
achieve stability of the voltage control loop and ensure high power factor and low THD.

3

MULT

I

Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor divider and 
provides the sinusoidal reference to the current loop.

4

CS

I

Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor, the result-
ing voltage is applied to this pin and compared with an internal sinusoidal-shaped reference, generated by 
the multiplier, to determine MOSFET’s turn-off.

5

ZCD

I

Boost inductor’s demagnetization sensing input for transition-mode operation. A negative-going edge trig-
gers MOSFET’s turn-on.

6

GND

—

Ground. Current return for both the signal part of the IC and the gate driver.

7

GD

O

Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s with a peak 
current of 600 mA source and 800 mA sink. The high-level voltage of this pin is clamped at about 12V to 
avoid excessive gate voltages in case the pin is supplied with a high Vcc.

8

VCC

—

Supply Voltage of both the signal part of the IC and the gate driver. The supply voltage upper limit is 
extended to 22V min. to provide more headroom for supply voltage changes.

5

DRAIN (D) Pin:

Power MOSFET drain connection. Provides internal operating current for both start-up 
and steady-state operation.

1

BYPASS (BP) Pin:

Connection point for a 0.1 

µF external bypass capacitor for the internally generated 5.8 

V supply.

4

ENABLE/UNDER-VOLTAGE (EN/UV) 
Pin:

This pin has dual functions: enable input and line under-voltage sense. During normal 
operation, switching of the power MOSFET is controlled by this pin. MOSFET switch-
ing is terminated when a current greater than 240 

µA is drawn from this pin. This pin 

also senses line under-voltage conditions through an external resistor connected to the 
DC line voltage. If there is no external resistor connected to this pin, TinySwitch-II 
detects its absence and disables the line undervoltage function.

2,3

SOURCE (S) Pin:

Control circuit common, internally connected to output MOSFET source.

LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU

5 – 24

DAC Interface
AD2

VDDZ_DAC

—

Digital power for DAC (+3.3V).

AD3

VSSZ_DAC

—

Digital ground for DAC.

AD1

DAC_VS

I/O

DAC vsync.

AE1

DAC_HS

I/O

DAC hsync.

AE2

DAC_CLK

I/O

DAC clock

AE4

DAC_DE

I/O

DAC DE

AE3

DAC_FLD

I/O

DAC field.

AA5

AVSS51

—

Analog ground for DAC (for bias circuit).

AB5

COMP

—

Bias for DAC coupling capacitor.

AB4

IRSET

I

Bias for DAC current source.

AB3

CVBS_B

I

DAC blue or PB (Not used).

AB2

ADVSS2

—

Analog ground for DAC (for DAC’s AVSS52).

AB1

ADVDD2

—

Analog power for DAC (+3.3V).

AC1

C_G

I

DAC green or Y (Not used).

AC2

AVSS50

—

Digital ground for DAC.

AC3

AVDD50

—

Analog power for DAC (+3.3V).

AC4

Y_R

I

DAC red or PR (Not used).

AC5

ADVSS2

—

Analog ground for DAC (for DAC’s AVSS52).

AD5

ADVDD2

—

Analog power for DAC (+3.3V).

AD4

VM

I

DAC VM

ADC Interface
N2

AVDD

—

ADC power +3.3V.

N3

VIN1

I

VRADC INPUT1 (Not used)

N4

VIN2

I

VRADC INPUT2 (Not used)

N5

AVSS

—

ADC ground.

USB Interface
R3

USB_PPON_PP

O

USB Power on control.

R2

USB_OC_PP

I

USB over current control.

P5

VDDA

—

Analog core +3.3V supply.

P4

DN

O

Negative output channel.

P3

DP

O

Positive output control.

P2

VSSA

—

Analog core ground.

P1

RREFEXT

—

External resistor connection for current reference.

R5

VSSP

—

PLL ground pin Double Bond.

R4

VDDP

—

PLL +1.2V supply Double Bond.

LVDS Interface
AJ5

LVDS_VSSP

—

LVDS PLL Ground.

AJ3

LVDS_VDDP

—

LVDS PLL Power supply (+3.3V).

AK5

LVDS_VSSO

—

LVDS Output buffer VSS (Long pad)

AK4

LVDS_VDDO

—

LVDS Output buffer VDD (+3.3V).

AK1

TF2P

O

LVDS Positive Output. (Not used)

AK2

TF2M

O

LVDS Negative Output. (Not used)

AL1

TE2P

O

LVDS Positive Output. (Not used)

AL2

TE2M

O

LVDS Negative Output. (Not used)

AM1

TD2P

O

LVDS Positive Output. (Not used)

AM2

TD2M

O

LVDS Negative Output. (Not used)

AN1

TCLK2P

O

LVDS Positive clock Output. (Not used)

AN2

TCLK2M

O

LVDS Negative clock Output. (Not used)

AP1

TC2P

O

LVDS Positive Output. (Not used)

AP2

TC2M

O

LVDS Negative Output. (Not used)

AM4

LVDS_VDDO

—

LVDS Output buffer VDD (+3.3V).

AP3

TB2P

O

LVDS Positive Output. (Not used)

AN3

TB2M

O

LVDS Negative Output. (Not used)

AP4

TA2P

O

LVDS Positive Output. (Not used)

AN4

TA2M

O

LVDS Negative Output. (Not used)

AJ6

LVDS_VSSO

—

LVDS Output buffer VSS.

AP5

TF1P

O

LVDS Positive Output. (Not used)

AN5

TF1M

O

LVDS Negative Output. (Not used)

AP6

TE1P

O

LVDS Positive Output. (Not used)

AN6

TE1M

O

LVDS Negative Output. (Not used)