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Model
LC-42XL2E (serv.man5)
Pages
42
Size
2.32 MB
Type
PDF
Document
Service Manual
Brand
Device
TV / LCD / Major IC Informations
File
lc-42xl2e-sm5.pdf
Date
PREV: Sharp LC-42XL2E (serv.man4) Service Manual

Sharp LC-42XL2E (serv.man5) Service Manual ▷ View online

LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
5 – 29
AK25
VDB_R0
I/O
Video input/output; Red channel bit 0;
IDE: IDE address bus bit 2.
EJTAG: PCST[8], output as EJTAG PC Trace bus, bit 8.
POD2: POD2_TS1_D1, the second POD_TS1 data[1].
AL25
VDB_R1
I/O
Video input/output; Red channel bit 1;
IDE: IDE bus DMA acknowledge.
EJTAG: PCST[9], output as EJTAG PC Trace bus, bit 9.
POD2: POD2_TS1_D2, the second POD_TS1 data[2].
AM25
VDB_R2
I/O
Video input/output; Red channel bit 2;
IDE: IDE bus IO Read Strobe signal.
EJTAG: PCST[10], output as EJTAG PC Trace bus, bit 10.
POD2: POD2_TS1_D3, the second POD_TS1 data[3].
AN25
VDB_R3
I/O
Video input/output; Red channel bit 3;
IDE: IDE bus IO Write Strobe signal.
EJTAG: PCST[11], output as EJTAG PC Trace bus, bit 11.
POD2: POD2_TS1_D4, the second POD_TS1 data[4].
AP25
VDB_R4
I/O
Video input/output; Red channel bit 4;
IDE: NOP
EJTAG: 
S1=0, select DCLK/TPC[7:0]/PCST[11:0] of host CPU as output.
S1=1, select DCLK/TPC[7:0]/PCST[11:0] of slave CPU as output.
POD2: POD2_TS1_D5, the second POD_TS1 data[5].
AK26
VDB_R5
I/O
Video input/output; Red channel bit 5;
IDE: NOP
EJTAG: 
S1=0, two EJTAG are separately used.
S1=1, two EJTAG are used in a daisy chain style.
POD2: POD2_TS1_D6, the second POD_TS1 data[6].
AL26
VDB_R6
I/O
Video input/output; Red channel bit 6;
IDE: NOP
EJTAG: TDI1, TDI EJTAG input of host CPU CPU.
POD2: POD2_TS1_D7, the second POD_TS1 data[7].
AM26
VDB_R7
I/O
Video input/output; Red channel bit 7;
IDE: NOP
EJTAG: TDO1, TDO EJTAG input of host CPU CPU.
POD2: POD2_TS1_DEN, the second POD_TS1 data valid.
AN26
VDB_R8
I/O
Video input/output; Red channel bit 8;
IDE: NOP
EJTAG: TMS1, TMS EJTAG input of host CPU CPU.
POD2: POD2_TS1_CLK, the second POD_TS1 clock.
AP26
VDB_R9
I/O
Video input/output; Red channel bit 9;
IDE: NOP
EJTAG: TCK1, TCK EJTAG input of host CPU CPU.
POD2: POD2_TS1_SYNC, the second POD_TS1 SYNC.
IEEE1394 Interface, 8051 and 656 share with 1394
AM7, AL7, AK7, AK8, AL8, 
AM8, AK9, AL9
HSD[7:0]
I/O
1394: Parallel data.
Video 656 port; 656D[9:2], data[9:2]
8051: AD[7:0], AD bus.
AM9
HSDCLK
I/O
1394: clock.
Video 656 port; 656CLK, clock.
8051: RD, ALE, address latch enable.
AM10
HSDRW
I/O
1394: Not used.
Video 656 port; 656CHS, horizontal sync.
8051: RD, read signal, low active.
AL10
HSDSYNC
I/O
1394: Packet synchronization.
Video 656 port; 656VS, vertical sync.
8051: WR, write signal, low active.
AK10
HSDAV
I/O
1394: Not used.
Video 656 port; data[1].
8051: NOP
AM11
HSDEN
I/O
1394: Data valid.
Video 656 port; data[0].
8051: CS, chip select.
Transport Stream Interface
G4, G5, F1, F2, F3, F4, F5, 
E5
TS2_D[7:0]
I
Transport Stream 2, data bus.
G3
TS2_DEN
I
Transport Stream 2, data enable.
G2
TS2_SYNC
I
Transport Stream 2, sync signal.
G1
TS2_CLK
I
Transport Stream 2, clock.
Ref No.
Pin Name
I/O
Pin Function
LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
5 – 30
J3, J2, J1, H1, H2, H3, H4, 
H5
TS1_D[7:0]
I
Transport Stream 1, data bus.
J4
TS1_DEN
I
Transport Stream 1, data enable.
J5
TS1_SYNC
I
Transport Stream 1, sync signal.
K1
TS1_CLK
I
Transport Stream 1, clock.
Memory Interface
AM30
DRVIMP
I
Driving strength impedance match reference pin.
AP29
MD0
I/O
Memory data bus.
AP30
MD1
I/O
Memory data bus.
AN30
MD2
I/O
Memory data bus.
AN31
MD3
I/O
Memory data bus.
AM33
DQM0
O
Memory data write mask enable for byte 0.
AM32
DQS0
I/O
Data strobe for memory data bus MD[7:0].
AL32
DQS0N
I/O
Data strobe for memory data bus MD[7:0].
AK30
MD4
I/O
Memory data bus.
AK31
MD5
I/O
Memory data bus.
AJ29
MD6
I/O
Memory data bus.
AJ30
MD7
I/O
Memory data bus.
AP32
MD8
I/O
Memory data bus.
AP33
MD9
I/O
Memory data bus.
AN33
MD10
I/O
Memory data bus.
AN34
MD11
I/O
Memory data bus.
AM34
DQM1
O
Memory data write mask enable for byte 1.
AL33
DQS1
I/O
Data strobe for memory data bus MD[15:8].
AL34
DQS1N
I/O
Data strobe for memory data bus MD[15:8].
AK33
MD12
I/O
Memory data bus.
AK34
MD13
I/O
Memory data bus.
AJ32
MD14
I/O
Memory data bus.
AJ33
MD15
I/O
Memory data bus.
AH33
MCLK0
O
Memory clock for MD[31:0].
AH34
MCLK0N
O
Memory clock for MD[31:0] - active LOW.
AG29
MD16
I/O
Memory data bus.
AG30
MD17
I/O
Memory data bus.
AF30
MD18
I/O
Memory data bus.
AF31
MD19
I/O
Memory data bus.
AE33
DQM2
O
Memory data write mask enable for byte 2.
AE32
DQS2
I/O
Data strobe for memory data bus MD[23:16].
AD32
DQS2N
I/O
Data strobe for memory data bus MD[23:16].
AC30
MD20
I/O
Memory data bus.
AC31
MD21
I/O
Memory data bus.
AB29
MD22
I/O
Memory data bus.
AB30
MD23
I/O
Memory data bus.
AG32
MD24
I/O
Memory data bus.
AG33
MD25
I/O
Memory data bus.
AF33
MD26
I/O
Memory data bus.
AF34
MD27
I/O
Memory data bus.
AE34
DQM3
O
Memory data write mask enable for byte 3.
AD33
DQS3
I/O
Data strobe for memory data bus MD[31:24].
AD34
DQS3N
I/O
Data strobe for memory data bus MD[31:24].
AC33
MD28
I/O
Memory data bus.
AC34
MD29
I/O
Memory data bus.
AB32
MD30
I/O
Memory data bus.
AB33
MD31
I/O
Memory data bus.
Y33
ODT
O
ODT
W34
CAS
O
Column Access Strobe of Port A or SCAN data input.
W33
RAS
O
Row Access Strobe of Port A or SCAN data input.
W31
WE
O
Write Enable of Port A or SCAN data input.
W30
CKE
O
Clock enable.
V34
CS0
O
Chip select for Ext Mem.
Y32
CS1
O
Chip select for Ext Mem.
U33
MAA10
O
Memory Address line of Port A or SCAN data input.
U32
BA1
O
Internal Bank Address Select for SDRAM.
U30
BA0
O
Internal Bank Address Select for SDRAM.
T34
MAA0
O
Memory Address line of Port A or SCAN data output.
T31
MAA1
O
Memory Address line of Port A or SCAN data output.
Ref No.
Pin Name
I/O
Pin Function
LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
5 – 31
T33
MAA2
O
Memory Address line of Port A or SCAN data output.
T30
MAA3
O
Memory Address line of Port A or SCAN data output.
R32
MAA4
O
Memory Address line of Port A or SCAN data output.
R30
MAA5
O
Memory Address line of Port A or SCAN data output.
R33
MAA6
O
Memory Address line of Port A or SCAN data output.
R29
MAA7
O
Memory Address line of Port A or SCAN data output.
P34
MAA11
O
Memory Address line of Port A or SCAN data output.
P33
MAA8
O
Memory Address line of Port A or SCAN data output.
P30
MAA9
O
Memory Address line of Port A or SCAN data output.
N29
MD32
I/O
Memory data bus.
N30
MD33
I/O
Memory data bus.
M30
MD34
I/O
Memory data bus.
M31
MD35
I/O
Memory data bus.
L33
DQM4
O
Memory data write mask enable for byte 4.
L32
DQS4
I/O
Data strobe for memory data bus MD[39:32].
K32
DQS4N
I/O
Data strobe for memory data bus MD[39:32].
J30
MD36
I/O
Memory data bus.
J31
MD37
I/O
Memory data bus.
H29
MD38
I/O
Memory data bus.
H30
MD39
I/O
Memory data bus.
N32
MD40
I/O
Memory data bus.
N33
MD41
I/O
Memory data bus.
M33
MD42
I/O
Memory data bus.
M34
MD43
I/O
Memory data bus.
L34
DQM5
O
Memory data write mask enable for byte 5.
K33
DQS5
I/O
Data strobe for memory data bus MD[47:40].
K34
DQS5N
I/O
Data strobe for memory data bus MD[47:40].
J33
MD44
I/O
Memory data bus.
J34
MD45
I/O
Memory data bus.
H32
MD46
I/O
Memory data bus.
H33
MD47
I/O
Memory data bus.
G33
MCLK1
O
Memory clock for MD[63:32].
G34
MCLK1N
O
Memory clock for MD[63:32] - active LOW.
F29
MD48
I/O
Memory data bus.
F30
MD49
I/O
Memory data bus.
E30
MD50
I/O
Memory data bus.
E31
MD51
I/O
Memory data bus.
D33
DQM6
O
Memory data write mask enable for byte 6.
D32
DQS6
I/O
Data strobe for memory data bus MD[55:48].
C32
DQS6N
I/O
Data strobe for memory data bus MD[55:48].
B30
MD52
I/O
Memory data bus.
B31
MD53
I/O
Memory data bus.
A29
MD54
I/O
Memory data bus.
A30
MD55
I/O
Memory data bus.
F32
MD56
I/O
Memory data bus.
F33
MD57
I/O
Memory data bus.
E33
MD58
I/O
Memory data bus.
E34
MD59
I/O
Memory data bus.
D34
DQM7
O
Memory data write mask enable for byte 7.
C33
DQS7
I/O
Data strobe for memory data bus MD[63:56].
C34
DQS7N
I/O
Data strobe for memory data bus MD[63:56].
B33
MD60
I/O
Memory data bus.
B34
MD61
I/O
Memory data bus.
A32
MD62
I/O
Memory data bus.
A33
MD63
I/O
Memory data bus.
CPU Interface
B26
MASTSEL
I
Lexra bus master select, H:I2C, L:1x5180.
Interrupt Interface
T1
INT1
I
External interrupt, low active Edge or level.
I2C Interface
W5
SCLMAST2
I/O
I2C master 2 clock.
Y5
SDAMAST2
I/O
I2C master 2 data.
AE5
SCLMAST1
I/O
I2C master 1 clock.
AF5
SDAMAST1
I/O
I2C master 1 data.
Ref No.
Pin Name
I/O
Pin Function
LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
5 – 32
I2S Interface
T3
SCKIN
O
I2S: SCK of I2S input port. (Not used)
AC Link: SDATA_OUT
POD2: POD_DRXB, the second POD OOB RX data.
T4
WSI2S
I
I2S: WS of I2S input port. (Not used)
AC Link: ACLINK_RSTN
POD2: POD_CRXB, the second POD OOB RX gapped clock.
T5
SDI2S
I
I2S: SD of I2S input port. (Not used)
AC Link: SYNC
POD2: POD_QTXB, the second POD OOB TXQ channel.
U1
WS
O
I2S: WS of I2S output port.
AC Link: SDATA_IN_2
U2
SCK
O
I2S: SCK of I2S output port.
AC Link: SDATA_IN_3
U3
SD1
O
I2S: SD of I2S output port.
AC Link: BIT_CLK
U4
SD2
O
I2S: SD of I2S output port. (Not used)
AC Link: SDATA_IN_0
U5
SD3
O
I2S: SD of I2S output port. (Not used)
AC Link: SDATA_IN_1
V5
I2SCLK
O
I2S: 1, 2, 4, 8 times of SCK of I2S output port, used by D/A chip.
V4
SD4
I
I2S: SCK of second I2S input port. (Not used)
POD2: POD_ETXB, the second POD OOB TX enable.
V3
SD5
I
I2S: WS of second I2S input port. (Not used)
POD2: POD_ITXB, the second POD OOB TXI channel.
V2
SD6
I
I2S: SD of second I2S input port. (Not used)
POD2: POD_CTXB, the second POD OOB TX gapped symbol clock.
SPDIF Interface
T2
SPDIF
I/O
SPDIF output.
UART Interface
Y4
TXD
O
Data output for UART.
Y3
RTS
O
Request to send output for UART (8mA output pad).
Y2
DTR
O
Data terminal Ready output for UART (8mA output pad, 5V TTL interface 25PF, 6ns 
rise timing).
Y1
RXD
I
Data input for UART.
AA1
CTS
I
Clear to send input for UART.
AA2
DSR
I
Data set ready for UART.
AA3
DCD
I
Receive line signal detect for UART. (Not used)
AA4
RI
I
Ring indicator for UART. (Not used)
Smart card Interface
V1
SCRST
I
Smart card reset 0, 8mA open-drain output pad. (Not used)
W1
SCPFET
I
Smart card power FET control output, 8mA open-drain output. The smart card reader 
interface requires this pin to drive an external power FET to supply the current for the 
Smart Card (65mA typical, 100mA short to ground). (Not used)
W2
SCIO
I/O
Smart card serial data, 8mA open-drain in out pad. (Not used)
W3
SCCLK
O
Smart card clock, 8mA open-drain output pad (7.1M to 3.5M) (Not used)
W4
SCPRES
I
Smart card present detect. (Not used)
CIR, RTC Interface
M1
VCCH12
—
1.2V RTC power for logic.
N1
VSSH12
—
RTC ground for logic.
L1
WDOG
O
Watch dog reset.
L2
VCCH33
—
3.3V RTC power for logic.
L3
CK32
I
32.768 kHz crystal oscillator input.
L4
CK32E
O
32.768 kHz crystal oscillator output.
L5
VSSH33
—
RTC ground for logic.
M5
CRX0
I
CIR0, receive data for CIRo interface.
M4
PWRON
O
Main power, power On control signal, low active, 4mA output pad. (Not used)
M3
PWRBT
I
Power switch button.
M2
VCCHRST
I
VCCH RST 
K4
VCCH12
—
1.2V RTC power for logic.
K5
VSSH12
—
RTC ground for logic.
R1
CTX0
O
Transmission data for CIR interface.
Program IO
AF4
GP15
I/O
Program IO.
PWM: Pulse-Width Modulation.
POD: OVERLOAD, the second POD interface current overload.
Ref No.
Pin Name
I/O
Pin Function
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