Sharp AR-BD14 (serv.man5) Service Manual ▷ View online
Pin No.
Pin Name
Signal Name
Pull Up/
Pull Dn
Type
Description
Bidirectional Centronics
64
CWOE
∗
CWOE
O
Centronics Write Output Enable: Controls the Output Enable signal of the
data register -from the peripheral to the host.
data register -from the peripheral to the host.
59
CROE
∗
CROE
O
Centronics Read Output Enable: Controls the OE of the Centronics
external register in the direction from the host to the peripheral (to the
IODATA(7:0) bus).
external register in the direction from the host to the peripheral (to the
IODATA(7:0) bus).
58
CWSTROBE
CWSTROBE
O
Centronics Write Strobe: Clocks data from the IODATA(7-0) into the
Centronics register (from peripheral to host).
Centronics register (from peripheral to host).
53
CRSTROBE
CRSTROBE
O
Centronics Read Strobe: Clocks data from the host into the Centronics
register (from host to peripheral).
register (from host to peripheral).
52
CSTROBE
∗
PALSTROBE
P.U.
I
Centronics Strobe signal
65
CACK
∗
CENTACK
O
Centronics acknowledge signal
54
CBUSY
CENTBUSY
O
Centronics Busy signal
62
CPERROR
CENTPERROR
O
Centronics Printer Error signal
63
CSELECT
CENTSELECT
O
Centronics Select signal
61
CAUTOFD
∗
PALAUTOFD
P.U.
I
Centronics Autofeed signal
51
CINIT
∗
N9
CENTINIT
CENTINIT
P.U.
I
Centronics Initialize signal
66
CFAULT
∗
CENTFAULT
O
Centronics Fault signal
50
CSELECTIN
∗
PALSELIN
P.U.
I
Centronics Select Input signal
Parallel Port Control
68
PSTROBE
∗
N.C.
O
Parallel Strobe: Clocks 8-bit or 16-bit parallel data from IODATA[15:0]
67
POE
∗
N.C.
O
Parallel Output Enable: When active (LOW), it controls the output enable
of a data buffer for 8-bit or 16-bit wide parallel data into IODATA[15:0]
of a data buffer for 8-bit or 16-bit wide parallel data into IODATA[15:0]
Video Control
137
VCLKIN
VCLGIO
P.U.
I
Video Clock In: Used for generating the video clock VCLK which is the
video data clock. The VCLKIN frequency is either VCLK
video data clock. The VCLKIN frequency is either VCLK
×
8 or VCLK.
138
VDATA
VDATA
O
Video Data: to the printer.
135
LINESYNC
∗
HSYNCGIO
P.U.
I
Line Synchronization: Input from the printer that indicates the beginning
of a line. In some printers this is called Beam Detect (BD) or SYNCBD
of a line. In some printers this is called Beam Detect (BD) or SYNCBD
∗
.
NOTE: LINESYNC
∗
is an edge-sensitive signal. It is clocked into the
3710/40 by the internal signal VCLK, where VCLK is equal to VCLKIN/8
when the PLL is used, and VCLKIN when the PLL is bypassed.
when the PLL is used, and VCLKIN when the PLL is bypassed.
136
PAGESYNC
∗
PSYNCGIO
P.U.
I
Page Synchronization: Input from the printer that indicates the beginning
of the page.
of the page.
VSYNC2
NOTE: PAGESYNC
∗
is an edge-sensitive signal. It is clocked into the
3710/40 by the internal signal VCLK, where VCLK is equal to VCLKIN/8
when the PLL is used, and VCLKIN when the PLL is bypassed.
when the PLL is used, and VCLKIN when the PLL is bypassed.
Misc.
160
TEST
GND FIXED
P.D.
I
Master Output Enable: When TEST is HIGH and RESET
∗
is active, All the
device outputs and I/Os are tri-stated.
29
RESET
∗
RESETO
I
Reset: Active low-will reset the GT-32011 to the initial state.
VDD
+5V (+/–5%)
VSS
Ground
NOTE: Pull Up/Pull Dn designates those pins with internal Pull Up (P.U.) or Pull Down (P.D.) resistors
– 31 –
B. Program memory section (EPROM)
The EPROM has the capacity of 1MB (4Mbit
×
2) and stores various
set values of the program and the printer.
ROM Block (EPROM & Flash ROM)
C. Flash memory section (Flash ROM)
The flash ROM has the capacity of 8MB (16Mbit
×
4), and stores the
program codes and font data used by PS/PCL.
D. Image development memory section (DRAM)
The built-in DRAM has the capacity of 16MB (16Mbit
×
8), and is
used as the image data development area for printing and the work
area for the program.
area for the program.
For expansion, one slot area is provided to allow connection of 72 pin
SIMM memory (16MB).
SIMM memory (16MB).
DRAM Block
E. Centronics interface section
The Centronics interface section is composed for supporting the con-
ventional compatible mode and the nibble mode.
ventional compatible mode and the nibble mode.
Centronics I/F Block
CPU
R3081
GT-32011
373
245
SEL
System-Bus
Address-Bus
ALE
Data-Bus
/OE
/ROMCS2
/WE
/CE
/CE
/FLASH_WE
EPROM
1MB
32bit-width
Flash-A
4MB
32bit-width
Flash-B
4MB
32bit-width
G/A
LZ95NA8
A22
GT-32011
245
System-Bus
DRAM-Address (10:0)
Data-Bus
/OE
827
/RAS0
/RAS1
/RAS2
/RAS0A
/RAS1A
/RAS1B
/CAS0,1,2,3
EPLD
CE16V8
CPU
R3081
DRAM
16MB
32bit-width
SIMM
1slot
16MB
32bit-width
GT-32011
373
System-Bus
16bit I/O bus (7:0)
ALE
/IOGPCS0
G/A
LZ95NA8
52BT
245
Parallel
I/F
CD7:0
244
244
SELECT
ERROR
BUSY
/ACK
/STROBE
/AUTOFD
/AUTOFD
/SELIN
/INIT
/CS
A23,22,21
IDT
R3741
CPU
R3081
– 32 –
Pin Assignment Table <ASIC: R3741>
CPU pins identified with an asterisk are active when LOW.
Centronics signals preceded by an ‘n’ are active when LOW.
Pin No.
Pin Name
Signal Name
I/O
Description
ASIC: GT-32011 interface
43
SYSCLK
∗
BSYCLK2
I
System Clock: connects directly to the CPU SYSCLK* output.
1
SYSRESET
∗
RESETO
I
System Reset: resets the R3741 to its initial state.
16, 24:29
IODATA[7:0]
IODATA[7:0]
I/O
Input/Output Device Data: connects directly to bits [7:0] of the Bidirectional
I/O Data bus.
I/O Data bus.
5, 8
IOA[3:2]
A[3:2]
I
Input/Output Address Bus: connect to two (2) I/O address lines.
4
IOCS
∗
CS3741
I
Input/Output Chip Select: connects to a chip select for the 8-bit I/O data bus.
6
IOWR
∗
IOWR
I
Input/Output Device Write: connects directly to ASIC: GT-32011 IOWR
∗
.
18
IORD
∗
IORD
I
Input/Output Device Read: connects directly to ASIC: GT-32011 IORD
∗
.
31
INTERRUPT
∗
INT1284
O
Interrupt: indicates detection of an initialization strobe during compatibility
mode. Should be connected to an ASIC: GT-32011 interrupt line.
mode. Should be connected to an ASIC: GT-32011 interrupt line.
ASIC: GT-32011 Centronics Peripheral Status Signals
2
nACK
CENTACK
I
ASIC: GT-32011 Centronics Acknowledge: connects directly to the ASIC:
GT-32011 CACK
GT-32011 CACK
∗
signal.
13
BUSY
CENTBUSY
I
ASIC: GT-32011 Centronics Busy: connects directly to the ASIC: GT-32011
CBUSY signal.
CBUSY signal.
20
nFAULT
CENTFAULT
I
ASIC: GT-32011 Centronics Fault: connects directly to the ASIC: GT-32011
CFAULT
CFAULT
∗
signal.
11
PERROR
CENTPERROR
I
ASIC: GT-32011 Centronics Peripheral Error: connects directly to the ASIC:
GT-32011 CPERROR signal.
GT-32011 CPERROR signal.
17
SELECT
CENTSELECT
I
ASIC: GT-32011 Centronics Select: connects directly to the ASIC:
GT-32011 CSELECT signal.
GT-32011 CSELECT signal.
Modified Centronics Peripheral Status Signals
38
pld_nACK
PALACK
O
modified Centronics Acknowledge: connects to the Centronics connector
nACK signal through a series resistor (may be buffered if desired).
nACK signal through a series resistor (may be buffered if desired).
40
pld_BUSY
PALAUTOFD
O
modified Centronics Busy: connects to the Centronics connector Busy signal
through a series resistor (may be buffered if desired).
through a series resistor (may be buffered if desired).
37
pld_nFAULT
PALFAULT
O
modified Centronics Fault: connects to the Centronics connector nFAULT
signal through a series resistor (may be buffered if desired).
signal through a series resistor (may be buffered if desired).
14
pld_PERROR
PALERROR
O
modified Centronics Peripheral Error: connects to the Centronics connector
PERROR signal through a series resister (may be buffered if desired).
PERROR signal through a series resister (may be buffered if desired).
34
pld_SELECT
PALSELECT
O
modified Centronics Select: connects to the Centronics connector Select
signal through a series resistor (may be buffered if desired)
signal through a series resistor (may be buffered if desired)
Centronics Host Status Signals
21
nSELECTIN
CENTSELIN
I
Centronics SelectIn: connects to the Centronics connector nSELECTIN
signal (may be connected to an external buffer first, if desired).
signal (may be connected to an external buffer first, if desired).
9
nSTROBE
CENTSTROBE
I
Centronics Strobe: connects to the Centronics connector STROBE signal
(may be connected to an external buffer first, if desired).
(may be connected to an external buffer first, if desired).
7
nAUTOFD
CENTAUTOFD
I
Centronics Auto Feed: connects to the Centronics connector nAUTOFD
signal (may be connected to an external buffer first, if desired).
signal (may be connected to an external buffer first, if desired).
12
nINIT
N9
I
Centronics Initialization: connects to the Centronics connector nINIT signal
(may be connected to an external buffer first, if desired).
(may be connected to an external buffer first, if desired).
Modified Centronics Host Status Signals
36
pld_nSELECTIN
PALSELIN
O
modified SelectIn: connects directly to ASIC: GT-32011 CSELECTIN* signal.
33
pld_nSTROBE
PALSTROBE
O
modified Strobe: connects directly to ASIC: GT-32011 CSTROBE* signal.
39
pld_nAUTOFD
PALAUTOFD
O
modified AutoFeed: connects directly to ASIC: GT-32011 CAUTOFD* signal.
19
pld_nINIT
IORD
O
modified Initialization: connects directly to ASIC: GT-32011 CINIT* signal.
– 33 –
F. Expansion interface section
For the expansion interface, one slot is provided to allow a network
card, enabling the network connection.
card, enabling the network connection.
LAN I/F
The LAN board will provide an interface that consists of a 16 bit data
bus accessing a maximum of 64 KBytes of shared memory and an
interrupt control register, 17 addressing bits, interrupt lines, and con-
trol lines.
bus accessing a maximum of 64 KBytes of shared memory and an
interrupt control register, 17 addressing bits, interrupt lines, and con-
trol lines.
Signal Description (Between ICU board and LAN I/F board)
Pin No.
Signal
Name
Name
Direction
Description
21, 19, 18,
17, 37, 44,
42, 40, 38,
36, 34, 32,
30, 28, 26,
17, 37, 44,
42, 40, 38,
36, 34, 32,
30, 28, 26,
24, 49
A0 – A16
OUT
Address lines that are used to access
the shared memory space. A0 - least
significant bit. word only accesses to
shared memory.
the shared memory space. A0 - least
significant bit. word only accesses to
shared memory.
35, 33, 31,
29, 27, 25,
23, 22, 14,
13, 11, 10,
29, 27, 25,
23, 22, 14,
13, 11, 10,
9, 7, 6, 5
D0 – 15
IN/OUT
Bi-directional data lines carrying the
data for memory requests. These lines
are buffered on the LAN board. D0 -
least significant bit.
data for memory requests. These lines
are buffered on the LAN board. D0 -
least significant bit.
*
Loading will not exceed 1 LS TTL
load.
39
RESET-
OUT
Reset line to LAN board. This line is
used by the printer to request a
hardware reset.
Active Low.
used by the printer to request a
hardware reset.
Active Low.
43
NETCS-
OUT
Printer chip select pins. These lines
are used by the printer to indicate a
valid address for a memory operation.
NETCS- will only be active to LAN
board accesses.
Active Low.
are used by the printer to indicate a
valid address for a memory operation.
NETCS- will only be active to LAN
board accesses.
Active Low.
45
NETOE-
OUT
Printer output enable pin. This line is
used by the printer to indicate the
printer bus is available. This signal is
qualified by NETCS-
Active Low.
used by the printer to indicate the
printer bus is available. This signal is
qualified by NETCS-
Active Low.
47
R/W-
OUT
Printer Read/Write line. This line is
used by the printer to indicate a read
or write cycle.
Write Active Low.
used by the printer to indicate a read
or write cycle.
Write Active Low.
41
NETRDY-
IN
LAN board Ready line. LAN board will
set this line active on a access to the
LAN board. It will be used to hold off a
printer access to shared memory.
Active Low.
set this line active on a access to the
LAN board. It will be used to hold off a
printer access to shared memory.
Active Low.
15
NETINT-
IN
Interrupt printer. This line indicates the
LAN board wants to interrupt the
printer. The LAN board will set this line
low if Bit 3 of the ICR register is a "0".
Active Low.
LAN board wants to interrupt the
printer. The LAN board will set this line
low if Bit 3 of the ICR register is a "0".
Active Low.
57
NETON-
OUT
Board plugged in line. A low on this
line signifies a LAN board is plugged
into the printer.
Active Low.
line signifies a LAN board is plugged
into the printer.
Active Low.
1, 2, 3, 58,
59, 60
VCC
+5V power lines. These lines provide a
continuous
continuous
8, 12, 16,
48, 52, 56
GND
Ground lines. These lines provide a
common reference for bus and control
signals and provide a return for the
+5V power lines.
common reference for bus and control
signals and provide a return for the
+5V power lines.
AC and DC Signal Specifications
Timing Specification
NETCS, NETOE-, R/W-, NETRDY-
These signals are used as control lines to read and write data to
the LAN board.
the LAN board.
R/W- is set high or low to indicate a read (1) or write (0) cycle.
NETCS- is set low by the printer to signal a memory access is
required and the printer address is now valid.
NETCS- is set low by the printer to signal a memory access is
required and the printer address is now valid.
The LAN board will set NETRDI- within 30nS of receiving NETCS-
Upon receiving a NETCS- the LAN board will begin memory ar-
bitration with the printer. NETRDY- will be deasserted when the
LAN board memory arbiter determines the bus is available.
bitration with the printer. NETRDY- will be deasserted when the
LAN board memory arbiter determines the bus is available.
MAXIMUM TIME BEFORE LAN BOARD COMPLETES THE
PRINTER ACCESS IS 530nS.
PRINTER ACCESS IS 530nS.
The printer will finish its memory access cycle by deasserting
NETCS- and NETOE-
NETCS- and NETOE-
Address and Data signals.
READ:
Address and R/W- will be valid before NETCS- is as-
serted. Data will be valid before NERDY is deasserted.
serted. Data will be valid before NERDY is deasserted.
WRITE:
Address and RW- will be valid before CSPn- is as-
serted. Data will be valid for the duration of the CPSn-
signal.
serted. Data will be valid for the duration of the CPSn-
signal.
Common Memory
A maximum of 64 KBytes will allocated for shared memory access.
Common memory will be allocated at LAN board locations 0000 thru
FFFF.
Common memory will be allocated at LAN board locations 0000 thru
FFFF.
G. I/O and peripheral control section
For control of I/O and peripheral circuits, the LZ95NA8: QFP100PIN
(1600 gate) is used. With this G/A, generating each I/O select signal,
image output control, flash write control are processed. For details of
this G/A signal line, refer to the table below.
(1600 gate) is used. With this G/A, generating each I/O select signal,
image output control, flash write control are processed. For details of
this G/A signal line, refer to the table below.
(G/A LZ95NA8 signal descriptions)
Pin
No.
Signal
name
I/O
Functions
1
PCLK
IBFSA
Horizontal effective area clock
2
TCNTO
IBF
Test signal 0 for counter
3
A22
IBF
Address 22
4
IOWR-
IBF
I/O write signal from LZ95NA8
5
TEST-
IBF
Test signal (L: test mode)
6
BE2-
IBF
Byte enable signal 2
7
EDMAK-
IBF
DMA acknowledge signal
8
RAS1-
IBF
DRAM row address select signal 1
from LZ95NA8
from LZ95NA8
9
BE3-
IBF
Byte enable signal 3
10
ED04
IBF
I/O data 4
11
RAS0-
IBF
DRAM row address select signal 0
from LZ95NA8
from LZ95NA8
12
ED05
IBF
I/O data 5
13
GND
14
BE0-
IBF
Byte enable signal 0
15
PD1
IBF
DRAM module presence detect pin 1
16
PD0
IBF
DRAM module presence detect pin 0
17
RMCS0-
IBF
ROM chip select signal 0
18
SELI2-
IBF
Interruption select signal 2
19
A5
IBF
Address 5
20
N.C
21
BE1-
IBF
Byte enable signal 1
22
VSYNC-
IBF
Vertical sync signal
23
A4
IBF
Address 4
– 34 –
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