Sharp AR-BD14 (serv.man5) Service Manual ▷ View online
Pin
No.
Signal
name
I/O
Functions
24
RAS2-
IBF
DRAM row address select signal 2
from LZ95NA8
from LZ95NA8
25
IDREQ
IBF
Input data request signal from PM2
26
ED06
IBF
I/O data 6
27
ACK-
IBF
Acknowledge signal from LZ95NA8
28
GND
29
ED07
IBF
I/O data 7
30
CWOE-
IBF
Centronics write output enable signal
31
SELI3-
IBF
Interruption select signal 3
32
A1
OBF
Address 1
33
RMCSJ-
IBF
ROM chip select signal 2 JUMP
34
SELI5-
IBF
Interruption select signal 5
35
A0
OBF
Address 0
36
VCC
37
RMCS2-
IBF
ROM chip select signal
38
ED00
IBF
I/O data 0
39
AREA2-
OBF
Horizontal effective area signal
40
GND
41
VCC
42
SINT0-
OBF
Interruption signal to CPU
43
RAS1A-
OBF
DRAM module row address select
signal
signal
44
EDMREQ
OBF
DMA request to LZ95NA8
45
GND
46
RAS1B-
OBF
DRAM module row address select
signal
signal
47
ODACK-
OBF
Output data strobe to PM2
48
INT4-
OBF
Interruption signal to CPU
49
RAS0A-
OBF
DRAM row address select signal
50
INT5-
OBF
Interruption signal to CPU
51
IDACK-
OBF
Input data strobe to PM2
52
INT3-
OBF
Interruption signal to CPU
53
TCNT1
IBF
Test signal 1 for counter
54
CTWRE-
OBF
Centronics write register output
enable signal
enable signal
55
CTDIR-
OBF
Centronics data output enable signal
56
HSYNC-
IBF
Horizontal sync signal
57
10GP1-
IBF
I/O chip select signal 1 (16bit I/O)
from LZ95NA8
from LZ95NA8
58
HSYN2-
OBF
Horizontal sync signal 2
59
QCLK
OBF
Output clock 6.25MHz
60
CSEET-
OBF
D9001MF chip select signal
61
GND
62
CSPM2-
OBF
PM2 chip select signal
63
CS374-
OBF
79R3741 chip select signal
64
TEST0
OBF
Schmidt buffer test pin
65
CS85C-
OBF
85C30 chip select signal
66
PIORD-
OBF
8bit i/o read signal
67
FLAWE-
OBF
Flash memory write signal
68
VCC
69
ROMOE-
OBF
Flash memory output enable signal
70
WR85C-
OBF
85C30 write signal
71
PIOWR-
OBF
8bit I/O write signal
72
RES16-
OBF
I/O chip select signal (16bit I/O)
reserve 1
reserve 1
73
HCLK
OBF
Output clock 12.5MHz
74
EXT16-
OBF
I/O chip select signal (16bit I/O)
reserve 1
reserve 1
75
RD85C-
OBF
85C30 read signal
Pin
No.
Signal
name
I/O
Functions
76
GND
77
INT37-
IBF
Interruption signal from LZ95NA8
78
ED03
IBF
I/O data 3
79
INT12-
IBF
Interruption signal from 79R3741
80
ED02
IBF
I/O data 2
81
WR-
IBF
Write signal from CPU
82
INT85-
IBF
Interruption signal from 85C30
83
VSYN2-
OBF
Vertical sync signal 2
84
VCC
85
INTPM-
IBF
Interruption signal from PM2
86
SELI4-
IBF
Interruption select signal 4
87
ED01
IBF
I/O data 1
88
GND
89
VCC
90
GND
91
RESET-
IBF
Reset signal
92
BSYSCK
IBFSA
Input clock 25MHz
93
VCC
94
ODREQ
IBF
Output data request from PM2
95
N.C.
96
IOGP0-
IBF
I/O chip select signal 0 (16bit I/O)
from LZ95NA8
from LZ95NA8
97
GND
98
IORD-
IBF
I/O read signal from LZ95NA8
99
A21
IBF
Address 21
100
A23
IBF
Address 23
H. Image output section and smoothing section
Output control of print data formed in the print PWB is performed by
the engine output section assembled in the GT-32011. By inputting
the serial image data from this circuit to D9001MF, smoothing is
performed.
the engine output section assembled in the GT-32011. By inputting
the serial image data from this circuit to D9001MF, smoothing is
performed.
Engine I/F Block
GT-32011
373
System-Bus
16bit I/O bus (7:0)
ALE
/IOGPCS0
A23,22,21
/CS
/AREA2
/DTEN2
/HS2
VIDEO
/HSYNC2
VD
DCLK
ICU I/F
EET
D9001
MF
G/A
LZ95NA8
CPU
R3081
OSC
58.465
Mhz
– 35 –
I. NVRAM section
This is the SRAM (8KByte) having the backup function of various set
values used for printer control.
values used for printer control.
NVRAM Block (DS1643)
Features
•
Form, fit, and function compatible with the MK48T08 Timekeeping
RAM
RAM
•
Integrated NV SRAM, real time clock, crystal, power fail control
circuit and lithium energy source
circuit and lithium energy source
•
Standard JEDEC bytewide 8K
×
8 static RAM pinout
•
Clock registers are accessed identical to the static RAM. These
registers are resident in the eight top RAM locations.
registers are resident in the eight top RAM locations.
•
Totally nonvolatile with over 10 years of operation in the absence
of power
of power
•
Access times of 120 ns and 150 ns
•
Quartz accuracy
±
1 minute a month @ 25°C, factory calibrated
•
BCD coded year, month, date, day, hours, minutes, and seconds
•
Power fail write protection allows for
±
10% V
CC
power supply
tolerance
•
Optional Low Profile Module (LPM)
– Fits into standard 52-pin PLCC surface mountable socket
– 225 mil package height
Pin Assignment
GT-32011
373
System-Bus
16bit I/O bus (7:0)
Address-Bus (13:1)
ALE
/IOCS0
CPU
R3081
NVRAM
8KB
8bit-width
NC
1
A12
2
A7
3
A6
4
A5
5
A4
6
A3
7
A2
8
A1
9
A0
10
DQ0
11
DQ1
12
DQ2
13
GND
14
VCC
28
WE
27
CE2
26
A8
25
A9
24
A11
23
OE
22
A10
21
CE
20
DQ7
19
DQ6
18
DQ5
17
DQ4
16
DQ3
15
28-Pin Encapsulated Package
(700 Mil Extended)
Pin Description
Pin
No.
Pin
Name
Signal Name
Description
Pin
No.
Pin
Name
Signal Name
Description
1
NC
/RDY_BUSY BUSY signal of this device
15
DQ3
IODATA3
Input/Output Device Data: connects
directly to bits of the bi-directional I/O
Data bus.
directly to bits of the bi-directional I/O
Data bus.
2
A12
A13
Address Bus
16
DQ4
IODATA4
Input/Output Device Data: connects
directly to bits of the bi-directional I/O
Data bus.
directly to bits of the bi-directional I/O
Data bus.
3
A7
A8
Address Bus
17
DQ5
IODATA5
Input/Output Device Data: connects
directly to bits of the bi-directional I/O
Data bus.
directly to bits of the bi-directional I/O
Data bus.
4
A6
A7
Address Bus
18
DQ6
IODATA6
Input/Output Device Data: connects
directly to bits of the bi-directional I/O
Data bus.
directly to bits of the bi-directional I/O
Data bus.
5
A5
A6
Address Bus
19
DQ7
IODATA7
Input/Output Device Data: connects
directly to bits of the bi-directional I/O
Data bus.
directly to bits of the bi-directional I/O
Data bus.
6
A4
A5
Address Bus
20
/CE
/IOCS0
Input/Output Chip Select: connects to a
chip select for the 8-bit I/O Data bus.
chip select for the 8-bit I/O Data bus.
7
A3
A4
Address Bus
21
A10
A11
Address Bus
8
A2
A3
Address Bus
22
/OE
/IOCRD
Input/Output Device Read: connects
directly to a chip ASIC: GT32011 /IORD.
directly to a chip ASIC: GT32011 /IORD.
9
A1
A2
Address Bus
23
A11
A12
Address Bus
10
A0
EA1
Address Bus
24
A9
A10
Address Bus
11
DQ0
IODATA0
Input/Output Device Data: connects
directly to bits of the bi-directional I/O
directly to bits of the bi-directional I/O
25
A8
A9
Address Bus
12
DQ1
IODATA1
Input/Output Device Data: connects
directly to bits of the bi-directional I/O
directly to bits of the bi-directional I/O
26
CE2
IOCS0
Input/Output Chip Select: connects to a
chip select for the 8-bit I/O Data bus.
chip select for the 8-bit I/O Data bus.
13
DQ2
IODATA2
Input/Output Device Data: connects
directly to bits of the bi-directional I/O
directly to bits of the bi-directional I/O
27
/WE
/IOWR
Input/Ouput Device Write: connects
directly to a chip ASIC: GT32011 /IOWR.
directly to a chip ASIC: GT32011 /IOWR.
14
GND
GND
Ground
28
VCC
+5V
Power Voltage
– 36 –
(4) Connection between the printer PWB
and the copier body
The printer PWB and the copier is connected via the mother board.
A. Signal lines in the connection section of the
copier and the printer PWB (128A-064S2C-L14A)
Pin
No.
Signal name
I/O
Function
1
D0
I
Image input data 0
2
D1
I
Image input data 1
3
D2
I
Image input data 2
4
D3
I
Image input data 3
5
D4
I
Image input data 4
6
D5
I
Image input data 5
7
D6
I
Image input data 6
8
D7
I
Image input data 7
9
GND2
—
10
N.C.
—
11
GND2
—
12
/HSYNC1
I
Horizontal sync signal (input)
13
GND2
—
14
/AREA1
I
Horizontal effective area (input)
15
GND2
—
16
/HSYNC2
I
Horizontal sync signal (output)
17
GND2
—
18
/AREA2
O
Horizontal effective area (output)
19
GND2
—
20
/DTEN1
I
Vertical sync signal (input)
21
GND2
—
22
/DTEN2
I
Vertical sync signal (output)
23
GND2
—
24
VIDEO
O
Image output signal (output)
25
GND2
—
26
N.C.
—
27
GND2
—
28
N.C.
—
29
GND2
—
30
/PRTCHIN
O
Board detect signal
31
RES-PRT
I
Reset signal
32
+5V1
I
33
/DSR-PRT
O
Data terminal ready
34
+5V1
I
35
/DTR-PRT
I
Data set ready
36
+5V1
I
37
RXD-PRT
O
Send data
38
+5V1
I
39
TXD-PRT
I
Receive data
40
GND2
—
41
RESERVED1
—
42
GND2
—
43
RESERVED2
—
44
GND2
—
45
RESERVED3
—
46
GND2
—
47
TEST
O
48
GND2
—
49
PRT-A
I
Pin
No.
Signal name
I/O
Function
50
GND2
—
51
PRT-B
O
52
GND2
—
53
GND2
—
54
GND2
—
55
GND2
—
56
GND2
—
57
GND2
—
58
GND2
—
59
GND2
—
60
GND2
—
61
GND2
—
62
GND2
—
63
GND2
—
64
GND2
—
(5) Interface
A. General
This interface is made by expanding the conventional Centronics in-
terface to bi-direction. Bi-directional communication is performed by
the Centronics interface signals. This interface supports the Nibble
mode and the compatible mode. Recognition of the interface signal
depends on the operation mode. In the compatible mode, data sent
from the conventional host computer are received by the printer side.
In the Nibble mode, the operation is controlled by the host computer,
supplying asynchronous reverse-direction channel (printer to host
computer). Especially in the Nibble mode, the status information of
the printer side is sent to the host computer.
terface to bi-direction. Bi-directional communication is performed by
the Centronics interface signals. This interface supports the Nibble
mode and the compatible mode. Recognition of the interface signal
depends on the operation mode. In the compatible mode, data sent
from the conventional host computer are received by the printer side.
In the Nibble mode, the operation is controlled by the host computer,
supplying asynchronous reverse-direction channel (printer to host
computer). Especially in the Nibble mode, the status information of
the printer side is sent to the host computer.
B. Connector
Female 36pin DDK57RE-40360-830B (D29) or equivalent
C. Interface cable
IEEE-1284 conforming cable with shield and grounded.
*
The cable length must be max. 3.0m.
*
To ensure the maximum performance and bi-directional com-
munication, be sure to use a cable conforming to IEEE-1284.
munication, be sure to use a cable conforming to IEEE-1284.
18
1
36
19
– 37 –
D. Pin No. and signal name
Pin No. and signal names are shown in the table below.
1284-B connector pin arrangement
Pin
No.
Source
Mode
Compatible
Nibble
Byte (Not used)
Peppy (Not used)
EPP (Not used)
1
H
nStrobe
HostClk
HostClk
HostClk
nWrite
2
Bi-direction
Data 1 (LFB: Least Significant Bit)
AD1
3
Bi-direction
Data 2
AD2
4
Bi-direction
Data 3
AD3
5
Bi-direction
Data 4
AD4
6
Bi-direction
Data 5
AD5
7
Bi-direction
Data 6
AD6
8
Bi-direction
Data 7
AD7
9
Bi-direction
Data 8 (MSB: Most Significant Bit)
AD8
10
P
nAck
PrtClk
PrtClk
PeriphClk
Intr
11
P
Busy
PrtBusy
PrtBusy
PeriphAck
nWait
12
P
PError
AckDataReq
AckDataReq
nAckReverse
User definition 1
13
P
Select
Xflag
Xflag
Xflag
User definition 3
14
H
nAutoFd
Hostbusy
HostBusy
HostAck
nDStrb
15
Not defined.
16
Logic GND
17
Chassis GND
18
P
Peripheral logic
19
Signal GND (nStrobe)
20
Signal GND (data 1)
21
Signal GND (data 2)
22
Signal GND (data 3)
23
Signal GND (data 4)
24
Signal GND (data 5)
25
Signal GND (data 6)
26
Signal GND (data 7)
27
Signal GND (data 8)
28
Signal GND (PError, Select, nAct)
29
Signal GND (Busy, nFault)
30
Signal GND (nAutoFd, nSelectin, nlnit)
31
H
nlnit
nlnit
nlnit
nReserve request
nlnit
32
P
nFault
nDataAvail
nDataAvail
nPeriph request
User definition 2
33
Not defined.
34
Not defined.
35
Not defined.
36
H
nSelectIn
1284 Active
1284 Active
1284 Active
nAStrb
*
Data signals are driven by some peripheral devices.
The pins which are not defined by this specification must be defined by the user.
The 1284-B connector is of 36 signal ribbon type.
E. 1284 protocol
AR-5132 support protocol
•
Compatibility Mode
Normally
•
Device ID (Nibble Mode)
When Windows 95 PC is started.
PC
Win95
operating
operating
Win95
reoperating
reoperating
Win95
operating
operating
Win95
end
end
Win95
start
start
Win95
operating
operating
Compatibility Mode
Device ID (Nibble Mode)
P1284 Mode
– 38 –
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