Sharp AR-BD14 (serv.man5) Service Manual ▷ View online
Pin No
Pin name
Signal name
I/O
Description
46
ALE
ALE
I/O
Address Latch Enable: Used to indicate that the A/D bus contains valid address information
for the bus transaction. This signal is used by external logic to capture the address for the
transfer, typically using transparent latches.
for the bus transaction. This signal is used by external logic to capture the address for the
transfer, typically using transparent latches.
During cache coherency operations, the R3081 monitors ALE at the start of a DMA write, to
capture the write target address for potential data cache invalidates.
capture the write target address for potential data cache invalidates.
45
Rd
RD
O
Read: An output which indicates that the current bus transaction is a read.
44
Wr
WR
I/O
Write: An output which indicates that the current bus transaction is a write. During coherent
DMA, this input indicates that the current transfer is a write.
DMA, this input indicates that the current transfer is a write.
43
DataEn
DATAEN
O
External Data Enable: This signal indicates that the A/D bus is no longer being driven by the
processor during read cycles, and thus the external memory system may enable the drivers
of the memory system onto this bus without having a bus conflict occur. During write cycles,
or when no bus transaction is occurring, this signal is negated, thus disabling the external
memory drivers.
processor during read cycles, and thus the external memory system may enable the drivers
of the memory system onto this bus without having a bus conflict occur. During write cycles,
or when no bus transaction is occurring, this signal is negated, thus disabling the external
memory drivers.
53
Burst/WrNear
BURST
O
Burst Transfer/Write Near: On read transactions, the Burst signal indicates that the current
bus read is requesting a block of four contiguous words from memory. This signal is asserted
only in read cycles due to cache misses; it is asserted for all-Cache miss read cycles, and for
D-Cache miss read cycles if quad word refill is currently selected.
bus read is requesting a block of four contiguous words from memory. This signal is asserted
only in read cycles due to cache misses; it is asserted for all-Cache miss read cycles, and for
D-Cache miss read cycles if quad word refill is currently selected.
On write transactions, the WrNear output tells the external memory system that the bus
interface unit is performing back-to-back write transactions to an address within the same 512
word page as the prior write transaction. This signal is useful in memory systems which
employ page mode or static column DRAMs, and allows near writes to be retired quickly.
interface unit is performing back-to-back write transactions to an address within the same 512
word page as the prior write transaction. This signal is useful in memory systems which
employ page mode or static column DRAMs, and allows near writes to be retired quickly.
36
Ack
ACK
I
Acknowledge: An input which indicates to the device that the memory system has sufficient-
ly processed the bus transaction, and that the CPU may either terminate the write cycle or
process the read data from this read transfer.
ly processed the bus transaction, and that the CPU may either terminate the write cycle or
process the read data from this read transfer.
During Coherent DMA, this input indicates that the current write transfer is completed, and
that the internal invalidation address counter should be incremented.
that the internal invalidation address counter should be incremented.
35
RdCEn
RDCEN
I
Read Buffer Clock Enable: An input which indicates to the device that the memory system
has placed valid data on the A/D bus, and that the processor may move the data into the
on-chip Read Buffer.
has placed valid data on the A/D bus, and that the processor may move the data into the
on-chip Read Buffer.
40
SysClk
SYSCLK
O
System Reference Clock: An output from the CPU which reflects the timing of the internal
processor "Sys" clock. This clock is used to control state transitions in the read buffer, write
buffer, memory controller, and bus interface unit. This clock will either be at the same
frequency as the CPU execution rate clock, or at one-half that frequency, as selected during
reset.
processor "Sys" clock. This clock is used to control state transitions in the read buffer, write
buffer, memory controller, and bus interface unit. This clock will either be at the same
frequency as the CPU execution rate clock, or at one-half that frequency, as selected during
reset.
34
BusReq
BUSREQ
I
DMA Arbiter Bus Request: An input to the device which requests that the CPU tri-state its
bus interface signal so that they may be driven by an external master.
bus interface signal so that they may be driven by an external master.
39
BusGnt
BUSGNT
O
DMA Arbiter Bus Grant. An output from the CPU used to acknowledge that a BusReq has
been detected, and that the bus is relinquished to the external master.
been detected, and that the bus is relinquished to the external master.
19
CohReq
+5V FIXED
I
Coherent DMA Request. An input used by the external DMA controller to indicate that the
requested DMA operations could involve hardware cache coherency. This signal is the
Rsvd(0) of the R3051.
requested DMA operations could involve hardware cache coherency. This signal is the
Rsvd(0) of the R3051.
28 29
33
33
SBrCond(3:2)
BrCond(0)
BrCond(0)
+5V FIXED
I
Branch Condition Port: These external signals are internally connected to the CPU signals
CpCond(3:0). These signals can be used by the branch on co-processor condition instruc-
tions as input ports. There are two types of Branch Condition inputs: the SBrCond inputs
have special internal logic to synchronize the inputs, and thus may be driven by
asynchronous agents. The direct Branch Condition inputs must be driven synchronously.
Note that BrCond(1) is used by the internal FPA, and thus is not available on an external pin.
CpCond(3:0). These signals can be used by the branch on co-processor condition instruc-
tions as input ports. There are two types of Branch Condition inputs: the SBrCond inputs
have special internal logic to synchronize the inputs, and thus may be driven by
asynchronous agents. The direct Branch Condition inputs must be driven synchronously.
Note that BrCond(1) is used by the internal FPA, and thus is not available on an external pin.
37
BusError
+5V FIXED
I
Bus Error: Input to the bus interface unit to terminate a bus transaction due to an external
bus error. This signal is only sampled during read and write operations. If the bus transaction
is a read operation, then the CPU will take a bus error exception.
bus error. This signal is only sampled during read and write operations. If the bus transaction
is a read operation, then the CPU will take a bus error exception.
20 23
24
24
Int(5:3)
INT(5:3)
I
Processor Interrupt: During normal operation, these signals are logically the same as the
Int(5:0) Slnt(2:0) signals of the R3000. During processor reset, these signals perform mode
initialization of the CPU, but in a different (simpler) fashion than the interrupt signals of the
R3000.
Int(5:0) Slnt(2:0) signals of the R3000. During processor reset, these signals perform mode
initialization of the CPU, but in a different (simpler) fashion than the interrupt signals of the
R3000.
There are two types of interrupt inputs: the Slnt inputs are internally synchronized by the
processor, and may be driven by an asynchronous external agent. The direct interrupt inputs
are not internally synchronized, and thus must be externally synchronized to the CPU. The
direct interrupt inputs have one cycle lower latency than the synchronized interrupts. Note
that the interrupt used by the on-chip FPA will not be monitored externally.
processor, and may be driven by an asynchronous external agent. The direct interrupt inputs
are not internally synchronized, and thus must be externally synchronized to the CPU. The
direct interrupt inputs have one cycle lower latency than the synchronized interrupts. Note
that the interrupt used by the on-chip FPA will not be monitored externally.
4
ClkIn
CLKIN
I
Master Clock Input: This input clock can be provided at the execution frequency of the CPU
(1x clock mode) or at twice that frequency (2x clock mode), as selected at reset.
(1x clock mode) or at twice that frequency (2x clock mode), as selected at reset.
38
Reset
RESET0
I
Master Processor Reset: This signal initializes the CPU. Mode selection is performed during
the last cycle of Reset.
the last cycle of Reset.
15:18
Rsvd(4:1)
N.C.
I/O
Not used
– 27 –
<Controller : GT32011>
Pin configurations
GT-32011
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
80
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
160
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
OEMAD*
AD(21)
VSS
VDD
AD(27)
VSS
AD(30)
AD(31)
VDATA
VCLKIN
PA GESYNC*
LINESYNC*
ROMOE*
ROMCS(0)*
ROMCS(1)*
VSS
VDD
RAS(1)*
RAS(0)*
TEST
AD
(1
4
)
AD
(1
3
)
AD
(1
2
)
AD
(1
1
)
AD
(1
0
)
VDD
VSS
AD
(9
)
AD
(8
)
AD
(7
)
AD
(6
)
AD
(5
)
AD
(4
)
AD
(3
)
AD
(2
)
AD
(1
)
AD
(0
)
VDD
VSS
VSS
BU
R
S
T
*
ADDR(
3
)
ADDR(
2
)
AL
E
RD*
RE
SE
T
WR
*
DA
TA
EN*
BU
SG
N
T
*
AC
K
*
RDCE
N*
BUS
R
EQ*
IN
T*
EA
DOE*
E
A
DDI
R
*
EA
T
O
E
*
ED
T
A
C
K
*
ED
S
*
EB
REQ*
EBG
N
T
*
EAS*
EAACK*
PIO(0)
PIO(1)
PIO(2)
PIO(3)
PIO(4)
PIO(5)
CSELECTIN*
CINIT*
CSTROBE*
CRSTROBE
CBUSY
VDD
SYSCLK
VSS
CWSTROBE
CROE*
VDD
CAUTOFD*
CPERROR
CSELECT
CWOE*
CACK*
CFAULT*
POE
PSTROBE*
N.C.
N.C.
N.C.
N.C.
VDD
VSS
IOWAIT*
DMAACK*(1)*
IORD*
IOA1
ECS*
DMAACK*(0)*
DADR(
4
)
DADR(
5
)
DADR(
6
)
VS
S
VDD
DADR(
1
0
)
IO
DAT
A(3
)
VS
S
VDD
VDD
D
M
AR
E
Q
(0
)
IO
CS(0
)
IO
CS(1
)*
IOGP
CS
(0
)*
IOGP
CS
(1
)*
IO
BE
(1
)*
IO
BE
(0
)*
D
M
AR
E
Q
(1
)
DM
A
R
E
Q
(1
5
)
DM
A
R
E
Q
(1
4
)
DM
A
R
E
Q
(1
3
)
DM
A
R
E
Q
(1
2
)
DM
A
R
E
Q
(1
1
)
DM
A
R
E
Q
(1
0
)
D
M
AR
E
Q
(9
)
D
M
AR
E
Q
(8
)
D
M
AR
E
Q
(7
)
D
M
AR
E
Q
(6
)
D
M
AR
E
Q
(5
)
D
M
AR
E
Q
(4
)
IO
DAT
A(2
)
IO
DAT
A(1
)
IO
DAT
A(0
)
DADR(
9
)
DADR(
8
)
DADR(
7
)
DADR(
1
)
DADR(
2
)
DADR(
3
)
DADR(
0
)
CAS(3)*
RAS(2)*
CAS(2)*
CAS(1)*
DWR*
CAS(3)*
ROMCS(2)*
AD(29)
AD(28)
AD(26)
AD(25)
AD(24)
AD(23)
AD(24)
AD(23)
AD(22)
AD(20)
AD(19)
AD(18)
AD(17)
AD(16)
AD(15)
AD(19)
AD(18)
AD(17)
AD(16)
AD(15)
79
IOWR*
GT32011
DRAM
Non I/L
ROM
I/L or Non I/L
DRAM
Control
RAM
Control
CPU
Interface
CPU
IDT79R3081
External Agent or
Co-processor
Co-processor
DMA Interface
Interrupt
Controller
24bit
Timer
Counter
Programmable
I/O
3cha
nne
l D
M
M
A
System
Arbiter
Parallel
Port
Control
16bit
I/O Bus
Bidirectional
Centronics
IEEE1284
eg.
Control panel
Modes:
Compatible
Nible / Byte
Nible / Byte
ECP / EPP
Peripherals:
SCSI,Enet,
PCMCIA,etc.
16bit Parallel
Port
– 28 –
Pin Assignment Table
Pin No.
Pin Name
Signal Name
Pull Up/
Pull Dn
Type
Description
CPU Interface
1: 5
8: 17
139:142
144:149
152:158
8: 17
139:142
144:149
152:158
A/D[31:0]
A/D[0:31]
P.U.
I/O
Address/Date: Multiplexed address and data bus.
In the Address phase: A/D[31:4] are address, A/D[3:0] are Byte
Enable[3:0]. During Coprocessor Master cycles, A/D[3:2] contain address
bits 3 and 2, and not Byte Enables.
Enable[3:0]. During Coprocessor Master cycles, A/D[3:2] contain address
bits 3 and 2, and not Byte Enables.
22, 23
ADDR[3:2]
ADDR[3:2]
P.U.
I/O
Non Multiplexed Address: Connected to the CPU ADDR[3:2]. In DMA
cycles the GT-32011 drives these lines.
cycles the GT-32011 drives these lines.
21
BURST
∗
BURST
P.U.
I/O
Burst Transfer: Used only during read cycles, the BURST signal indicates
that the current bus read is requesting a block of four continuous words
from memory. The pin connects to the CPU’s BURST/WRNEAR
that the current bus read is requesting a block of four continuous words
from memory. The pin connects to the CPU’s BURST/WRNEAR
∗
signal. In
DMA cycles the GT-32011 drives this signal HIGH.
24
ALE
ALE
P.D.
I/O
Address Latch Enable: Used by the CPU to indicate that the A/D bus
contains valid address information for the bus transaction. During
Coprocessor DMA cycles, the GT-32011 asserts ALE to capture the
address supplied by the Coprocessor.
contains valid address information for the bus transaction. During
Coprocessor DMA cycles, the GT-32011 asserts ALE to capture the
address supplied by the Coprocessor.
5:6
SYSCLK
SYSCLK
I
System Clock: Connected directly to the CPU SYSCLK
∗
output.
25
RD
∗
RD
P.U.
I/O
Read: Indicates a read access by the CPU. In DMA cycles the GT-32011
drivers the signal HIGH.
drivers the signal HIGH.
26
WR
∗
WR
P.U.
I/O
Write: Indicates a write access by the CPU or the Coprocessor. In a non-
Coprocessor DMA cycle the GT-32011 drivers this signal HIGH.
Coprocessor DMA cycle the GT-32011 drivers this signal HIGH.
30
ACK
∗
ACK
O
Acknowledge: Indicates that the memory system has sufficiently
processed the bus transaction i.e. that the CPU may either terminate a
write cycle or process read data.
processed the bus transaction i.e. that the CPU may either terminate a
write cycle or process read data.
31
RDCEN
∗
RDCEN
O
Read Buffer Clock Enable: Indicates to the CPU that there is valid data on
the A/D bus.
the A/D bus.
32
BUSREQ
∗
BUREQ
O
Bus Request: The GT-32011 requests the CPU bus which is required for
I/O and Coprocessor DMA’s.
I/O and Coprocessor DMA’s.
28
BUSGNT
∗
BUSGNT
I
Bus Grand: Indicates that the CPU has relinquished the bus.
33
INT
∗
INT3710
O
Interrupt: "OR’s" the internal and external interrupt sources.
27
DATAEN
∗
DATAEN
I/O
Data Enable: indicates the data phase in CPU read cycles. In DMA the
GT-32011 asserts DATAEN when the ROM/DRAM drives data onto
A/D[31:0].
GT-32011 asserts DATAEN when the ROM/DRAM drives data onto
A/D[31:0].
ROM
129
132
133
132
133
ROMCS[2:0]
∗
ROMCS[2:0]
O
ROM Chip Select: Select one of the 3 ROM banks. They can be connected
to the ROM’s Chip Select or Output Enable. ROMCS[2] is connected to the
boot ROM, with a starting physical address 0x1fc00000.
to the ROM’s Chip Select or Output Enable. ROMCS[2] is connected to the
boot ROM, with a starting physical address 0x1fc00000.
134
ROMOE
∗
N.C.
O
ROM Output Enable: Asserted when there is an access to any of the ROM
banks. Used to output- enable the ROM data in systems where there is a
buffer between ROM and DRAM data bus; eg. when using an interleaved
ROM configuration.
banks. Used to output- enable the ROM data in systems where there is a
buffer between ROM and DRAM data bus; eg. when using an interleaved
ROM configuration.
DRAM
108:111
114:150
114:150
DADR[10:0]
DRAMAD[10:0]
O
DRAM Address: Multiplexed row and column address connected to the
DRAM address.
DRAM address.
121:123
RAS[2:0]
∗
RAS[2:1]
O
Row Address Select: Supports up to three banks of DRAM, connected to
the RAS inputs of the DRAMs.
the RAS inputs of the DRAMs.
124:127
CAS[3:0]
∗
CAS[2:0]
O
Column Address Select: Connects a CAS to each of the four bytes in
every bank.
every bank.
128
DWR
∗
DRAMWE
O
DRAM Write: Connects to the write pin of each of the DRAMs.
Coprocessor/External Agent Interface
39
EBREQ
∗
+5V FIXED
P.U.
I
Ext. Agent Bus Request: An Ext. Agent bus request to make system
resource access in master mode.
resource access in master mode.
40
EBGNT
∗
+5V FIXED
O
Ext. Agent Bus Grant: The GT-32011 asserts EBGNT
∗
to grant the CPU
bus to the Ext. Agent. Once the EBGNT
∗
is asserted, it remains so until
EBREQ
∗
is deasserted.
– 29 –
Pin No.
Pin Name
Signal Name
Pull Up/
Pull Dn
Type
Description
41
EAS
∗
+5V FIXED
P.U.
I/O
Ext. Agent Address Strobe:
Master Mode – The external agent indicates that it drives valid data on the
A/D bus.
A/D bus.
Slave mode – The GT-32011 indicates that it drives valid data on the A/D
bus.
bus.
42
EDS
∗
+5V FIXED
O
Ext. Agent Data Strobe:
Master mode – during Write indicates that there is valid data on the A/D
bus. During Read indicates a request for data.
bus. During Read indicates a request for data.
Slave mode – the GT-32011 drives EDS
∗
to indicate that it is ready to
accept data during reads or that valid data is available during writes ont he
A/D bus.
A/D bus.
37
EDTACK
∗
+5V FIXED
P.U.
I/O
Ext. Agent Data acknowledge:
Master mode – The GT-32011 asserts EDTACK
∗
to indicate that it is
receiving or driving the requested data to/from the A/D bus.
Slave mode – The Ext. Agent asserts EDTACK
∗
to signal that it has
supplied or received data on its bus.
43
EAACK
∗
+5V FIXED
O
Ext. Agent Address Acknowledge: The GT-32011 asserts EAACK
∗
one
clock after asserting ALE for the Ext. Agent. This insures that the Ext. Agent
continues driving the address until latched by the system.
continues driving the address until latched by the system.
42
ECS
∗
+5V FIXED
O
Ext. Agent Chip Select: When the CPU accesses the Ext. Agent, the
GT-32011 asserts ECS
GT-32011 asserts ECS
∗
. It is active one clock before GT-32011 asserts
EAS
∗
.
34
EADOE
∗
+5V FIXED
O
Ext. Agent A/D Output Enable: The GT-32011 asserts EADOE
∗
when the
Ext. Agent drives the address to the A/D bus, and in the data phases of the
Ext. Agent.
Ext. Agent.
35
EADDIR
∗
+5V FIXED
O
Ext. Agent A/D Direction: The GT-32011 asserts EADDIR
∗
(LOW) when
the Ext. Agent drives the A/D bus.
36
EATOE
∗
+5V FIXED
O
Ext. Agent Address To Output Enable: The GT-32011 asserts EATOE
∗
in the address phase of cycles in which the CPU accesses the Ext. Agent.
Buffer Control
159
OEMAD
∗
OEMAD
O
Output Enable between Memory and A/D: Output enable for the data
path transceiver, between the memory system and the A/D bus.
path transceiver, between the memory system and the A/D bus.
I/O Bus
89:100
104:107
104:107
IODATA[15:0]
IODATA[15:0]
P.U.
I/O
Input/Output Data: Bidirectional 16-bit I/O Data bus.
79
IORD
∗
IORD
O
Input/Output Read: Active during Read from an I/O device.
78
IOWR
∗
IOWR
O
Input/Output Write: Active during Write to an I/O device.
85, 86
IOCS[1:0]
∗
IOCS[1:0]
O
Input/Output Chip Selects: Chip selects for 8 bit I/O channels 0 and 1.
83, 84
IOGPCS[1:0]
∗
IOGPCS[1:0]
O
Input/Output Chip Selects: Chip select outputs for 16 bit I/O channels 0
and 1.
and 1.
87, 88
DMAREQ[1:0]
DMAREQ[1:0]
P.D.
I
DMA Request: Requesting DMA service on channels 0 and 1.
76, 77
DMAACK
∗
[1:0]
∗
DMAACK[1:0]
O
DMA acknowledge: Indicating that DMA access is granted on channels 0
and 1.
and 1.
80
IOA1
N.C.
O
Input/Output Address bit 1: Provides a half word (16 bit) address on the
I/O bus.
I/O bus.
81, 82
IOBE[1:0]
∗
N.C.
O
Input/Output Byte Enable: Indicates which byte data bus is valid on the 16
bit I/O bus.
bit I/O bus.
75
IOWAIT
∗
IOWAIT
P.U.
I
Input/Output Wait: Indicates to the GT-32011 that a transfer cycle on the
I/O bus needs to be extended.
I/O bus needs to be extended.
44
PIO0
IDREQ
P.U.
I/O
Input data request signal to I/O and peripheral controller
45
PIO1
ODREQ
P.U.
I/O
Output data request signal to I/O and peripheral controller
46
PIO2
EINTR11
P.U.
I/O
Interrupt signal from NIC Board
47
PIO3
EINTR12
P.U.
I/O
Interrupt signal from NIC Board
48
PIO4
SONIC_INT
P.U.
I/O
Interrupt signal from NIC Board
49
PIO5
PSYNCG10
P.U.
I/O
Vertical sync signal
– 30 –
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