Sharp AR-BD14 (serv.man5) Service Manual ▷ View online
Main
Sub
Item
Content
Adjustment
code
code
range
67
12
Flash program
writing.
writing.
• During program data reception
SIMULATION No.67-12
PRINTER FLASH MEMORY PROGRAM DATA
WRITING CHECK
WRITING CHECK
WRITING IN PROGRESS
• When the program data writing is completed (example)
SIMULATION No.67-12
PRINTER FLASH MEMORY PROGRAM DATA
WRITING CHECK
WRITING CHECK
PROGRAM DATA WRITING HAS COMPLETED
(1,234,567 BYTE)
(1,234,567 BYTE)
[PAUSE]KEY:END DISPLAY
[Content] The content of the flash of the PRT PWB is deleted. When data reception is
started, the screen of data reception is displayed. The program data sent
from PC is written into the flash. After completion of writing, the display of
completion is displayed.
from PC is written into the flash. After completion of writing, the display of
completion is displayed.
(a)
Operation/display
[PAUSE]:
The execution of the simulation is stopped and the screen returns to the
sub code input screen.
sub code input screen.
[CA] :
The execution is stopped and the simulation is terminated.
13
Flash program
data
comparison
check.
data
comparison
check.
• Initial screen
SIMULATION No.67-13
PRINTER FLASH MEMORY PROGRAM DATA
VERIFYING CHECK
VERIFYING CHECK
PLEASE SEND PROGRAM DATA FROM PERSONAL
COMPUTER.
COMPUTER.
• During program data reception
SIMULATION No.67-13
PRINTER FLASH MEMORY PROGRAM DATA
VERIFYING CHECK
VERIFYING CHECK
VERIFYING IN PROGRESS
• When the program data comparison is completed (example)
SIMULATION No.67-13
PRINTER FLASH MEMORY PROGRAM DATA
VERIFYING CHECK
VERIFYING CHECK
PROGRAM DATA VERIFYING OK
(1,234,567 BYTE)
(1,234,567 BYTE)
[PAUSE]KEY:END DISPLAY
[Content] The program data sent from PC and the flash content are compared. If all are
the same, "OK" is displayed. If not, "NG" is displayed.
(a)
Operation/display
[PAUSE]:
The execution of the simulation is stopped and the screen returns to the
sub code input screen.
sub code input screen.
[CA] :
The execution is stopped and the simulation is terminated.
– 23 –
Main
Sub
Item
Content
Adjustment
code
code
range
67
14
Flash program
data
write/comparison
check.
data
write/comparison
check.
• Initial screen
SIMULATION No.67-14
PRINTER FLASH MEMORY PROGRAM DATA
WRITING/VERIFYING CHECK
WRITING/VERIFYING CHECK
PLEASE SEND FONT DATA PROGRAM PERSONAL
COMPUTER.
COMPUTER.
• During program data reception
SIMULATION No.67-14
PRINTER FLASH MEMORY PROGRAM DATA
WRITING/VERIFYING CHECK
WRITING/VERIFYING CHECK
WRITING/VERIFYING IN PROGRESS
• When the program data write/comparison is completed (example)
SIMULATION No.67-14
PRINTER FLASH MEMORY PROGRAM DATA
WRITING/VERIFYING CHECK
WRITING/VERIFYING CHECK
PROGRAM DATA WRITING/VERIFYING OK
(1,234,567 BYTE)
(1,234,567 BYTE)
[PAUSE]KEY:END DISPLAY
[Content] The content of the flash of the PRT PWB is deleted.
Then the program data sent from PC is written into the flash and read and
compared. If all are the same, "OK" is displayed. If not, "NG" is displayed.
compared. If all are the same, "OK" is displayed. If not, "NG" is displayed.
(a)
Operation/display
[PAUSE]:
The execution of the simulation is stopped and the screen returns to the
sub code input screen.
sub code input screen.
[CA] :
The execution is stopped and the simulation is terminated.
15
Flash program
data sum check.
data sum check.
• During checking
SIMULATION No.67-15
PRINTER FLASH MEMORY PROGRAM DATA
SUM CHECK
SUM CHECK
CHECKING IN PROGRESS
• When checking is completed (example)
SIMULATION No.67-15
PRINTER FLASH MEMORY PROGRAM DATA
SUM CHECK
SUM CHECK
PROGRAM DATA SUM CHECK OK
(1,234,567 BYTE)
(1,234,567 BYTE)
[PAUSE]KEY:END DISPLAY
[Content] The flash content is read and check with check sum. If there is no abnor-
mality, "OK" is displayed. If there is any abnormality, "NG" is displayed.
(a)
Operation/display
[PAUSE]:
The execution of the simulation is stopped and the screen returns to the
sub code input screen.
sub code input screen.
[CA] :
The execution is stopped and the simulation is terminated.
– 24 –
[9] ELECTRICAL SECTION
(1) Block diagram
A. Basic Specifications
CPU:
IDT79R3081/50MHz
32bit microcontroller (below functions include)
MIPS R3000-core, 16KB INST, 4KB Data cache,
MMU,
MMU,
FPA (R3010A compatible)
Frequency = 50MHz (System clock = 25MHz)
Package = 84pin PLCC
ASIC:
GT-32011
DRAM controller (Max 40Mbyte area, 3 banks)
ROM controller (Max 20Mbyte area, 3 banks)
Video controller, Centronics controller,
Interrupt controller, General purpose I/O (6 port)
DMA counter 2ch. + 1ch for Centronics
24bit timer/counter, Package = 160pin PQFP
ASIC:
R3741A
P1284 Enhancement ASIC
EPLD Version (ALTERA EMP7064-15)
ASIC:
D9001-MF
EET, Toner save
Gate Array:
LZ95NA8
About 1000 gates
Memory:
Base ROM:
1MB max. Device = 256k
×
16bit,2pcs
4Mbit EPROM: HN27C4096G-10
Flash ROM:
8MB max. Device = 1M
×
16bit ,4pcs
16Mbit Flash: LH28F016SUT-10
Base DRAM:
16MB max. Device = 4M
×
4bit ,8pcs
16Mbit DRAM:uPD4217400 (Fast Page Mode)
NVRAM:
8K byte
Dallas DS1643-15
Nonvolatile Timekeeping RAM
package = 28pin DIP
Expansion
Memory:
Memory:
SIMM DRAM (Option)
Available in 16MB
72pin access time 60nsec
None parity
Peripherals:
Engine I/F
*
Serial I/F for command and status
*
Video I/F
Parallel I/F
*
IEEE-P1284
External I/O
*
LAN Card
Serial I/F
*
for only debug
Fl
as
h R
h R
O
M
E
x
te
nd
ed
R
O
ed
R
O
M
A
re
a
Ma
x
8
M
B
E
x
te
n
ded D
R
A
M A
rea
32bit Add.
bus
32bit Data
bus
32b
it Loc
al
B
u
s
16bit I/O Bus
GT-32011
8bit I/O Bus
NVRAM
8KB
R3741A
Bi-Parallel I/F
(IEEE1284)
Ho
s
s
t-
P
C
SW3
LED0~3
M
a
x202
De
bu
g CN
bu
g CN
RS-232C I/F
IC
U CN
Engine I/F
T
D
62
50
4
50
4
Ch-A
Ch-B
CPU
IDT79R3081
50MHz
OSC
50MHz
Add.Latch
373
ROM
1MB
DRAM
16MB
Data Buff.
245
LZ95NA8
G/A
QFP 100pin
S
e
rial
2c
h
h
ESC
C
A
M
D8
5C
30
5C
30
EET
D
9
001M
F
OSC
58.465MHz
Misc.
I/O
Logic
C
entr
o
Logi
c
ID
T29FC
T
52
B
B
T
LS
24
5,
24
5,
24
4
4
Centro
CN
External
CN1
Network
Card
(Option)
ASIC
ASIC
Not used in the
field service
field service
– 25 –
(2) General
The printer unit is composed of the printer PWB, the Centronics
connector PWB, and network I/F PWB, and the interface harness
which connects them.
connector PWB, and network I/F PWB, and the interface harness
which connects them.
The component sections of the printer PWB are described below.
A. CPU section
<CPU : R3081>
The CPU section of the printer controller is composed of two chips
which include the high-speed RICS microprocessor IDT79R3081 with
the cache memory and the peripheral circuits (for memory control,
image print control, various I/O control). The CPU’s operating fre-
quency is 50MHz, and the system clock is 25MHz.
which include the high-speed RICS microprocessor IDT79R3081 with
the cache memory and the peripheral circuits (for memory control,
image print control, various I/O control). The CPU’s operating fre-
quency is 50MHz, and the system clock is 25MHz.
Pin configurations
Pin description
Vss
Vcc
Vcc
Clkln
Rsvd(4)
Rsvd(3)
Rsvd(2)
Rsvd(1)
Rsvd(1)
CohReq
Int(5)
Vss
Vcc
Int(4)
Int(3)
Int(3)
SInt(2)
SInt(1)
SInt(0)
SInt(0)
SBrCond(3)
SBrCond(2)
SBrCond(2)
NC
Vss
Vcc
12
Vss
Vcc
A/D(14)
A/D(13)
Vcc
A/D(14)
A/D(13)
A/D(12)
A/D(11)
A/D(10)
A/D(10)
A/D(9)
Vcc
Vss
Vss
A/D(8)
A/D(7)
A/D(6)
A/D(6)
A/D(5)
A/D(4)
A/D(3)
Vss
Vcc
A/D(3)
Vss
Vcc
A/D(2)
A/D(1)
A/D(1)
A/D(0)
54
33
1 84
75
84-Pin MQUAD/PLCC
Top View
Pin No
Pin name
Signal name
I/O
Description
54:56
59:64
67:72
75:80
83:84
1: 4
7:11
59:64
67:72
75:80
83:84
1: 4
7:11
A/D(31:0)
A/D(31:0)
I/O
Address/Data: A 32-bit time multiplexed bus which indicates the desired address for a bus
transaction in one phase, and which is used to transmit data between the CPU and external
memory resources during the rest of the transfer.
transaction in one phase, and which is used to transmit data between the CPU and external
memory resources during the rest of the transfer.
Bus transactions on this bus are logically separated into two phases: during the first phase,
information about the transfer is presented to the memory system to be captured using the
ALE output. This information consists of:
information about the transfer is presented to the memory system to be captured using the
ALE output. This information consists of:
Address(31:4):
The high-order address for the transfer is presented on A/D(31:4).
BE(3:0):
These strobes indicate which bytes of the 32-bit bus will be involved
in the transfer, and are presented on A/D(3:0).
in the transfer, and are presented on A/D(3:0).
During write cycles, the bus contains the data to be stored and is driven from the internal
write buffer. On read cycles, the bus receives the data from the external resource, in either a
single data transaction or in a burst of four words, and places it into the on-chip read buffer.
write buffer. On read cycles, the bus receives the data from the external resource, in either a
single data transaction or in a burst of four words, and places it into the on-chip read buffer.
During cache coherency operations, the R3081 monitors the A/D bus at the start of a DMA
write to capture the write target address for potential data cache invalidates.
write to capture the write target address for potential data cache invalidates.
51
52
52
Addr(3:2)
ADDR(2:3)
O
Low Address (3:2) A 2-bit bus which indicates which word is currently expected by the
processor. Specifically, this two bit bus presents either the address bits for the single word to
be transferred (writes or single datum reads) or functions as a two bit counter starting at ‘00’
for burst read operations.
processor. Specifically, this two bit bus presents either the address bits for the single word to
be transferred (writes or single datum reads) or functions as a two bit counter starting at ‘00’
for burst read operations.
During cache coherency operations, the R3081 monitors the Addr bus at the start of a DMA
write to capture the write target address for potential data cache invalidates.
write to capture the write target address for potential data cache invalidates.
48
Diag(1)
N.C.
O
Not used
47
Diag(0)/
Ivd Req
Ivd Req
LAST
I/O
Diagnostic Pin 0. This output distinguishes cache misses due to instruction references from
those due to data references, and presents the remaining bit of the miss address. The value
output on this pin is also time multiplexed:
those due to data references, and presents the remaining bit of the miss address. The value
output on this pin is also time multiplexed:
I/D:
If the "Cached" Pin indicates a cache miss, then a high on this pin at
this time indicates an instruction reference, and a low indicates a data
reference. If the read is not due to a cache miss but rather an un-
cached reference, then this pin is undefined during this phase.
this time indicates an instruction reference, and a low indicates a data
reference. If the read is not due to a cache miss but rather an un-
cached reference, then this pin is undefined during this phase.
Miss Address (2): During the remainder of the read operation, this output presents ad-
dress bit (2) of the address the processor was attempting to reference
when the cache miss occurred. Regardless of whether a cache miss
is being processed, this pin reports the transfer address during this
time.
when the cache miss occurred. Regardless of whether a cache miss
is being processed, this pin reports the transfer address during this
time.
During write cycles, the value of this pin during both the address and data phases is
reserved.
reserved.
Invalidate Request. An input provided by an external DMA controller to request that the CPU
invalidate the Data Cache line corresponding to the current DMA write target address.
invalidate the Data Cache line corresponding to the current DMA write target address.
– 26 –
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