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LC-32X20E/S/RU, LC-37X20E/S/RU

5 – 9

22

SCLKOUT1

O

Bit clock #1 out. Used to receive input serial data.

23

SCLKOUT2

O

Bit clock #2 out. Used to clock output serial data.

15

SDA1

I/O

I2C port #1 data (always a slave)

17

SDA2

I/O

I2C port #2 data (always a slave)

11

SDIN1

I

Pull-down Serial data input 1

12

SDIN2

I

Pull-down Serial data input 2

13

SDIN3

I

Pull-down Serial data input 3

14

SDIN4

I

Pull-down Serial data input 4

27

SDOUT1

O

Serial data output 1

26

SDOUT2

O

Serial data output 2

25

SDOUT3

O

Serial data output 3

24

SDOUT4

O

Serial data output 4

2

VR_PLL

—

Internal regulator. This pin must not be used to power external devices.

3

XTALI

I

Oscillator input (connect to ground when not in use)

4

XTALO

O

Oscillator output

28

VR_DIG

---

Internal regulator. This pin must not be used to power external devices.

LC-32X20E/S/RU, LC-37X20E/S/RU

5 – 10

1

PVDD

—

PLL Power supply, 4.5V~5.5V.

2

RX0

I

Receiver Channel 0 (Internal biased pin. Internally biased at PVDD/2).

3

I2C

I

Control Mode Select.
“L”: 4-wire Serial, “H”: I2C Bus

4

RX1

I

Receiver Channel 1.

5

RX2

I

Receiver Channel 2.

6

RX3

I

Receiver Channel 3.

7

INT

O

Interrupt

8

DZF

O

Zero Input Detect.
When the input data of DAC follow total 8192 LRCK cycles with “0” input data, this pin goes to “H”. And 
when RSTN1 bit is “0”, PWDA bit is “0”, this pin goes to “H”

9

CDTO

O

Control Data Output in Serial Mode and I2C pin = “L”.

10

LRCKB

I/O

Channel Clock B

11

BICKB

I/O

Audio Serial Data Clock B

12

SDTOB

O

Audio Serial Data Output B

13

OLRCKA

I/O

Output Channel Clock A

14

ILRCKA

I/O

Input Channel Clock A

15

BICKA

I/O

Audio Serial Data Clock A

16

SDTOA

O

Audio Serial Data Output A

17

MCKO

O

Master Clock Output

18

TVDD

—

Output Buffer Power Supply, 2.7V~5.5V

19

DVSS

—

Digital Ground

20

DVDD

—

Digital Power Supply, 4.5V~5.5V

21

XTI

I

X’tal Input

22

XTO

O

X’tal Output

23

TX

O

Transmit Channel Output
When DIT bit = “0”, RX0~3 Through.
When DIT bit = “1”, Internal DIT Output.

24

MCLK2

I

Master Clock Input

25

PDN

I

Power-Down Mode & Reset
When “L”, the AK4683 is powered-down, all registers are reset. And then all digital output pins go “L”.
The AK4683 must be reset once upon power-up.

26

SDA

I/O

Control Data in Serial Mode and I2C pin = “H”.

27

SCL

I

Control Data Clock in Serial Mode and I2C pin = “H”.

28

CSN

I

Chip Select in Serial Mode and I2C pin = “L”.

29

SDTIA1

I

Audio Serial Data Input A1

30

SDTIA2

I

Audio Serial Data Input A2

31

SDTIA3

I

Audio Serial Data Input A3

32

SDTIB

I

Audio Serial Data Input B

33

HVDD

—

HP Power Supply, 4.5V~5.5V

34

HVSS

—

HP Ground

35

HPR

O

HP Rch Output.

36

HPL

O

HP Lch Output.

37

MUTET

—

HP Common Voltage Output

38

LOUT2

O

DAC2 Lch Positive Analog Output

39

ROUT2

O

DAC2 Rch Positive Analog Output

40

LOUT1

O

DAC1 Lch Positive Analog Output

41

ROUT1

O

DAC1 Rch Positive Analog Output

42

VCOM

—

DAC/ADC Common Voltage Output

43

AVDD2

—

DAC Power Supply, 4.5V~5.5V

44

AVSS2

—

DAC Ground

45

LISEL

O

Lch Feedback Resistor Output

46

LOPIN

O

Lch Feedback Resistor Input. 0.5 x AVDD1.

47

ROPIN

O

Rch Feedback Resistor Input. 0.5 x AVDD1.

48

RISEL

O

Rch Feedback Resistor Output

49

AVSS1

—

ADC Ground

50

AVDD1

—

ADC Power Supply, 4.5V~5.5V

51

LIN1

I

Lch Input 1

52

RIN1

I

Rch Input 1

53

LIN2

I

Lch Input 2

54

RIN2

I

Rch Input 2

55

LIN3

I

Lch Input 3

56

RIN3

I

Rch Input 3

LC-32X20E/S/RU, LC-37X20E/S/RU

5 – 11

57

LIN4

I

Lch Input 4

58

RIN4

I

Rch Input 4

59

LIN5

I

Lch Input 5

60

RIN5

I

Rch Input 5

61

LIN6

I

Lch Input 6

62

RIN6

I

Rch Input 6

63

PVSS

—

PLL Ground

64

R

—

External Resistor

LC-32X20E/S/RU, LC-37X20E/S/RU

5 – 12

System Switching Pins
30, 50, 70

DSDA0, DSDA1, DSDA2 

I/O

DDC I2C Data for respective port.

31, 51, 71

DSCL0, DSCL1, DSCL2 

I

DDC I2C Clock for respective port.

32, 52, 72

RPWR0, RPWR1, RPWR2

I

5V Port detection input for respective port.
Connect to 5V signal from HDMI input connector.

16, 36, 56 

HPD0, HDP1, HPD2 

O

Hot Plug Detect Output for respective port.
Connect to HOTPLUG of HDMI input connector. 

76

HPDIN

I

Hot Plug Detect Input.

78

TSCL

O

Master DDC I2C Clock (Open Drain Output) to HDMI receiver.
I2C transactions required for HDCP operation are performed over this I2C bus.

77

TSDA

I/O

Master DDC Data (Open drain output.) to HDMI receiver. I2C transactions required for 
HDCP operation are performed over this I2C bus.

Configuration Pins
79

I2CADDR/TPWR

I/O

I2C Slave Address input / Transmit Power Sense output pin.
When RESET# is low, this pin is used as an input to latch the I2C sub-address.
The level on this pin is latched when the RESET# pin transitions from low to high.
When RESET# is high, this pin is used as the TPWR output, indicating that the selected 
Rx-port has 5V present. When none of the Rx ports are selected, this signal is low.

35

I2CSEL/INT#

I/O

I2C Selection input / Interrupt output pin.
When RESET# is low, this pin is used as an input to latch the External Port Detection 
signal. The level on this pin is latched when the RESET# pin transitions from low to high.
When this pin is low during reset, the external pins EPSEL1/LSCL and EPSEL0/LSDA 
are used to select the Rx-port as EPSEL[1:0].
When this pin is high during reset, the internal local I2C register is used to select the Rx-
port.

75

RSVDL

I

Reserved for use by Silicon Image and must be tied low.

Control Pins
13

RESET#

I

Reset Pin (Active LOW). Certain configuration inputs are latched when RESET# transi-
tions from low to high.

15

LSCL/EPSEL1

I

Local I2C Clock / External Port Select 1. When I2CSEL is high, this becomes the Local 
I2C bus clock pin, LSCL. When I2CSEL is low, this becomes the external port select pin, 
EPSEL1. True open drain, so does not pull to ground if power not applied. An external 
pull-up is required.

14

LSDA/EPSEL0

I/O

Local I2C Data / External Port Select 0. When I2CSEL is high, this becomes the Local 
I2C bus data pin, LSDA. When I2CSEL is low, this becomes the external port select pin, 
EPSEL0. True open drain, so does not pull to ground if power not applied. An external 
pull-up is required.

CEC Pins
54

CEC_A

I/O

HDMI compliant CEC I/O used to interface to CEC devices.
CEC electrically compliant signal. This pin connects to the CEC signal of all HDMI con-
nectors in the system. As an input, the pad acts as a LVTTL Schmitt triggered input and 
is 5V tolerant. As an output, the pad acts as an NMOS driver with resistive pull-up. This 
pin has an internal pull-up resistor.

53

CEC_D

I/O

CEC interface to local system. True open-drain. An external pull-up is required.
This pin typically connects to the local CPU.

Differential Signal Data Pins
22

R0X0+

I

TMDS input Port 0 data pairs.

21

R0X0-

I

25

R0X1+

I

24

R0X1-

I

28

R0X2+

I

27

R0X2-

I

19

R0C+

I

TMDS input Port 0 clock pair.

18

R0C-

I

42

R1X0+

I

TMDS input Port 1 data pairs.

41

R1X0-

I

45

R1X1+

I

44

R1X1-

I

48

R1X2+

I

47

R1X2-

I

39

R1C+

I

TMDS input Port 1 clock pair.

38

R1C-

I