Sharp LC-37X20E Service Manual ▷ View online
LC-32X20E/S/RU, LC-37X20E/S/RU
5 – 5
2. Detailed ICs Information
2.1. IC402 (VHiBD9305AF-1Y)
2.1.1 Pin Connections and short description
2.2. IC506 (VHiMM3151XQ-1Q)
2.2.1 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
1
RT
—
Timing resistor external terminal
2
CT
—
Timing capacitor external terminal
3
ENB
I
Control input terminal
4
GD
O
Gate drive output terminal
5
VCC
—
Power terminal
6
GND
—
Ground terminal
7
COMP
O
Error amplifier output terminal
8
FB
I
Error amplifier inversion input terminal
Pin No.
Pin Name
I/O
Pin Function
69
C1
I
Chroma signal input
75
C2
I
1
C3
I
7
C4
I
70
S1
I
The terminal which detects the connection state of S-connector.
76
S2
I
2
S3
I
65
V1
I
Composite signal input.
71
V2
I
77
V3
I
3
V4
I
9
V5
I
15
V6
I
68
S2-1
I
The terminal which detects the aspect ratio information of S-connector.
74
S2-2
I
80
S2-3/ FS3
I
The terminal which detects the aspect ratio information of S-connector, or which detects
the voltage of FS pin of a scart connector.
the voltage of FS pin of a scart connector.
67
Y1
I
Luminance signal input.
73
Y2
I
79
Y3
I
5
Y4
I
14
ADR
I
Slave address select pin.
16
BIAS
I
BIAS
32
L13
I
The terminal which detects the number of scanning lines information on D-connector.
20
L11/ FS1
I
The terminal which detects the number of scanning lines information on D-connector, or
which detects the voltage of FS pin of a scart connector.
which detects the voltage of FS pin of a scart connector.
26
L12/ FS2
I
21
CY1
I
Component Y-signal input.
27
CY2
I
33
CY3
I
22
L21
I
The terminal which detects the I/P information of D-connector.
28
L22
I
34
L23
I
24
L31
I
The terminal which detects the aspect ratio information of D-connector.
30
L32
I
36
L33
I
23
PB1
I
Colour difference PB-signal input.
29
PB2
I
35
PB3
I
25
PR1
I
Colour difference PR-signal input.
31
PR2
I
37
PR3
I
38
SW1
I
The terminal which detects the connection state of D-connector.
40
SW2
I
42
SW3
I
45
SDA
I/O
Data I/O of I2C bus
46
SCL
I
Clock input of I2C bus
LC-32X20E/S/RU, LC-37X20E/S/RU
5 – 6
2.3. IC1301 (VHiYDA147SZ-1Y)
2.3.1 Block Diagram
49
DCOUT
O
DC output for S-terminal.
51
VOUT3
O
Monitor output (composit signal)
50
COUT3/VOUT6
O
Monitor output (Chroma or composite signal)
52
YOUT3/ VOUT5
O
Monitor output (Luminance or composite signal)
54
PROUT2
O
Colour difference PR-signal output.
58
PROUT1
O
55
PBOUT2/ COUT2
O
Colour difference PB-signal or chroma signal output.
59
PBOUT1/ COUT1
O
56
CYOUT2/ YOUT2/ VOUT2
O
Colour difference signal, Luminance or composite signal output.
60
CYOUT1/ YOUT1/ VOUT1
O
64
O1
O
Output port.
66
O2
O
72
O3
O
78
O4
O
53, 57
VDD1
—
Power supply (+9V)
8, 47
VDD2
—
Power supply (+5V)
18, 44, 62
GND
—
Ground
4, 6, 10, 11, 12, 13,
17, 19, 39, 41, 43,
48, 61, 63
17, 19, 39, 41, 43,
48, 61, 63
NC
—
Unconnected pins.
Pin No.
Pin Name
I/O
Pin Function
LC-32X20E/S/RU, LC-37X20E/S/RU
5 – 7
2.3.2 Pin Connections and short description
2.4. IC1402 (VHiR2S15502-1Y)
2.4.1 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
1, 2, 12, 25, 35, 36
NC
—
No connection
3
PVDDREG
—
Power terminal for regulator (PVDD)
4
AVDD
—
Output terminal for 3.3V regulator
5
INLP
I
Analog input terminal (Lch+)
6
INLM
I
Analog input terminal (Lch-)
7
VREF
VREF terminal
8
INRM
I
Analog input terminal (Rch-)
9
INRP
I
Analog input terminal (Rch+)
10
AVSS
—
GND terminal for analog
11
PLIMIT
I
Power limit setting terminal
13, 14
PVDDPR
—
Power terminal for digital amplifier output (Rch+)
15, 16, 17
OUTPR
O
Digital amplifier output terminal (Rch+)
18, 19
PVSSR
—
Ground terminal for digital amplifier output (Rch)
20, 21, 22
OUTMR
O
Digital amplifier output terminal (Rch-)
23, 24
PVDDMR
—
Power terminal for digital amplifier output (Rch-)
26
SLEEPN
I
Sleep control terminal
27
PROTN
O
Error flag output terminal
28
MUTEN
I
Mute control terminal
29
CKOUT
O
Clock output terminal for synchronization
30
CKIN
I
External clock input terminal
31
NCDRC0
I
Non-clip/DRC1/DRC2 mode selection terminal 0
32
NCDRC1
I
Non-clip/DRC1/DRC2 mode selection terminal 1
33
GAIN0
I
GAIN setting terminal 0
34
GAIN1
I
GAIN setting terminal 1
37, 38
PVDDML
—
Power terminal for digital amplifier output (Lch-)
39, 40, 41
OUTML
O
Digital amplifier output terminal (Lch-)
42, 43
PVSSL
—
Ground terminal for digital amplifier output (Lch)
44, 45, 46
OUTPL
O
Digital amplifier output terminal (Lch+)
47, 48
PVDDPL
—
Power terminal for digital amplifier output (Lch+)
Pin No.
Pin Name
I/O
Pin Function
1
AVSS
—
0V Power Supply for Analog Core
2
AVDD
—
3.3V Power Supply for Analog Core
3
SIF
I
Sound IF Input
4
VREF1
—
ADC Voltage Reference 1
5
VREF2
—
ADC Voltage Reference 2
6
TEST
I
Test pin
7
XI
I
Crystal Oscillator Input
8
XO
O
Crystal Oscillator Output
9
IVDD
—
3.3V Power Supply for I/O Buffer
10
IVSS
—
0V Power Supply for I/O Buffer
11
DVSS
—
0V Power Supply for Logic Core
12
DVDD
—
1.5V Power Supply for Logic Core
13
DACCLK
I/O
DAC Clock
14
BCK
I/O
Bit Clock
15
LRCK
I/O
LR Clock
16
SD0
O
Digital Output for External DAC
17
SDI
I
Digital Input for Internal DAC
18
SDA
I/O
I2C bus Serial Data
19
SCL
I
I2C bus Serial Clock
20
STATUS
I/O
PLL Setting / Status Signal
21
RESET
I
Hardware Reset (Active low)
22
ROUT
O
Rch Analog Output
23
VCOM
—
DAC Voltage Reference
24
LOUT
O
Lch Analog Output
LC-32X20E/S/RU, LC-37X20E/S/RU
5 – 8
2.5. IC1403 (VHiTAS3108D-1Y)
2.5.1 Block Diagram
2.5.2 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
38
AVDD
—
Analog power-supply input (3.3V)
1
AVSS
—
Analog ground
7
CS0
I
Pull-down Chip select
9, 30
DVDD
—
Digital power-supply input (3.3V)
10, 29
DVSS
—
Digital ground
8
GPIO
I/O
Pull-up GPIO control pin (user programmable)
19
LRCLK
I/O
Pull-down Sample rate clock (fS) input or output
5
MCLKIN
I
Master clock input (Connect to ground when not in use.)
21
MCLKO
O
Master clock output
6
MICROCLK_DIV
I
Pull-down Internal microprocessor clock divide control
31
PDN
I
Pull-up Powers down all logic and stops all clocks, active-low. Coefficient memory remains stable
through power-down cycle.
through power-down cycle.
34
PLL0
I
Pull-up PLL control 0
35
PLL1
I
Pull-down PLL control 1
36
PLL2
I
Pull-down PLL control 2
33, 37
RESERVED
—
Connect to ground
32
RESET
I
Pull-up Reset, active-low
16
SCL1
I/O
I2C port #1 clock (always a slave)
18
SCL2
I/O
I2C port #2 clock (always a slave)
20
SCLKIN
I
Pull-down Bit clock input
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