DOWNLOAD Sharp LC-37X20E Service Manual ↓ Size: 2.22 MB | Pages: 40 in PDF or view online for FREE

Name: Sharp LC-37X20E
Brand: Sharp
SKU: 68098
Rating: 4 (1 reviews)

Model: LC-37X20E
Pages: 40
Size: 2.22 MB
Type: PDF
Document: Service Manual
Brand: Sharp
Device: TV / LCD / Major IC Information
File: lc-37x20e.pdf
Date: 2018-11-20

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LC-32X20E/S/RU, LC-37X20E/S/RU
5 – 25
D12
POD_CE1
O
Card enable.
E12
POD_CTX
O
POD OOB TX Gapped Symbol clock.
A11
POD_DRX
O
POD OOB RX data.
B11
POD_CD1
I
Card Detect.
C11
POD_IREQ
I
Ready/IRQ
D11
POD_CRX
O
POD OOB RX Gapped clock.
E11
POD_RESET
O
POD Card reset signal.
A10
POD_QTX
I
POD OOB TX Q Channel.
B10
POD_VS1
I
Card voltage Sense.
C10
POD_ETX
I
POD OOB TX enable.
D10
POD_CD2
I
Card Detect.
E10
POD_CE2
O
Card enable.
A9
POD_VPP_EN
O
Slot VPP enable.
B9
POD_OVERLOAD
I
Current overload detect.
C9
POD_VPP_EN#
O
Slot VPP enable.
D9
POD_VCC_EN#
O
Slot VCC enable.
E9
POD_VCC_EN
O
Slot VCC enable.
A8
POD_A9
O
POD Host interface address bit 9.
B8
POD_A8
O
POD Host interface address bit 8.
C8
POD_A7
I/O
POD Host interface address bit 7.
D8
POD_A6
I/O
POD Host interface address bit 6.
D7
POD_A5
I/O
POD Host interface address bit 5.
C7
POD_A4
O
POD Host interface address bit 4.

VDA Interface
AP13, AN13, AM13, AL13, 
AK13, AP14, AN14, AM14, 
AL14, AK14
VDA_R[9:0]
I
Video input, R channel. (Not used)
AP15, AN15, AM15, AL15, 
AK15, AM16, AL16, AK16, 
AP17, AN17
VDA_B[9:0]
I
Video input, B channel. (Not used)
AM17, AL17, AK17, AP18, 
AN18, AM18, AL18, AK18, 
AP19, AN19
VDA_G[9:0]
I
Video input, G channel. (Not used)
AP16
VDA_CLK
I
Video input, Clock. (Not used)
AM19
VDA_VS
I
Video input, Vertical sync. (Not used)
AL19
VDA_HS
I
Video input, Horizontal sync. (Not used)
AK19
VDA_DE
I
Video input, Data enable. (Not used)

VDB Interface, EJTAG, IDE and POD2 share with VDB
AK20
VDB_DE
I/O
Video input/output; data enable;
IDE: IDE bus interrupt.
EJTAG: NOP
POD2: POD_CE2B#, the second POD Card enable.
AL20
VDB_HS
I/O
Video input/output; Horizontal sync;
IDE: PDLAGCBLID, Passed diagnostics, cable assembly type identifier.
EJTAG: TDI2, TDI EJTAG input of slave CPU.
POD2: POD_A_B5, the second POD host interface address bit 5.
AM20
VDB_VS
I/O
Video input/output; Vertical sync;
IDE: DMAREQ, IDE bus DMA request.
EJTAG: NOP
POD2: POD_A_B4, the second POD host interface address bit 4.
AN20
VDB_G0
I/O
Video input/output; Green channel bit 0;
IDE: IDE data bus bit 0.
EJTAG: TDO2, TDO EJTAG input of slave CPU CPU.
POD2: POD_A_B6, the second POD host interface address bit 6.
AP20
VDB_G1
I/O
Video input/output; Green channel bit 1;
IDE: IDE data bus bit 1.
EJTAG: TMS2, TMS EJTAG input of slave CPU CPU.
POD2: POD_A_B7, the second POD host interface address bit 7.
AK21
VDB_G2
I/O
Video input/output; Green channel bit 2;
IDE: IDE data bus bit 2.
EJTAG: TCK2, TCK EJTAG input of slave CPU CPU.
POD2: POD_A_B8, the second POD host interface address bit 8.
AL21
VDB_G3
I/O
Video input/output; Green channel bit 3;
IDE: IDE data bus bit 3.
EJTAG: DCLK EJTAG output of both CPU CPUs.
POD2: POD_A_B8, the second POD host interface address bit 9.
Ref No.
Pin Name
I/O
Pin Function

LC-32X20E/S/RU, LC-37X20E/S/RU
5 – 26
AM21
VDB_G4
I/O
Video input/output; Green channel bit 4;
IDE: IDE data bus bit 4.
EJTAG: TPC[0], output as EJTAG PC Trace bus, bit 0.
POD2: POD_CD2B#, the second POD interface card detect.
AN21
VDB_G5
I/O
Video input/output; Green channel bit 5;
IDE: IDE data bus bit 5.
EJTAG: TPC[1], output as EJTAG PC Trace bus, bit 1.
POD2: POD_CD1B#, the second POD interface card detect.
AP21
VDB_G6
I/O
Video input/output; Green channel bit 6;
IDE: IDE data bus bit 6.
EJTAG: TPC[2], output as EJTAG PC Trace bus, bit 2.
POD2: POD_RSTB, the second POD host interface reset.
AK22
VDB_G7
I/O
Video input/output; Green channel bit 7;
IDE: IDE data bus bit 7.
EJTAG: TPC[3], output as EJTAG PC Trace bus, bit 3.
POD3: POD_A_B14, the second POD host interface address bit 14.
AL22
VDB_G8
I/O
Video input/output; Green channel bit 8;
IDE: IDE data bus bit 8.
EJTAG: TPC[4], output as EJTAG PC Trace bus, bit 4.
POD3: POD2_TS2_D0, the second POD_TS2 data[0].
AM22
VDB_G9
I/O
Video input/output; Green channel bit 9;
IDE: IDE data bus bit 9.
EJTAG: TPC[5], output as EJTAG PC Trace bus, bit 5.
POD3: POD2_TS2_D2, the second POD_TS2 data[1].
AN22
VDB_B0
I/O
Video input/output; Blue channel bit 0;
IDE: IDE data bus bit 10.
EJTAG: TPC[6], output as EJTAG PC Trace bus, bit 6.
POD3: POD2_TS2_D2, the second POD_TS2 data[2].
AP22
VDB_B1
I/O
Video input/output; Blue channel bit 1;
IDE: IDE data bus bit 11.
EJTAG: TPC[7], output as EJTAG PC Trace bus, bit 7.
POD3: POD2_TS2_D3, the second POD_TS2 data[3].
AK23
VDB_B2
I/O
Video input/output; Blue channel bit 2;
IDE: IDE data bus bit 12.
EJTAG: PCST[0], output as EJTAG PC Trace bus, bit 0.
POD3: POD2_TS2_D4, the second POD_TS2 data[4].
AL23
VDB_B3
I/O
Video input/output; Blue channel bit 3;
IDE: IDE data bus bit 13.
EJTAG: PCST[1], output as EJTAG PC Trace bus, bit 1.
POD3: POD2_TS2_D5, the second POD_TS2 data[5].
AM23
VDB_B4
I/O
Video input/output; Blue channel bit 4;
IDE: IDE data bus bit 14.
EJTAG: PCST[2], output as EJTAG PC Trace bus, bit 2.
POD3: POD2_TS2_D6, the second POD_TS2 data[6].
AP23
VDB_CLK
I/O
Video input/output; Clock;
IDE: IDE data bus IO access complete.
EJTAG: NOP
POD3: POD_CE1B#, the second POD interface card enable.
AK24
VDB_B5
I/O
Video input/output; Blue channel bit 5;
IDE: IDE data bus bit 15.
EJTAG: PCST[3], output as EJTAG PC Trace bus, bit 3.
POD3: POD2_TS2_D7, the second POD_TS2 data[7].
AL24
VDB_B6
I/O
Video input/output; Blue channel bit 6;
IDE: Chip Select 0 for IDE interface.
EJTAG: PCST[4], output as EJTAG PC Trace bus, bit 4.
POD3: POD2_TS2_DEN, the second POD_TS2 data valid.
AM24
VDB_B7
I/O
Video input/output; Blue channel bit 7;
IDE: Chip Select 1 for IDE interface.
EJTAG: PCST[5], output as EJTAG PC Trace bus, bit 5.
POD2: POD2_TS2_CLK, the second POD_TS2 clock.
AN24
VDB_B8
I/O
Video input/output; Blue channel bit 8;
IDE: IDE address bus bit 0.
EJTAG: PCST[6], output as EJTAG PC Trace bus, bit 6.
POD2: POD2_TS2_SYNC, the second POD_TS2 SYNC.
AP24
VDB_B9
I/O
Video input/output; Blue channel bit 9;
IDE: IDE address bus bit 1.
EJTAG: PCST[7], output as EJTAG PC Trace bus, bit 7.
POD2: POD2_TS1_D0, the second POD_TS1 data[0].
Ref No.
Pin Name
I/O
Pin Function

LC-32X20E/S/RU, LC-37X20E/S/RU
5 – 27
AK25
VDB_R0
I/O
Video input/output; Red channel bit 0;
IDE: IDE address bus bit 2.
EJTAG: PCST[8], output as EJTAG PC Trace bus, bit 8.
POD2: POD2_TS1_D1, the second POD_TS1 data[1].
AL25
VDB_R1
I/O
Video input/output; Red channel bit 1;
IDE: IDE bus DMA acknowledge.
EJTAG: PCST[9], output as EJTAG PC Trace bus, bit 9.
POD2: POD2_TS1_D2, the second POD_TS1 data[2].
AM25
VDB_R2
I/O
Video input/output; Red channel bit 2;
IDE: IDE bus IO Read Strobe signal.
EJTAG: PCST[10], output as EJTAG PC Trace bus, bit 10.
POD2: POD2_TS1_D3, the second POD_TS1 data[3].
AN25
VDB_R3
I/O
Video input/output; Red channel bit 3;
IDE: IDE bus IO Write Strobe signal.
EJTAG: PCST[11], output as EJTAG PC Trace bus, bit 11.
POD2: POD2_TS1_D4, the second POD_TS1 data[4].
AP25
VDB_R4
I/O
Video input/output; Red channel bit 4;
IDE: NOP
EJTAG: 
S1=0, select DCLK/TPC[7:0]/PCST[11:0] of host CPU as output.
S1=1, select DCLK/TPC[7:0]/PCST[11:0] of slave CPU as output.
POD2: POD2_TS1_D5, the second POD_TS1 data[5].
AK26
VDB_R5
I/O
Video input/output; Red channel bit 5;
IDE: NOP
EJTAG: 
S1=0, two EJTAG are separately used.
S1=1, two EJTAG are used in a daisy chain style.
POD2: POD2_TS1_D6, the second POD_TS1 data[6].
AL26
VDB_R6
I/O
Video input/output; Red channel bit 6;
IDE: NOP
EJTAG: TDI1, TDI EJTAG input of host CPU CPU.
POD2: POD2_TS1_D7, the second POD_TS1 data[7].
AM26
VDB_R7
I/O
Video input/output; Red channel bit 7;
IDE: NOP
EJTAG: TDO1, TDO EJTAG input of host CPU CPU.
POD2: POD2_TS1_DEN, the second POD_TS1 data valid.
AN26
VDB_R8
I/O
Video input/output; Red channel bit 8;
IDE: NOP
EJTAG: TMS1, TMS EJTAG input of host CPU CPU.
POD2: POD2_TS1_CLK, the second POD_TS1 clock.
AP26
VDB_R9
I/O
Video input/output; Red channel bit 9;
IDE: NOP
EJTAG: TCK1, TCK EJTAG input of host CPU CPU.
POD2: POD2_TS1_SYNC, the second POD_TS1 SYNC.

IEEE1394 Interface, 8051 and 656 share with 1394
AM7, AL7, AK7, AK8, AL8, 
AM8, AK9, AL9
HSD[7:0]
I/O
1394: Parallel data.
Video 656 port; 656D[9:2], data[9:2]
8051: AD[7:0], AD bus.
AM9
HSDCLK
I/O
1394: clock.
Video 656 port; 656CLK, clock.
8051: RD, ALE, address latch enable.
AM10
HSDRW
I/O
1394: Not used.
Video 656 port; 656CHS, horizontal sync.
8051: RD, read signal, low active.
AL10
HSDSYNC
I/O
1394: Packet synchronization.
Video 656 port; 656VS, vertical sync.
8051: WR, write signal, low active.
AK10
HSDAV
I/O
1394: Not used.
Video 656 port; data[1].
8051: NOP
AM11
HSDEN
I/O
1394: Data valid.
Video 656 port; data[0].
8051: CS, chip select.

Transport Stream Interface
G4, G5, F1, F2, F3, F4, F5, 
E5
TS2_D[7:0]
I
Transport Stream 2, data bus.
G3
TS2_DEN
I
Transport Stream 2, data enable.
G2
TS2_SYNC
I
Transport Stream 2, sync signal.
G1
TS2_CLK
I
Transport Stream 2, clock.
Ref No.
Pin Name
I/O
Pin Function

LC-32X20E/S/RU, LC-37X20E/S/RU
5 – 28
J3, J2, J1, H1, H2, H3, H4, 
H5
TS1_D[7:0]
I
Transport Stream 1, data bus.
J4
TS1_DEN
I
Transport Stream 1, data enable.
J5
TS1_SYNC
I
Transport Stream 1, sync signal.
K1
TS1_CLK
I
Transport Stream 1, clock.

Memory Interface
AM30
DRVIMP
I
Driving strength impedance match reference pin.
AP29
MD0
I/O
Memory data bus.
AP30
MD1
I/O
Memory data bus.
AN30
MD2
I/O
Memory data bus.
AN31
MD3
I/O
Memory data bus.
AM33
DQM0
O
Memory data write mask enable for byte 0.
AM32
DQS0
I/O
Data strobe for memory data bus MD[7:0].
AL32
DQS0N
I/O
Data strobe for memory data bus MD[7:0].
AK30
MD4
I/O
Memory data bus.
AK31
MD5
I/O
Memory data bus.
AJ29
MD6
I/O
Memory data bus.
AJ30
MD7
I/O
Memory data bus.
AP32
MD8
I/O
Memory data bus.
AP33
MD9
I/O
Memory data bus.
AN33
MD10
I/O
Memory data bus.
AN34
MD11
I/O
Memory data bus.
AM34
DQM1
O
Memory data write mask enable for byte 1.
AL33
DQS1
I/O
Data strobe for memory data bus MD[15:8].
AL34
DQS1N
I/O
Data strobe for memory data bus MD[15:8].
AK33
MD12
I/O
Memory data bus.
AK34
MD13
I/O
Memory data bus.
AJ32
MD14
I/O
Memory data bus.
AJ33
MD15
I/O
Memory data bus.
AH33
MCLK0
O
Memory clock for MD[31:0].
AH34
MCLK0N
O
Memory clock for MD[31:0] - active LOW.
AG29
MD16
I/O
Memory data bus.
AG30
MD17
I/O
Memory data bus.
AF30
MD18
I/O
Memory data bus.
AF31
MD19
I/O
Memory data bus.
AE33
DQM2
O
Memory data write mask enable for byte 2.
AE32
DQS2
I/O
Data strobe for memory data bus MD[23:16].
AD32
DQS2N
I/O
Data strobe for memory data bus MD[23:16].
AC30
MD20
I/O
Memory data bus.
AC31
MD21
I/O
Memory data bus.
AB29
MD22
I/O
Memory data bus.
AB30
MD23
I/O
Memory data bus.
AG32
MD24
I/O
Memory data bus.
AG33
MD25
I/O
Memory data bus.
AF33
MD26
I/O
Memory data bus.
AF34
MD27
I/O
Memory data bus.
AE34
DQM3
O
Memory data write mask enable for byte 3.
AD33
DQS3
I/O
Data strobe for memory data bus MD[31:24].
AD34
DQS3N
I/O
Data strobe for memory data bus MD[31:24].
AC33
MD28
I/O
Memory data bus.
AC34
MD29
I/O
Memory data bus.
AB32
MD30
I/O
Memory data bus.
AB33
MD31
I/O
Memory data bus.
Y33
ODT
O
ODT
W34
CAS
O
Column Access Strobe of Port A or SCAN data input.
W33
RAS
O
Row Access Strobe of Port A or SCAN data input.
W31
WE
O
Write Enable of Port A or SCAN data input.
W30
CKE
O
Clock enable.
V34
CS0
O
Chip select for Ext Mem.
Y32
CS1
O
Chip select for Ext Mem.
U33
MAA10
O
Memory Address line of Port A or SCAN data input.
U32
BA1
O
Internal Bank Address Select for SDRAM.
U30
BA0
O
Internal Bank Address Select for SDRAM.
T34
MAA0
O
Memory Address line of Port A or SCAN data output.
T31
MAA1
O
Memory Address line of Port A or SCAN data output.
Ref No.
Pin Name
I/O
Pin Function

Display

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