Sharp LC-37X20E Service Manual ▷ View online
LC-32X20E/S/RU, LC-37X20E/S/RU
5 – 33
2.17. IC8451 (VHiS29GL128-1Q)
2.17.1 Block Diagram
33, 35, 37,
39, 54, 56,
58, 60, 82
39, 54, 56,
58, 60, 82
VSSQ
—
DQ Ground.
9
VDDL
—
DLL Power Supply: 1.8V
± 0.1V.
78
VSSL
—
DLL Ground.
5, 12, 18, 20
VDD
—
Power Supply: 1.8V
± 0.1V.
11. 17, 65, 69
VSS
—
Ground.
40
VREF
—
Reference voltage.
Pin No.
Pin Name
I/O
Pin Function
LC-32X20E/S/RU, LC-37X20E/S/RU
5 – 34
2.17.2 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
2
A22
I
23 Address inputs
15
A21
I
12
A20
I
11
A19
I
18
A18
I
19
A17
I
54
A16
I
3
A15
I
4
A14
I
5
A13
I
6
A12
I
7
A11
I
8
A10
I
9
A9
I
10
A8
I
20
A7
I
21
A6
I
22
A5
I
23
A4
I
24
A3
I
25
A2
I
26
A1
I
31
A0
I
51
DQ15/A-1
I/O
DQ15 (Data input/output, word mode), A-1(LSB Address input, byte mode)
49
DQ14
I/O
15 Data inputs/outputs
47
DQ13
I/O
45
DQ12
I/O
42
DQ11
I/O
40
DQ10
I/O
38
DQ9
I/O
36
DQ8
I/O
50
DQ7
I/O
48
DQ6
I/O
46
DQ5
I/O
44
DQ4
I/O
41
DQ3
I/O
39
DQ2
I/O
37
DQ1
I/O
35
DQ0
I/O
32
CE#
I
Chip Enable input
34
OE#
I
Output Enable input
13
WE#
I
Write Enable input
16
WP#/ACC
I
Hardware Write Protect input/Programming Acceleration input
14
RESET#
I
Hardware Reset Pin input
53
BYTE#
I
Selects 8-bit or 16-bit mode
17
RY/BY#
O
Ready/Busy output
43
VCC
—
3.0 volt-only single power supply
29
VIO
O
Output Buffer power.
33, 52
VSS
—
Device Ground
1, 27, 28, 30, 55, 56
N.C
—
Pin not Connected Internally.
LC-32X20E/S/RU, LC-37X20E/S/RU
5 – 35
2.18. IC8702 (RH-iXC0150WJQZY)
2.18.1 Block Diagram
2.18.2 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
1
VIN
I
Voltage input to VCXO. Zero to 3.3V signal which controls the VCXO frequency.
2
S0
I
Select pin 0. Internal pull-up resistor.
3
S1
I
Select pin 1. Internal pull-up resistor.
4
VDD
—
Connect to +3.3 V.
5
CLK1
O
Output clock 1. Weak internal pull-down when tri-state.
6
CLK2
O
Output clock 2. Weak internal pull-down when tri-state.
7
GND
—
Connect to ground.
8
X1
I
Crystal input. Connect this pin to a crystal.
9
X2
O
Crystal Output. Connect this pin to a crystal.
10
VDD
—
Connect to +3.3 V.
11
CLK3
O
Output clock 3. Weak internal pull-down when tri-state.
12
CLK4
O
Output clock 4. Weak internal pull-down when tri-state.
13
GND
—
Connect to ground.
14
PDTS
I
Power-down tri-state. Powers down entire chip and tri-states clock outputs when low. Internal pull-up resistor.
15
VDD
—
Connect to +3.3 V.
16
S2
I
Select pin 2. Internal pull-up resistor.
LC-32X20E/S/RU, LC-37X20E/S/RU
5 – 36
2.19. IC9101 (RH-iXC121WJN8Q)
2.19.1 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
1
D3.3V
—
Power supply(+3.3V)
2
N_CPLD_CS0
I
HiDTV CS0
⋅⋅⋅ Flash
3
XERE
I
HiDTV PCI_BUS OE#
4
ROM_CE
I
BOOT ROM CE input
5
N_CPLD_CS1
I
HiDTV CS1
⋅⋅⋅ CPLD
6
XEWE
I
HiDTV PCI_BUS WE#
7
NC
O
HiDTV PCI_BUS ACK#
8
D3.3V
—
Power supply (+3.3V)
9
FRDA_0
I/O
For HiDTV PCI_BUS DATA0/CPLD control
10
FRDA_1
I/O
For HiDTV PCI_BUS DATA1/CPLD control
11
FRDA_2
I/O
For HiDTV PCI_BUS DATA2/CPLD control
12
FRDA_3
I/O
For HiDTV PCI_BUS DATA3/CPLD control
13
FRDA_4
I/O
For HiDTV PCI_BUS DATA4/CPLD control
14
FRDA_5
I/O
For HiDTV PCI_BUS DATA5/CPLD control
15
FRDA_6
I/O
For HiDTV PCI_BUS DATA6/CPLD control
16
FRDA_7
I/O
For HiDTV PCI_BUS DATA7/CPLD control
17
FRAA_0
I
HiDTV PCI_BUS ADDRESS0
18
GND_B
—
Ground
19
FRAA_1
I
For HiDTV PCI_BUS ADDRESS1/CPLD control
20
FRAA_2
I
For HiDTV PCI_BUS ADDRESS2/CPLD control
21
FRAA_3
I
For HiDTV PCI_BUS ADDRESS3/CPLD control
22
FRAA_4
I
For HiDTV PCI_BUS ADDRESS4/CPLD control
23
FRAA_5
I
For HiDTV PCI_BUS ADDRESS5/CPLD control
24
N_CPLD2_CNF_DONE
I
FPGA Config
25
FRAA_6
I
For HiDTV PCI_BUS ADDRESS6/CPLD control
26
FRAA_22
I
HiDTV PCI_BUS ADDRESS22
27
FRAA_23
I
HiDTV PCI_BUS ADDRESS23
28
FRAA_24
I
HiDTV PCI_BUS ADDRESS24
29
GND_B
—
Ground
30
SBCLK_27M
I
HiDTV PCI_BUS CLOCK (27MHz)
31
3.3V_DPOW_DETECT
I
DPOW system 3.3V detection
32
NACE_N
I
NAND-FLASH CE output
33
CODEC_RST
O
CODEC reset
34
N_VCCH_RST
O
HiDTV standby reset
35
N_COLD_RST
O
HiDTV main reset
36
GND_B
—
Ground
37
D3.3V
—
Power supply (+3.3V)
38
CPLD_33M
I
System clock (33MHz)
39
N_FLS_RST
O
On-Board Flash reset
40
N_EXT_RST
O
External Flash reset
41
N_EXT_BOOT
I
Flash start-up discrimination (H = On-Board, L = External)
42
D3.3V
—
Power supply(+3.3V)
43
ROM_ADD22
O
On-Board/External Flash ADDRESS22
44
ROM_ADD23
O
On-Board/External Flash ADDRESS23
45
ROM_ADD24
O
On-Board/External Flash ADDRESS24
46
N_ROM_OE
O
On-Board/External Flash OE#
47
GND_B
—
Ground
48
N_ROM_WE
O
On-Board/External Flash WE#
49
N_EXT_CE
O
External Flash CE#
50
N_FLS_CS0
O
On-Board Flash CE0#
51
N_CPLD_INT0
O
HiDTV (Level interrupt, Active Low)
52
N_CPLD_INT1
O
SVP_WX (Level interrupt, Active Low)
53
DSP_RST
O
DSP reset
54
N_TUNER_INT
INT
CE6353 (Level interrupt, Active Low)
55
D3.3V
—
Power supply (+3.3V)
56
VON
O
Inverter ON/OFF control
57
PE
O
PANEL controller control signal
58
A_MUTE_ADIF
I
HDMI_MUTE control signal
59
BUS_SPLIT
O
Slow bus/video bus enable (Isplation supported)
60
I2C_EXT
O
I2C bus enable (Isolation supported)
61
STB
O
Inverter ON/OFF control
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