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LC-32X20E/S/RU, LC-37X20E/S/RU

5 – 21

1

INV

I

Inverting input of the error amplifier. The information on the output voltage of the PFC preregulator is fed 
into the pin through a resistor divider.

2

COMP

O

Output of the error amplifier. A compensation network is placed between this pin and INV (pin #1) to 
achieve stability of the voltage control loop and ensure high power factor and low THD.

3

MULT

I

Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor divider and 
provides the sinusoidal reference to the current loop.

4

CS

I

Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor, the result-
ing voltage is applied to this pin and compared with an internal sinusoidal-shaped reference, generated by 
the multiplier, to determine MOSFET’s turn-off.

5

ZCD

I

Boost inductor’s demagnetization sensing input for transition-mode operation. A negative-going edge trig-
gers MOSFET’s turn-on.

6

GND

—

Ground. Current return for both the signal part of the IC and the gate driver.

7

GD

O

Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s with a peak 
current of 600 mA source and 800 mA sink. The high-level voltage of this pin is clamped at about 12V to 
avoid excessive gate voltages in case the pin is supplied with a high Vcc.

8

VCC

—

Supply Voltage of both the signal part of the IC and the gate driver. The supply voltage upper limit is 
extended to 22V min. to provide more headroom for supply voltage changes.

5

DRAIN (D) Pin:

Power MOSFET drain connection. Provides internal operating current for both start-up 
and steady-state operation.

1

BYPASS (BP) Pin:

Connection point for a 0.1 

µF external bypass capacitor for the internally generated 5.8 

V supply.

4

ENABLE/UNDER-VOLTAGE (EN/UV) 
Pin:

This pin has dual functions: enable input and line under-voltage sense. During normal 
operation, switching of the power MOSFET is controlled by this pin. MOSFET switch-
ing is terminated when a current greater than 240 

µA is drawn from this pin. This pin 

also senses line under-voltage conditions through an external resistor connected to the 
DC line voltage. If there is no external resistor connected to this pin, TinySwitch-II 
detects its absence and disables the line undervoltage function.

2,3

SOURCE (S) Pin:

Control circuit common, internally connected to output MOSFET source.

LC-32X20E/S/RU, LC-37X20E/S/RU

5 – 22

DAC Interface
AD2

VDDZ_DAC

—

Digital power for DAC (+3.3V).

AD3

VSSZ_DAC

—

Digital ground for DAC.

AD1

DAC_VS

I/O

DAC vsync.

AE1

DAC_HS

I/O

DAC hsync.

AE2

DAC_CLK

I/O

DAC clock

AE4

DAC_DE

I/O

DAC DE

AE3

DAC_FLD

I/O

DAC field.

AA5

AVSS51

—

Analog ground for DAC (for bias circuit).

AB5

COMP

—

Bias for DAC coupling capacitor.

AB4

IRSET

I

Bias for DAC current source.

AB3

CVBS_B

I

DAC blue or PB (Not used).

AB2

ADVSS2

—

Analog ground for DAC (for DAC’s AVSS52).

AB1

ADVDD2

—

Analog power for DAC (+3.3V).

AC1

C_G

I

DAC green or Y (Not used).

AC2

AVSS50

—

Digital ground for DAC.

AC3

AVDD50

—

Analog power for DAC (+3.3V).

AC4

Y_R

I

DAC red or PR (Not used).

AC5

ADVSS2

—

Analog ground for DAC (for DAC’s AVSS52).

AD5

ADVDD2

—

Analog power for DAC (+3.3V).

AD4

VM

I

DAC VM

ADC Interface
N2

AVDD

—

ADC power +3.3V.

N3

VIN1

I

VRADC INPUT1 (Not used)

N4

VIN2

I

VRADC INPUT2 (Not used)

N5

AVSS

—

ADC ground.

USB Interface
R3

USB_PPON_PP

O

USB Power on control.

R2

USB_OC_PP

I

USB over current control.

P5

VDDA

—

Analog core +3.3V supply.

P4

DN

O

Negative output channel.

P3

DP

O

Positive output control.

P2

VSSA

—

Analog core ground.

P1

RREFEXT

—

External resistor connection for current reference.

R5

VSSP

—

PLL ground pin Double Bond.

R4

VDDP

—

PLL +1.2V supply Double Bond.

LVDS Interface
AJ5

LVDS_VSSP

—

LVDS PLL Ground.

AJ3

LVDS_VDDP

—

LVDS PLL Power supply (+3.3V).

AK5

LVDS_VSSO

—

LVDS Output buffer VSS (Long pad)

AK4

LVDS_VDDO

—

LVDS Output buffer VDD (+3.3V).

AK1

TF2P

O

LVDS Positive Output. (Not used)

AK2

TF2M

O

LVDS Negative Output. (Not used)

AL1

TE2P

O

LVDS Positive Output. (Not used)

AL2

TE2M

O

LVDS Negative Output. (Not used)

AM1

TD2P

O

LVDS Positive Output. (Not used)

AM2

TD2M

O

LVDS Negative Output. (Not used)

AN1

TCLK2P

O

LVDS Positive clock Output. (Not used)

AN2

TCLK2M

O

LVDS Negative clock Output. (Not used)

AP1

TC2P

O

LVDS Positive Output. (Not used)

AP2

TC2M

O

LVDS Negative Output. (Not used)

AM4

LVDS_VDDO

—

LVDS Output buffer VDD (+3.3V).

AP3

TB2P

O

LVDS Positive Output. (Not used)

AN3

TB2M

O

LVDS Negative Output. (Not used)

AP4

TA2P

O

LVDS Positive Output. (Not used)

AN4

TA2M

O

LVDS Negative Output. (Not used)

AJ6

LVDS_VSSO

—

LVDS Output buffer VSS.

AP5

TF1P

O

LVDS Positive Output. (Not used)

AN5

TF1M

O

LVDS Negative Output. (Not used)

AP6

TE1P

O

LVDS Positive Output. (Not used)

AN6

TE1M

O

LVDS Negative Output. (Not used)

LC-32X20E/S/RU, LC-37X20E/S/RU

5 – 23

AP7

TD1P

O

LVDS Positive Output. (Not used)

AN7

TD1M

O

LVDS Negative Output. (Not used)

AP8

TCLK1P

O

LVDS Positive clock Output. (Not used)

AN8

TCLK1M

O

LVDS Negative clock Output. (Not used)

AP9

TC1P

O

LVDS Positive Output. (Not used)

AN9

TC1M

O

LVDS Negative Output. (Not used)

AJ4

LVDS_VDDO

—

LVDS Output buffer VDD (+3.3V).

AP10

TB1P

O

LVDS Positive Output. (Not used)

AN10

TB1M

O

LVDS Negative Output. (Not used)

AP11

TA1P

O

LVDS Positive Output. (Not used)

AN11

TA1M

O

LVDS Negative Output. (Not used)

AL5

LVDS_VSSO

—

LVDS Output buffer VSS.

AM5

LVDS_VDDO

—

LVDS Output buffer VDD (+3.3V).

AL3

LVDS_VSSA

—

LVDS Analog VSS.

AL4

LVDS_VDDA

—

LVDS Analog VDD (+3.3V).

AK3

LVDS_VSSD

—

LVDS Digital VSS.

AM3

LVDS_VDDD

—

LVDS Digital VDD (+3.3V).

PLL Interface
B7

DVSS22

—

PLL ground related to DVDD22; supply for VCO circuit.

A7

DVDD22

—

PLL power= 1.2V; supply for VCO circuit.

A6

DVSS21

—

PLL ground related to DVDD21; supply for digital circuit.

B6

DVDD21

—

PLL power= 1.2V; supply for digital circuit.

C6

AVSS7

—

PLL ground related to AVDD7.

D6

MCLK2LF

—

Low pass filter for MCLK2PLL.

E6

AVDD7

—

PLL analog power= 3.3V; supply for MCLK2PLL.

D5

AVSS6

—

PLL ground related to AVSS6.

C5

MPEGCLK2LF

—

Low pass filter for MPEGCLK2PLL.

B5

AVDD6

—

PLL analog power= 3.3V; supply for MPEGCLK2PLL.

A5

AVSS5

—

PLL ground related to AVSS5.

A4

MPEGCLK1LF

—

Low pass filter for MPEGCLK1PLL.

B4

AVDD5

—

PLL analog power= 3.3V; supply for MPEGCLK1PLL.

C4

AVSS2

—

PLL ground related to AVSS2.

D4

PLF

—

Low pass filter for PCLKPLL.

C3

AVDD2

—

PLL analog power= 3.3V; supply for PCLKPLL.

B3

AVSS1

—

PLL ground related to AVSS1.

A3

MLF

—

Low pass filter for MCLKPLL.

A2

AVDD1

—

PLL analog power= 3.3V; supply for MCLKPLL.

B2

AVSS4

—

PLL ground related to AVSS4.

A1

IDELF

—

Low pass filter for IDECLKPLL.

B1

AVDD4

—

PLL analog power= 3.3V; supply for IDECLKPLL.

C1

AVDD3

—

PLL analog power= 3.3V; supply for CK48MPLL.

C2

CK48MLF

—

Low pass filter for CK48MPLL.

D3

AVSS3

—

PLL ground related to AVSS3.

D2

XTLI

—

24MHz_PLL crystal input.

D1

XTLO

—

24MHz_PLL crystal output.

E1

DVSS12

—

PLL ground related to DVDD12; supply for VCO circuit.

E2

DVDD12

—

PLL power= 1.2V; supply for VCO circuit.

E3

DVSS11

—

PLL ground related to DVDD11; supply for digital circuit.

E4

DVDD11

—

PLL power= 1.2V; supply for digital circuit.

FLASH Interface
E25

AD30_FRA14

I/O

Flash address 14/PCI AD bus bit 30.

D24

AD28_FRA12

I/O

Flash address 12/PCI AD bus bit 28.

E24

AD26_FRA10

I/O

Flash address 10/PCI AD bus bit 26.

A23

AD29_FRA13

I/O

Flash address 13/PCI AD bus bit 29.

B23

AD31_FRA15

I/O

Flash address 15/PCI AD bus bit 31.

D23

AD24_FRA8

I/O

Flash address 8/PCI AD bus bit 24.

E23

AD22_FRA6

I/O

Flash address 6/PCI AD bus bit 22.

A22

CBE3#_FRA19

I/O

Flash address 19/PCI CBE#[3].

B22

AD25_FRA9

I/O

Flash address 9/PCI AD bus bit 25.

C22

AD27_FRA11

I/O

Flash address 11/PCI AD bus bit 27.

D22

AD20_FRA4

O

Flash address 4/PCI AD bus bit 20/POD host interface Card access register selec-
tion.

E22

AD18_FRA2

O

Flash address 2/PCI AD bus bit 18/POD host interface Card I/O output enable.

A21

AD19_FRA3

O

Flash address 3/PCI AD bus bit 19/POD host interface Card I/O Write enable.

B21

AD21_FRA5

O

Flash address 5/PCI AD bus bit 21.

LC-32X20E/S/RU, LC-37X20E/S/RU

5 – 24

C21

AD23_FRA7

O

Flash address 7/PCI AD bus bit 23.

D21

AD16_FRA0

O

Flash address 0/PCI AD bus bit 16/POD host interface Card I/O output enable.

A20

IRDY_PCAS

I/O

PCI bus IRDY# signal/M68K CPU interface address strobe signal.

B20

CBE2#_FRA18

O

Flash address 18/PCI CBE#[2].

C20

AD17_FRA1

O

Flash address 1/PCI AD bus bit 17/POD host interface Card I/O Write enable.

A19

CBE1#_FRA17

O

Flash address 17/PCI CBE#[1].

E19

AD15_FRD15

I/O

Flash Data bus bit 15/PCI AD bus bit 15.

A18

AD7_FRD7

I/O

Flash Data bus 7/PCI AD bus bit 7.

B18

AD10_FRD10

I/O

Flash Data bus bit 10/PCI AD bus bit 10/POD host interface address bit 2.

C18

AD12_FRD12

I/O

Flash Data bus bit 12/PCI AD bus bit 12/POD host interface address bit 10.

D18

AD13_FRD13

I/O

Flash Data bus bit 13/PCI AD bus bit 13/POD host interface address bit 13.

E18

AD11_FRD11

I/O

Flash Data bus bit 11/PCI AD bus bit 11/POD host interface address bit 3.

A17

AD8_FRD8

I/O

Flash Data bus bit 8/PCI AD bus bit 8/POD host interface address bit 0.

B17

AD14_FRD14

I/O

Flash Data bus bit 14/PCI AD bus bit 14/POD host interface address bit 12.

C17

AD9_FRD9

I/O

Flash Data bus bit 9/PCI AD bus bit 9/POD host interface address bit 1.

D17

AD6_FRD6

I/O

Flash Data bus bit 6/PCI AD bus bit 6/POD host interface Data bus bit 6.

E17

CBE0#_FRA16

O

Flash address 16/PCI CBE#[0].

A16

AD5_FRD5

O

Flash Data bus bit 5/PCI AD bus bit 5/POD host interface Data bus bit 5.

B16

AD1_FRD1

I/O

Flash Data bus bit 1/PCI AD bus bit 1/POD host interface Data bus bit 1.

C16

AD3_FRD3

I/O

Flash Data bus bit 3/PCI AD bus bit 3/POD host interface Data bus bit 3.

D16

AD2_FRD2

I/O

Flash Data bus bit 2/PCI AD bus bit 2/POD host interface Data bus bit 2.

E16

AD4_FRD4

I/O

Flash Data bus bit 4/PCI AD bus bit 4/POD host interface Data bus bit 4.

E15

AD0_FRD0

I/O

Flash Data bus bit 0/PCI AD bus bit 0/POD host interface Data bus bit 0.

D15

FRA25

I/O

Flash address bit 25.

C15

FRA24

I/O

Flash address bit 24.

B15

FRA23

I/O

Flash address bit 23.

A15

FRA22

I/O

Flash address bit 22.

A14

FRA21

I/O

Flash address bit 21.

B14

FRA20

I/O

Flash address bit 20.

C14

GCS3

I/O

Flash chip select (0:Active).

D14

GCS2

I/O

Flash chip select (0:Active).

E14

GCS1

I/O

Flash chip select (0:Active).

E13

GCS0

I/O

Flash chip select (0:Active).

D13

BOOTCS

O

EPPROM chip select (0:Active).

C13

FWE#

O

Write enable signal of Flash Rom.

B13

FOE#

O

Read enable signal of Flash Rom.

A13

NAND_CE#

O

Chip select signal of NAND Flash Rom.

A12

NAND_RDY

I

Ready signal of NAND Flash Rom.

PCI Interface
A27

INTA

I

PCI interrupt A.

C25

INTB

I

PCI interrupt B.

B27

INTC

I

PCI interrupt C.

B25

INTD

I

PCI interrupt D.

D27

GNT0

O

PCI gnt signal. (Not used)

D26

GNT1

O

PCI gnt signal. (Not used)

E26

GNT2

O

PCI gnt signal. (Not used)

D25

GNT3

O

PCI gnt signal. (Not used)

C27

PCIRST#

O

PCIRSTN/68K clock output.

A25

PCICLK

O

PCI clock.

C24

REQ0

I

PCI req signal.

B24

REQ1

I

PCI req signal.

A24

REQ2

I

PCI req signal.

C23

REQ3

I

PCI req signal.

E21

FRAME#_SIZI

I/O

PCI bus FRAME# signal/68K Transfer size bit 1. (analog with Transfer size bit 0 to 
indicate the number byte to be transferred during a bus cycle M68K CPU bus.)

A20

IRDY_PCAS

I/O

PCI bus IRDY# signal/68K address strobe signal.

B20

CBE2#_FRA18

I/O

PCI bus CBE#[2]/Flash address bit 18.

D20

TRDY#_SIZ0

I/O

PCI bus TRDY# signal/68K Transfer size bit 0.

B19

SEPR#_DSACK1

I/O

PCI bus SERR# signal/68K Data and Size acknowledge signal bit 1.

C19

DVSEL_PCDS

I/O

PCI bus DEVSEL# signal/68K Data Strobe signal.

D19

PAR_DSACK0

I/O

PCI bus PAR signal/68K Data and Size acknowledge signal bit 0.

E20

STOP#_PCRW

I/O

Flash, 3.3V CMOS IF, 16mA output pad.

POD Interface
B12

POD_ITX

I

POD OOB TXI Channel.

C12

POD_WAIT

I

POD WAIT# signal to expand bus cycle.