Sharp LC-37X20E Service Manual ▷ View online
LC-32X20E/S/RU, LC-37X20E/S/RU
5 – 13
2.8. IC2002 (RH-iXB986WJN8Q)
2.8.1 Pin Connections and short description
62
R2X0+
I
TMDS input Port 2 data pairs.
61
R2X0-
I
65
R2X1+
I
64
R2X1-
I
68
R2X2+
I
67
R2X2-
I
59
R2C+
I
TMDS input Port 2 clock pair.
58
R2C-
I
7
TX0+
O
TMDS output data pairs.
8
TX0-
O
4
TX1+
O
5
TX1-
O
1
TX2+
O
2
TX2-
O
10
TXC+
O
TMDS output clock pair.
11
TXC-
O
12
EXT_SWING
I
Voltage Swing Adjust. A resistor tied from this pin to AVCC18 determines the amplitude
of the voltage swing. The recommended value is 750
of the voltage swing. The recommended value is 750
Ω.
Power and Ground Pins
23, 43, 55, 63
23, 43, 55, 63
AVCC33
—
Analog VCC. Connect to 3.3V supply.
6, 17, 29, 37, 49,
57, 69
57, 69
AVCC18
—
Analog VCC. Connect to 1.8V supply.
3, 9, 20, 26, 40,
46, 60, 66, 80
46, 60, 66, 80
AGND —
Analog
GND.
33, 73
DVCC18
—
Digital VCC. Connect to 1.8V supply.
34, 74
DGND
—
Digital GND.
Pin No.
Pin Name
I/O
Pin Function
1
SHIP_EN
O
SHIP (CSI) processing enabled/disabled selection signal
2
CS_CPLD
O
CPLD chip select
3
N_SRESET
O
Reset
4
PM_REQ
O
Request signal (Communication request at H)
5
IR_PASS
O
Remote control signal external through switching
6
Vc1
—
Internal voltage drop power terminal
7
X2
I
Sub clock (32.768kHz)
8
X1
O
Sub clock (32.768kHz)
9
N_RESET
I
System reset
10
OSC2
O
System clock (20.00MHz)
11
Vss
—
GND
12
OSC1
I
System clock (20.00MHz)
13
Vcc
—
Power supply (+3.3V)
14
N_NMI
I
For FLASH rewrite
15
WAKE_UP
I
For WAIT mode return
16
AC_DET
I
For instantaneous blackout detection
17
POW_SW
I
Power SW
18
FRAME
O
Panel controller control (50/60 setting)
19
ROMSEL0
O
For test pattern control
20
O_S_SET
O
Panel controller control ON/OFF
21
TEMP1
O
Panel controller control, temperature information 1
22
TEMP2
O
Panel controller control, temperature information 2
23
TEMP3
O
Panel controller control, temperature information 3
24
L_R
O
Panel controller control, flip horizontal
25
U_D
O
Panel controller control, flip vertical
26
UARXD_M
I
Serial for MAIN CPU communication (To TXD of MAIN CPU)
27
UATXD_M
O
Serial for MAIN CPU communication (To RXD of MAIN CPU)
28
TXD
O
For debugger (E8) connection
29
RXD
I
For debugger (E8) connection
30
SCLD
I
For debugger (E8) connection
31
BUSY
I
For debugger (E8) connection
32
LED_R
O
Power LED, red
33
LED_G
O
Power LED, green
34
LED_OPC
O
OPC LED
Pin No.
Pin Name
I/O
Pin Function
LC-32X20E/S/RU, LC-37X20E/S/RU
5 – 14
35
LED_SLEEP
O
SLEEP_LED
36
AV_LINK_O
O
AV_LINK output
37
ANT_POW
O
Antenna power control
38
EXE_LED
O
Microprocessor operation check LED
39
I2C_GATE
O
I2C bus SW
40
N_SYSRST_IN
I
SYSTEM RESET switch detection
41
RS_ON
O
RS232C power control
42
STB
O
Backlight control.
43
ERR_PNL
I
Lamp error detection (L: error)
44
AV_LINK_I
I
AV_LINK input
45
SYNC_DET
O
PC power management setting
46
VSYNC
I
VSYNC interrupt
47
CEC_O
O
CEC output
48
CEC_I
I
CEC input
49
RC
I
Remote control signal input.
50
I2C1_SCL
O
I2C CH1
51
I2C1_SDA
I/O
I2C CH1
52
W_PROT_M
O
EEP write protection
53
P16
—
For debugger (E8) connection
54
DVIA_DET
I
DVI analog detection (for PC power management)
55
MUTE_A_ALL
O
Audio mute
56
DET_6V
I
6V detection
57
DET_10V
I
10V detection
58
DET_PNL12V
I
Panel 12V detection
59
DER_D3V3
I
D3.3V detection
60
DET_3V3
I
3.3V detection
61
EU_POW
O
Digital system power control
62
LINK_POW
O
i.Link power control
63
PNL_POW
O
5V ON/OFF SW for panel
64
D_POW
O
Main power ON/OFF control
65
SMPOW
O
Power control
66
PSIZ_L
I
Panel size discrimination terminal (Mounting discrimination)
67
PSIZ_H
I
Panel size discrimination terminal (Mounting discrimination)
68
QSTEMP
I
Thermistor input (Panel temperature)
69
KEY1
I
Main unit key input 1
70
KEY2
I
Main unit key input 2
71
AREA1
I
Panel size discrimination terminal (Mounting discrimination)
72
PNL_TYPE
I
Panel manufacturer discrimination (Mounting discrimination)
73
OPC
I
Brightness sensor input
74
AFT/AGC
I
Tuner AFT/ACG input
75
Avss
—
Analog GND for A/D
76
LNBSHORT
I
Antenna short detection (Low: OK, High: NG)
77
Vref
—
A/D converter reference voltage
78
Avcc
—
Analog power for A/D
79
PNL_TYPE
I
Panel solution discrimination (Mounting discrimination)
80
ILLUMI
O
Illumination LED
Pin No.
Pin Name
I/O
Pin Function
LC-32X20E/S/RU, LC-37X20E/S/RU
5 – 15
2.9. IC3301 (RH-iXC010WJQZQ)
2.9.1 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
Ball Assignments for CPU Host Interface.
K20, K19, K18, K17, L20,
L19, L18, L17
K20, K19, K18, K17, L20,
L19, L18, L17
A_D[7:0]
I/O
Multiplexed address and data bus powered by VDDH/VSS.
M17, M18, M119, M20,
N20, N19, N18, N17
N20, N19, N18, N17
ADDR[7:0]
I
CPU Address. (Not connected)
J18
ALE
I
Address latch enables.
J19
WR#
I
CPU Write.
J20
RD#
I
CPU Read.
H17
SDA
I/O
I2C data.
H18
SCL
I
I2C clock.
J17
CPU_CS
I
UX chip select pin from MCU. Active Low.
Ball Assignments for Analog Support Interface.
W1
W1
XTALI
I
Input for Clock Synthesizer. Supports 24MHz Oscillator or crystal powered by ana-
log PLL.
log PLL.
Y1
XTALO
O
Used in conjunction with XTALI for 24MHz crystal output powered by analog PLL.
U2
MLF1
I
Low pass filter node for memory clock PLL powered by analog PLL.
R4
PLF2
I
Low pass filter node for video clock PLL powered by analog PLL.
Ball Assignments for Analog Input Interface.
Y4
Y4
CVBS1
I
Composite video input 1.
V6
Y_G1
I
Y input 1 of component or G input 1 of PC RGB.
W6
Y_G2
I
Y input 2 of component or G input 2 of PC RGB.
Y6
Y_G3
I
Y input 3 of component or G input 3 of PC RGB.
W2
CVBS_OUT1
I
CVBS Output 1. (Not connected)
V2
CVBS_OUT2
I
CVBS Output 2. (Not connected)
V9
C
I
C input of S-Video.
W9
PB_B1
I
PB input 1 of component.
Y9
PB_B2
I
PB input 2 of component.
Y10
PB_B3
I
PB input 3 of component.
Y8
PR_R1
I
PR input 1 of component.
W8
PR_R2
I
PR input 2 of component.
V8
PR_R3
I
PR input 3 of component.
W4, V4
FS2, FS1
I
SCART function select 2, 1.
U4, Y5
FB2, FB1
I
SCART FB input for Port 2, Port 1.
V10
AIN_H
I
Hsync input (PC RGB input)
U10
AIN_V
I
Vsync input (PC RGB input)
U8
PC_R
I
PC Red input.
Y7
PC_G
I
PC Green input.
W10
PC_B
I
PC Blue INPUT.
Ball Assignments for Capture Interface (TV & RGB).
U18, U19, U20, T20, T18,
T17, R19, R20
U18, U19, U20, T20, T18,
T17, R19, R20
DPB[15:8] (DP_B[15:8])
I/O
Digital input port [15:8] (Output reserved)
Y12, U13, V13, W13,
Y13, Y14, W14, V14,
U14, U15, V15, W15,
Y16, W16, V16, U16,
U17, V17, W17, Y17,
Y18, W18, V18, W19
Y13, Y14, W14, V14,
U14, U15, V15, W15,
Y16, W16, V16, U16,
U17, V17, W17, Y17,
Y18, W18, V18, W19
DPA[23:0] (DP_A[23:0])
I/O
Digital input/output port [23:0]
T19
DPB_CLK (CLK_B)
I/O
Digital port B CLK input/output. (Not connected)
Y15
DPA_CLK (CLK_A)
I/O
Digital port A CLK input/output.
W20
DPE_DE (DE_B)
I/O
DE input/output of Digital port B.
Y20
DPA_VS (VS_A)
I/O
Vsync input/output of Digital port A.
Y19
DPA_HS (HS_A)
I/O
Hsync input/output of Digital port A.
V20
DPB_VS (VS_B)
I/O
Vsync input/output of Digital port B. (Not connected)
V19
DPB_HS (HS_B)
I/O
Hsync input/output of Digital port B. (Not connected)
P19
HS
I/O
Hsync output for Digital port.
P17
VS
I/O
Vsync output for Digital port.
LC-32X20E/S/RU, LC-37X20E/S/RU
5 – 16
Pin No.
Pin Name
I/O
Pin Function
Ball Assignments for Frame Buffer Memory.
D3, C3, C2, C1, A1, A2,
A3, C5, A4, B5, A5, D6,
A7, B7, C7, D7, D8, C8,
B8, A8, D9, D10, C10,
B10, A10, A11, B11, C11,
D12, A13, B13, C13
D3, C3, C2, C1, A1, A2,
A3, C5, A4, B5, A5, D6,
A7, B7, C7, D7, D8, C8,
B8, A8, D9, D10, C10,
B10, A10, A11, B11, C11,
D12, A13, B13, C13
MD[31:0]
I/O
Memory data.
F1, F2, F3, F4, G4, G3,
G2, G1, H1, H2, H3, H4
G2, G1, H1, H2, H3, H4
MA[11-0]
I/O
Memory Address.
J2
RAS#
O
RAS# signal powered by VDDH/VSS.
J1
CAS#
O
CAS# signal powered by VDDH/VSS.
K1
WE#
O
WE#, write enable signal powered by VDDH/VSS.
J3
CS1#
O
Chip select 0 for the first 2/4 Mbyte of SGRAM/SDRAM powered by VDDH/VSS.
J4
CS0#
O
Chip select 1 for the first 2/4 Mbyte of SGRAM/SDRAM powered by VDDH/VSS.
D1
MCK0
O
Memory clock+.
E1
MCK0#
O
Memory clock-.
B1, A6, A9, A12
DQM[3:0]
O
Read/Write bytes enable powered by VDDH/VSS.
K2
CLKE
O
Memory clock enable.
B2, B6, B9, B12
DQS[3:0]
I/O
Memory data strobe.
E3
MVREF
—
DDR voltage reference.
K3
BA0
O
Bank address select.
K4
BA1
O
Bank address select.
Ball Assignments for Power and Ground.
C14, C15, D13, D14,
D15, E13, E14, E15,
G16, H5, H16, J5, J16,
K5, K16, R16, T14, T15
C14, C15, D13, D14,
D15, E13, E14, E15,
G16, H5, H16, J5, J16,
K5, K16, R16, T14, T15
VDDC
—
1.2V Digital core power.
E4, E7
VSSR
—
Digital memory reference Ground.
E2, E8
VDDR
—
2.5V Digital power for Memory.
B4, C4, D4, D5, D11, E5,
E6, E9, E10, E11, E12,
F5, G5
E6, E9, E10, E11, E12,
F5, G5
VDDM
—
2.5V Memory interface power. Output driver.
L16, M16, N16, P16, T12,
T13, R17, R18
T13, R17, R18
VDDH
—
3.3V Digital I/O power.
B3, C6, C9, C12, D2, H8,
H9, H10, H11, H12, H13,
J8, J9, J10, J11, J12, J13,
K8, K9, K10, K11,K12,
K13, L5, L8, L9, L10, L11,
L12, L13, M8, M9, M10,
M11, M12, M13, N8, N9,
N10, N11, N12, N13,
P18, T16, H20
H9, H10, H11, H12, H13,
J8, J9, J10, J11, J12, J13,
K8, K9, K10, K11,K12,
K13, L5, L8, L9, L10, L11,
L12, L13, M8, M9, M10,
M11, M12, M13, N8, N9,
N10, N11, N12, N13,
P18, T16, H20
VSS
—
Core and Digital IO ground.
W3
AVSS_BG_ASS
—
ADC ground.
V3
AVDD3_BG_ASS
—
3.3V ADC power.
T3
PAVDD1
—
3.3V power for MCLK PLL.
T2
PAVSS1
—
Ground for MCLK PLL.
R3
PAVSS2
—
Ground for PCLK PLL.
T4
PAVDD2
—
3.3V power for PCLK PLL.
U6, T8, U7, U5
AVDD_ADC[4, 3, 2, 1]
—
1.2V power for analog ADC.
T6, T9, T7, T5
AVSS_ADC[4, 3, 2, 1]
—
Ground for analog ADC.
U9, Y3
AVDD3_ADC[2, 1]
—
3.3V ADC power.
U3
AVDD3_OUTBUF
—
3.3V power for output buffer.
Y2
AVSS_OUTBUF
—
3.3V ground for output buffer.
C18, C19
LVDS_VSSO
—
LVDS out buffer ground.
C16
LVDS_VSSD
—
LVDS Digital ground.
E16
LVDS_VSSA
—
LVDS analog ground.
E18
LVDS_VSSP
—
LVDS PLL GND.
D18
LVDS_VDDP
—
LVDS PLL VDD.
E17
LVDS_VDDA
—
LVDS analog VDD.
D16
LVDS_VDDD
—
LVDS Digital VDD.
C17, D17
LVDS_VDDO
—
LVDS out buffer VDD.
P20
NC
—
Not connected.
U1
AVDDAPLL
—
1.2V analog PLL power.
V1
AVSSAPLL
—
1.2V analog GND.
R2
AVDDLLPLL
—
1.2V Line Lock PLL power.
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