DOWNLOAD Sharp LC-37X20E Service Manual ↓ Size: 2.22 MB | Pages: 40 in PDF or view online for FREE

LC-32X20E/S/RU, LC-37X20E/S/RU

5 – 29

T33

MAA2

O

Memory Address line of Port A or SCAN data output.

T30

MAA3

O

Memory Address line of Port A or SCAN data output.

R32

MAA4

O

Memory Address line of Port A or SCAN data output.

R30

MAA5

O

Memory Address line of Port A or SCAN data output.

R33

MAA6

O

Memory Address line of Port A or SCAN data output.

R29

MAA7

O

Memory Address line of Port A or SCAN data output.

P34

MAA11

O

Memory Address line of Port A or SCAN data output.

P33

MAA8

O

Memory Address line of Port A or SCAN data output.

P30

MAA9

O

Memory Address line of Port A or SCAN data output.

N29

MD32

I/O

Memory data bus.

N30

MD33

I/O

Memory data bus.

M30

MD34

I/O

Memory data bus.

M31

MD35

I/O

Memory data bus.

L33

DQM4

O

Memory data write mask enable for byte 4.

L32

DQS4

I/O

Data strobe for memory data bus MD[39:32].

K32

DQS4N

I/O

Data strobe for memory data bus MD[39:32].

J30

MD36

I/O

Memory data bus.

J31

MD37

I/O

Memory data bus.

H29

MD38

I/O

Memory data bus.

H30

MD39

I/O

Memory data bus.

N32

MD40

I/O

Memory data bus.

N33

MD41

I/O

Memory data bus.

M33

MD42

I/O

Memory data bus.

M34

MD43

I/O

Memory data bus.

L34

DQM5

O

Memory data write mask enable for byte 5.

K33

DQS5

I/O

Data strobe for memory data bus MD[47:40].

K34

DQS5N

I/O

Data strobe for memory data bus MD[47:40].

J33

MD44

I/O

Memory data bus.

J34

MD45

I/O

Memory data bus.

H32

MD46

I/O

Memory data bus.

H33

MD47

I/O

Memory data bus.

G33

MCLK1

O

Memory clock for MD[63:32].

G34

MCLK1N

O

Memory clock for MD[63:32] - active LOW.

F29

MD48

I/O

Memory data bus.

F30

MD49

I/O

Memory data bus.

E30

MD50

I/O

Memory data bus.

E31

MD51

I/O

Memory data bus.

D33

DQM6

O

Memory data write mask enable for byte 6.

D32

DQS6

I/O

Data strobe for memory data bus MD[55:48].

C32

DQS6N

I/O

Data strobe for memory data bus MD[55:48].

B30

MD52

I/O

Memory data bus.

B31

MD53

I/O

Memory data bus.

A29

MD54

I/O

Memory data bus.

A30

MD55

I/O

Memory data bus.

F32

MD56

I/O

Memory data bus.

F33

MD57

I/O

Memory data bus.

E33

MD58

I/O

Memory data bus.

E34

MD59

I/O

Memory data bus.

D34

DQM7

O

Memory data write mask enable for byte 7.

C33

DQS7

I/O

Data strobe for memory data bus MD[63:56].

C34

DQS7N

I/O

Data strobe for memory data bus MD[63:56].

B33

MD60

I/O

Memory data bus.

B34

MD61

I/O

Memory data bus.

A32

MD62

I/O

Memory data bus.

A33

MD63

I/O

Memory data bus.

CPU Interface
B26

MASTSEL

I

Lexra bus master select, H:I2C, L:1x5180.

Interrupt Interface
T1

INT1

I

External interrupt, low active Edge or level.

I2C Interface
W5

SCLMAST2

I/O

I2C master 2 clock.

Y5

SDAMAST2

I/O

I2C master 2 data.

AE5

SCLMAST1

I/O

I2C master 1 clock.

AF5

SDAMAST1

I/O

I2C master 1 data.

LC-32X20E/S/RU, LC-37X20E/S/RU

5 – 30

I2S Interface
T3

SCKIN

O

I2S: SCK of I2S input port. (Not used)
AC Link: SDATA_OUT
POD2: POD_DRXB, the second POD OOB RX data.

T4

WSI2S

I

I2S: WS of I2S input port. (Not used)
AC Link: ACLINK_RSTN
POD2: POD_CRXB, the second POD OOB RX gapped clock.

T5

SDI2S

I

I2S: SD of I2S input port. (Not used)
AC Link: SYNC
POD2: POD_QTXB, the second POD OOB TXQ channel.

U1

WS

O

I2S: WS of I2S output port.
AC Link: SDATA_IN_2

U2

SCK

O

I2S: SCK of I2S output port.
AC Link: SDATA_IN_3

U3

SD1

O

I2S: SD of I2S output port.
AC Link: BIT_CLK

U4

SD2

O

I2S: SD of I2S output port. (Not used)
AC Link: SDATA_IN_0

U5

SD3

O

I2S: SD of I2S output port. (Not used)
AC Link: SDATA_IN_1

V5

I2SCLK

O

I2S: 1, 2, 4, 8 times of SCK of I2S output port, used by D/A chip.

V4

SD4

I

I2S: SCK of second I2S input port. (Not used)
POD2: POD_ETXB, the second POD OOB TX enable.

V3

SD5

I

I2S: WS of second I2S input port. (Not used)
POD2: POD_ITXB, the second POD OOB TXI channel.

V2

SD6

I

I2S: SD of second I2S input port. (Not used)
POD2: POD_CTXB, the second POD OOB TX gapped symbol clock.

SPDIF Interface
T2

SPDIF

I/O

SPDIF output.

UART Interface
Y4

TXD

O

Data output for UART.

Y3

RTS

O

Request to send output for UART (8mA output pad).

Y2

DTR

O

Data terminal Ready output for UART (8mA output pad, 5V TTL interface 25PF, 6ns 
rise timing).

Y1

RXD

I

Data input for UART.

AA1

CTS

I

Clear to send input for UART.

AA2

DSR

I

Data set ready for UART.

AA3

DCD

I

Receive line signal detect for UART. (Not used)

AA4

RI

I

Ring indicator for UART. (Not used)

Smart card Interface
V1

SCRST

I

Smart card reset 0, 8mA open-drain output pad. (Not used)

W1

SCPFET

I

Smart card power FET control output, 8mA open-drain output. The smart card reader 
interface requires this pin to drive an external power FET to supply the current for the 
Smart Card (65mA typical, 100mA short to ground). (Not used)

W2

SCIO

I/O

Smart card serial data, 8mA open-drain in out pad. (Not used)

W3

SCCLK

O

Smart card clock, 8mA open-drain output pad (7.1M to 3.5M) (Not used)

W4

SCPRES

I

Smart card present detect. (Not used)

CIR, RTC Interface
M1

VCCH12

—

1.2V RTC power for logic.

N1

VSSH12

—

RTC ground for logic.

L1

WDOG

O

Watch dog reset.

L2

VCCH33

—

3.3V RTC power for logic.

L3

CK32

I

32.768 kHz crystal oscillator input.

L4

CK32E

O

32.768 kHz crystal oscillator output.

L5

VSSH33

—

RTC ground for logic.

M5

CRX0

I

CIR0, receive data for CIRo interface.

M4

PWRON

O

Main power, power On control signal, low active, 4mA output pad. (Not used)

M3

PWRBT

I

Power switch button.

M2

VCCHRST

I

VCCH RST 

K4

VCCH12

—

1.2V RTC power for logic.

K5

VSSH12

—

RTC ground for logic.

R1

CTX0

O

Transmission data for CIR interface.

Program IO
AF4

GP15

I/O

Program IO.
PWM: Pulse-Width Modulation.
POD: OVERLOAD, the second POD interface current overload.

LC-32X20E/S/RU, LC-37X20E/S/RU

5 – 31

AF3

GP14

I/O

Program IO.
PWM: Pulse-Width Modulation.
POD: VS1, the second POD interface voltage sense.

AF2

GP13

I/O

Program IO.
PWM: Pulse-Width Modulation.
POD: VPP_EN#, the second POD interface slot VPP enable.

AF1

GP12

I/O

Program IO.
PWM: Pulse-Width Modulation.
POD: VPP_EN, the second POD interface slot VPP enable.

AG1

GP11

I/O

Program IO.
PWM: Pulse-Width Modulation.
POD: VCC_EN#, the second POD interface slot VCC enable.

AG2

GP10

I/O

Program IO.
PWM: Pulse-Width Modulation.
POD: VCC_EN, the second POD interface slot VCC enable.

AG3

GP9

I/O

Program IO.
PWM: Pulse-Width Modulation.
POD: WAIT#, WAIT# signal to expend bus cycle.

AG4

GP8

I/O

Program IO.
PWM: Pulse-Width Modulation.
POD: Ready and IREQ.

AG5

GP7

I/O

Program IO.
PWM: Pulse-Width Modulation.
POD: SI2C1_SDA, I2C bus SDA.

AH5

GP6

I/O

Program IO.
PWM: Pulse-Width Modulation.
POD: SI2C1_SCL, I2C bus SCL.

AH4

GP5

I/O

Program IO.
PWM: Pulse-Width Modulation.
POD: SI2C1_DEVID, I2C bus DEVID.

AH3

GP4

I/O

Program IO.
PWM: Pulse-Width Modulation.
POD: SI2C2_SDA, I2C bus SDA.

AH2

GP3

I/O

Program IO.
PWM: Pulse-Width Modulation.

AH1

GP2

I/O

Program IO.
PWM: Pulse-Width Modulation.

AJ1

GP1

I/O

Program IO.
PWM: Pulse-Width Modulation.
POD: SI2C2_SCL, I2C bus SCL.

AJ2

GP0

I/O

Program IO.
PWM: Pulse-Width Modulation.
POD: SI2C2_DEVID, I2C bus DEVID.

Power and ground pins
A26, AJ20, Y6

V5SF

—

5V safe power.

AA13, AA22, AB13, AB14, 
AB21, AB22, AD6, AE6, 
AF6, AG6, AH6, AJ8, AJ9, 
AJ10, AJ11, AJ12, AJ16, 
AJ17, AJ18, AJ19, AK11, 
AK12, AL11, AL12, AM12, 
AN12, AP12, E7, E8, F6, F7, 
F8, F9, G6, H6, J6, N13, 
N14, N21, N22, P13, P22, 
T6, U6, V6, W6

VDDC

—

Core power supply= 1.2V

A28, B28, C28, C29, D28, 
D29, E27, E28, F16, F17, 
F18, F19, F23, F24, F25, 
F26, F27, F28, K6, L 6, M6

VDDF

—

Power supply= 3.3V

AE31, AM31, C31, L31

VDDI33

—

3.3V power for DDR IO input buffer.

AA29, AA30, AA31, AA32, 
AA33, AA34, AD29, AD30, 
AE29, AE30, AH29, AH30, 
AH31, AJ27, AJ28, AK27, 
AK28, AL27, AL28, AM27, 
AM28, AM29, AN27, AN28, 
AP27, AP28, G29, G30, 
G31, K29, K30, L29, L30, 
V31, V32, W29, Y29, Y30

VDDM

—

2.5V supply ring for memory interface (Long PAD).

LC-32X20E/S/RU, LC-37X20E/S/RU

5 – 32

—

VSS

—

IO ground related to VDDF./Core ground related to VDDC.
A31, A34, AA6, AA14, AA15, AA16, AA17, AA18, AA19, AA20, AA21, AB6, AB15, 
AB16, AB17, AB18, AB19, AB20, AB31, AB34, AC6, AC29, AC32, AD31, AF29, 
AF32, AG31, AG34, AH32, AJ13, AJ14, AJ15, AJ21, AJ23, AJ24, AJ25, AJ26, AJ31, 
AJ34, AK32, AL31, AN16, AN23, AN29, AN32, AP31, AP34, B32, D31, E29, E32, 
F10, F11, F12, F13, F14, F15, F20, F21, F22, F31, F34, G32, H31, H34, J29, J32, 
K31, M29, M32, N6, N15, N16, N17, N18, N19, N20, N31, N34, P6, P14, P15, P16, 
P17, P18, P19, P20, P21, P29, P32, R6, R13, R14, R15, R16, R17, R18, R19, R20, 
R21, R22, R31, R34, T13, T14, T15, T16, T17, T18, T19, T20, T21, T22, T29, T32, 
U13, U14, U15, U16, U17, U18, U19, U20, U21, U22, U31, V13, V14, V15, V16, V17, 
V18, V19, V20, V21, V22, V33, W13, W14, W15, W16, W17, W18, W19, W20, W21, 
W22, W32, Y13, Y14, Y15, Y16, Y17, Y18, Y19, Y20, Y21, Y22, Y31, Y34

AL29, V29, C30

MVREF

—

Memory interface voltage reference.

AL30, V30, D30

VDDR

—

1.8V input buffer reference power.

AK29

VSSR

—

Ground of input buffer reference power.

OTHER
C26

RESET#

I

System reset input, high active.

AJ7

FULL_EJTAG

I

1: Full EJTAG, 0:simple EJTAG.

K3

VCOTP

O

DEMUX output.

K2

CLK27M

I

DEMUX input.

AM6

PCMOD

I

1: PC MODE (Not used)

AL6

TESTCON

I

Test mode control.

AK6

TESTMOD

I

Test mode input.

53, 52

CK, CK

I

Clock: CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the 
positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK 
and CK (both directions of crossing).

41

CKE

I

Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input 
buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh opera-
tion (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power 
down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be 
maintained high throughout read and write accesses. Input buffers, excluding CK, and CKE are disabled 
during powerdown. Input buffers, excluding CKE, are disabled during self refresh.

51

CS

I

Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank 
selection on systems with multiple banks. CS is considered part of the command code.

19

ODT

I

On Die Termination: ODT (registered HIGH) enables termination resistance internal to the gDDR2 
SDRAM. When enabled, ODT is only applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM 
signal for x16 configurations. The ODT pin will be ignored if the Extended Mode Register (EMRS) is pro-
grammed to disable ODT.

77, 76, 70

RAS, CAS, WE

I

Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

66, 62

(L) UDM

I

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled 
HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.

42, 71

BA0 - BA1

I

Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge com-
mand is being applied. BA0 also determines if the mode register or extended mode register is to be 
accessed during a MRS or EMRS cycle.

50, 72, 75, 
44, 49, 73, 
74, 45, 48, 
46, 43, 47, 13

A0 - A12

I

Address Inputs: Provided the row address for Active commands and the column address and Auto Pre-
charge bit for Read/Write commands to select one location out of the memory array in the respective 
bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one 
bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by 
BA0, BA1. The address inputs also provide the op-code during Mode Register Set commands.

DQ

I/O

Data Input/ Output: Bi-directional data bus.

81, 57,
61, 29

LDQS, (LDQS)
UDQS, (UDQS)

I/O

Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write 
data. LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15.
The data strobes LDQS and UDQS may be used in single ended mode or paired with optional comple-
mentary signals LDQSand UDQS to provide differential pair signaling to the system during both reads 
and writes. An EMRS (1) control bit enables or disables all complementary data strobe signals.

10, 14, 15, 
16, 32, 36, 

NC/RFU

—

No Connect: No internal electrical connection is present.

3, 7, 22, 24, 
26, 28, 63, 
67, 80, 84

VDDQ

—

DQ Power Supply: 1.8V 

± 0.1V.