Sharp LC-37X20E Service Manual ▷ View online
LC-32X20E/S/RU, LC-37X20E/S/RU
5 – 17
T1
AVSSLLPLL
—
1.2V Line Lock PLL GND.
Miscellaneous Ball Assignments.
F18
F18
RESET
I
System reset forces the chip to a known state. Active High.
G18
INTN
I/O
Interrupt signal (active low).
G17
PWM0
I/O
PWM I/O. (Not connected)
F16
V5SF
I
5V reference voltage (must be connected to 5V even in standby mode, when CPU
I/O is 5V)
I/O is 5V)
F17
TESTMODE
I
Reserved (Connected to ground).
LVDS Output Ball Assignments.
A14
A14
TA1P
O
LVDS 1st Channel Differential positive data out.
B14
TA1M
O
LVDS 1st Channel Differential negative data out.
A15
TB1P
O
LVDS 1st Channel Differential positive data out.
B15
TB1M
O
LVDS 1st Channel Differential negative data out.
A16
TC1P
O
LVDS 1st Channel Differential positive data out.
B16
TC1M
O
LVDS 1st Channel Differential negative data out.
A18
TD1P
O
LVDS 1st Channel Differential positive data out.
B18
TD1M
O
LVDS 1st Channel Differential negative data out.
A19
TE1P
O
LVDS 1st Channel Differential positive data out.
B19
TE1M
O
LVDS 1st Channel Differential negative data out.
B17
TCLK1M
O
LVDS 1st Channel Differential positive CLK out.
A17
TCLK1P
O
LVDS 1st Channel Differential negative CLK out.
F19
TCLK2M
O
LVDS 2st Channel Differential positive CLK out.
E20
TCLK2P
O
LVDS 2st Channel Differential negative CLK out.
H19
TE2P
O
LVDS 2st Channel Differential positive data out.
G20
TE2M
O
LVDS 2st Channel Differential negative data out.
G19
TD2P
O
LVDS 2st Channel Differential positive data out.
F20
TD2M
O
LVDS 2st Channel Differential negative data out.
E19
TC2P
O
LVDS 2st Channel Differential positive data out.
D20
TC2M
O
LVDS 2st Channel Differential negative data out.
B20
TB2P
O
LVDS 2st Channel Differential positive data out.
A20
TB2M
O
LVDS 2st Channel Differential negative data out.
D19
TA2P
O
LVDS 2st Channel Differential positive data out.
C20
TA2M
O
LVDS 2st Channel Differential negative data out.
HDMI Interface Ball Assignments.
L4
L4
PVCC
—
TMDS PLL supply voltage.
M5
ANTSTO
O
Test pin. (Not connected)
M4, N4, N5, P4
AVCC
—
TMDS analog supply voltage.
L2
RXC-
I
TMDS differential CLK-.
L1
RXC+
I
TMDS differential CLK+.
L3, M3, N3, P3, R1
TMDS_GND
—
TMDS GND.
M2
RX0-
I
HDMI Differential input pair 0-
M1
RX0+
I
HDMI Differential input pair 0+
N2
RX1-
I
HDMI Differential input pair 1-
N1
RX1+
I
HDMI Differential input pair 1+
P2
RX2-
I
HDMI Differential input pair 2-
P1
RX2+
I
HDMI Differential input pair 2+
R5
REGVCC
—
ACR PLL Regulator supply voltage.
P5
DGND
—
ACR PLL GND.
T10
PWR5V
I
TMDS port Transmitter Detect (5V tolerant).
T11
DSCL
I/O
DDC I2C clock for DDC (5V tolerant).
U11
DSDA
I/O
DDC I2C data for DDC (5V tolerant).
U12
WS
O
I2S Word select output.
V11
SCDT
O
Indicates Active video at HDMI input port.
V12
SD0
O
I2S serial data output.
W11
AUDIOCLK
I
Audio master clock input reference.
W12
SPDIF
O
S/PDIF audio output.
Y11
SCK
O
I2S serial clock output.
Pin Assignments for Reference Voltage.
V5
V5
VREFN1
—
ADC1 voltage reference-.
W5
VREFP1
—
ADC1 voltage reference+.
V7
VREFN2
—
ADC2 voltage reference-.
W7
VREFP2
—
ADC2 voltage reference+.
Pin No.
Pin Name
I/O
Pin Function
LC-32X20E/S/RU, LC-37X20E/S/RU
5 – 18
2.10. IC3501-2 (RH-iXC163WJQZQ)
2.10.1 Block Diagram
2.10.2 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
62, 63
CK, CK
I
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except DQ’s and DM’s that are
sampled on both edges of the DQS.
All of the inputs are sampled on the rising edge of the clock except DQ’s and DM’s that are
sampled on both edges of the DQS.
22
CKE
I
Activates the CK signal when high and deactivates the CK signal when low. By deactivating
the clock, CKE low indicates the Power down mode or Self refresh mode.
the clock, CKE low indicates the Power down mode or Self refresh mode.
12
CS
I
CS enables the command decoder when low and disabled the command decoder when high.
When the command decoder is disabled, new commands are ignored but previous operations
continue.
When the command decoder is disabled, new commands are ignored but previous operations
continue.
11
RAS
I
Latches row addresses on the positive going edge of the CK with RAS low.
Enables row access & precharge.
Enables row access & precharge.
10
CAS
I
Latches column addresses on the positive going edge of the CK with CAS low.
Enables column access.
Enables column access.
53
WE
I
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Latches data in starting from CAS, WE active.
1, 28, 7, 34
DQS0-3
I/O
Data input and output are synchronized with both edge of DQS.
44, 67, 50, 35
DM0-3
I
Data In mask. Data In is masked by DM Latency=0 when DM is high in burst write. DM0 for
DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31.
DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31.
40, 78, 41, 42, 2, 46, 3, 4,
26, 65, 27, 66, 29, 68, 30,
69, 48, 5, 49, 6, 51, 8, 9,
52, 31, 32, 71, 33, 37, 38,
75, 39
26, 65, 27, 66, 29, 68, 30,
69, 48, 5, 49, 6, 51, 8, 9,
52, 31, 32, 71, 33, 37, 38,
75, 39
DQ0-31
I/O
Data inputs/Outputs are multiplexed on the same pins.
14, 56
BA0, BA1
I
Selects which bank is to be active.
15, 16, 57, 17, 18, 60, 19,
20, 21, 59, 90, 58
20, 21, 59, 90, 58
A0-11
I
Row/Column addresses are multiplexed on the same pins.
Row addresses: RA0 ~ RA11, Column addresses: CA0 ~ CA7.
Column address CA8 is used for auto precharge.
Row addresses: RA0 ~ RA11, Column addresses: CA0 ~ CA7.
Column address CA8 is used for auto precharge.
82, 88, 91, 92, 95, 101,
105, 106
105, 106
VDD
—
Power for the input buffers and core logic.
LC-32X20E/S/RU, LC-37X20E/S/RU
5 – 19
2.11. IC7507 (VHiCE6353++-1Q)
2.11.1 Block Diagram
89, 94, 109, 115, 116,
117, 118, 124, 126, 127,
129, 130, 131, 132, 133,
134, 135, 136, 137, 138,
139, 140, 141, 142, 143,
144
117, 118, 124, 126, 127,
129, 130, 131, 132, 133,
134, 135, 136, 137, 138,
139, 140, 141, 142, 143,
144
VSS
—
Ground for the input buffers and core logic.
45, 47, 70, 72, 74, 76, 77,
79, 83, 84, 86, 87, 96, 97,
99, 100
79, 83, 84, 86, 87, 96, 97,
99, 100
VDDQ
—
Isolated power supply for the output buffers to provide improved noise immunity.
36, 43, 81, 102, 103, 104,
107, 108, 110, 111, 112,
113, 114, 119, 120, 121,
122, 123, 125, 128
107, 108, 110, 111, 112,
113, 114, 119, 120, 121,
122, 123, 125, 128
VSSQ
—
Isolated ground for the output buffers to provide improved noise immunity.
23
VREF
—
Reference voltage for inputs, used for SSTL interface.
93, 61
RFU1/RFU2
—
Reserved for Future Use.
13, 24, 25, 54, 55, 64, 73,
80, 85, 98
80, 85, 98
NC
—
No Connection.
Pin No.
Pin Name
I/O
Pin Function
LC-32X20E/S/RU, LC-37X20E/S/RU
5 – 20
2.11.2 Pin Connections and short description
2.12. IC7603 (9NK2633003842)
2.12.1 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
MPEG pins
47
47
MOSTRT
O
MPEG packet start
48
MOVAL
O
MPEG data valid
49-53, 56-58
MDO[0:4]/ MDO[5:7]
O
MPEG data bus
61
MOCLK
O
MPEG clock out
62
BKERR
O
Block error
63
MICLK
I
MPEG clock in
11
STATUS
O
Status output
6
IRQ
O
Interrupt output
Control pins
4
4
CLK1
I
Serial clock
5
DATA1
I/O
Serial data
23
XTI
I
Low phase noise oscillator
24
XTO
O
10
SLEEP
I
Device power down
12, 15-18
SADD[4:0]
I
Serial address set
44
SMTEST
I
Production test (only set low)
35
CLK2/GPP0
I/O
Serial clock tuner
36
DATA2/GPP1
I/O
Serial data tuner
42
AGC1
O
Primary AGC
41
AGC2/GPP2
I/O
Secondary AGC
43
GPP3
I/O
General purpose I/O
9
RESET
I
Device reset
27
OSCMODE
I
Crystal oscillator mode
26
PLLTEST
O
PLL analog test
Analog inputs
30
30
VIN
I
positive input
31
VIN
I
negative input
34
RFLEV
I
RF level
Supply pins
21
21
PLLVdd
—
PLL supply
22
PLLGND
—
GND
7, 19, 37, 39, 59, 64
CVdd
—
Core logic power
2, 13, 45, 54
Vdd
—
I/O ring power
1, 3, 8, 14, 20, 25, 38,
40, 46, 55, 60
40, 46, 55, 60
Vss
—
Core and I/O ground
28
Avdd
—
ADC analog supply
29, 32
AGnd
—
GND
33
Vdd
—
2nd ADC supply
Pin No.
Pin Name
I/O
Pin Function
1
Css
I
Soft start timing capacitor.
2
Rfstart
—
Soft start frequency setting-low impedance voltage source-see also Cf.
3
Cf
—
Oscillator frequency setting-see also Rfmin, Rfstart.
4
Rfmin
I
Minimum oscillation frequency setting-low impedance voltage source-see also Cf.
5
OPOUT
O
Sense OP Amp output-low impedance.
6
OPIN-
I
Sense OP Amp inverting input-high impedance.
7
OPIN+
I
Sense OP Amp non inverting input-high impedance.
8
EN1
I
Half bridge latched enable.
9
EN2
I
Half bridge unlatched enable.
10
GND
—
Ground.
11
LVG
O
Low side driver output.
12
Vss
—
Supply voltage with internal zener clamp.
13
N.C.
—
Not connected.
14
OUT
O
High side driver reference.
15
HVG
O
High side driver output.
16
VBOOT
I
Bootstrapped supply voltage.
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