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LC-32X20E/S/RU, LC-37X20E/S/RU

5 – 37

62

GND_B

—

Ground

63

CPLD_TDI

I

64

PNL_WP

O

VCOM Write Protect control signal

65

CPLD_TMS

O

66

FE_RST

O

CE6353 reset

67

CPLD_TCK

O

68

FEPG0_COMP

O

Sleep signal

69

FEPG1_LOCK

I

Signal LOCK detection

70

FERR_UNCOR

I

Error flag

71

N_TS1_DEMORST

O

TS1 demodulator reset

72

GND_B

—

Ground

73

D3.3V

—

Power supply (+3.3V)

74

EXTRG

O

Partner

75

DRSTMSK

O

Partner

76

N_IRS_INT

I

IrSS interrupt request

77

CLON_RC

O

For controlling clone remote control

78

DTM_RST

O

Reset signal for DTM

79

N_IRS_RST

O

IrSS reset signal

80

DTM_GPIO0

I

Control signal for DTM (GPIO0)

81

DTM_GPIO1

O

Control signal for DTM (GPIO1)

82

DTM_UART_INT

I

Interrupt request of UART-I2C conversion IC for DTM

83

DTM_UART_RST

O

Reset of UART-I2C conversion IC for DTM

84

D3.3V

—

Power supply (+3.3V)

85

AGC_SEL

O

Digital/Analog AGC switching control

86

HP_MUTE

O

HP audio mute control

87

HP_PLUG

I

HP connection detection

88

CION

O

VCC/ON signal for PCMCIA

89

GND_B

—

Ground

90

GND_B

—

Ground

91

SC2_MUTE

O

SCART2 audio mute control

92

SPDIF_MUTE

O

SPDIF audio mute control

93

SC_MUTE

O

SCART1 audio mute control

94

S_STBY

O

Audio AMP shutdown control

95

DU_LINK_ACK0

I

ACK from IEEE1394 chip

96

SIF_SW

O

I2C line SW control of sound multiplex decoder

97

DU_LINK_IRQ

I

IEEE1394 chip interrupt request

98

CNVSS

O

Monitor microprocessor write mode control

99

GND_B

—

Ground

100

N_PCI_RST

O

PCI reset

101

RS_BUF_CNT

O

Monitor microprocessor UART mode switching

102

PNL_I2C_EN

O

VCOM/I2C switch control

103

AUDIO_SEL2

O

DTV/HDMI analog audio switching control 2

104

PCHD_AUDIO_SEL

O

PC/HDMI external audio input switching

105

N_DVOUT_EN

O

DTV/AD YPbPr switching

106

MSP_RESET

O

MSP reset

107

HDMI_RESET

O

HDMI-TMDS_SW reset

108

GND_B

—

Ground

109

D3.3V

—

Power supply(+3.3V)

110

SVP_RESET

O

SVP_WX reset

111

N_PHY_RESET

O

i.Link PHY reset

112

N_LINK_RESET

O

i.Link LINK reset

113

FL_VPP0

O

Flash WP

114

GND_B

—

Ground

115

AREA_4

I

Destination setting (L: Europe/H: Asia)

116

DIG_AD

I

DTV add-on Unit presence/absence setting

117

HDMI_SEL1

O

HDMI_Select_1

118

HDMI_SEL2

O

HDMI_Select_2

119

HDMI_SEL3

O

HDMI_Select_3

120

HDMI_HPG1

I

HDMI_HotPlug_1

121

HDMI_HPG2

I

HDMI_HotPlug_2

122

CPLD_TDO

O

123

GND_B

—

Ground

124

HDMI_HPG3 

I

HDMI_HotPlug_3 (for temporary insertion)

125

HDMI_SW_EMP

O

HDMI output waveform adjustment

LC-32X20E/S/RU, LC-37X20E/S/RU

5 – 38

126

HDMI_PLG_EN

O

HDMI output control

127

D3.3V

—

Power supply(+3.3V)

128

MUTE_HDMI

O

HDMI_MUTE initial value Low

129

HPLUGOUT_A

I

HDMI Plug Out detection

130

HDMIKEY_WP

O

EDIT_Write Protect

131

N_CPLD2_RST

O

CPLD2 reset

132

PNL_POW

O

Panel power control

133

HDMI_SW_INT

INT

HDMI SW IC interrupt request

134

HDELAY_DOUT

O

HDMI Data Delay Serial_Data_OUTPUT

135

N_MICOM_FLSW

O

Monitor microprocessor write control

136

N_MICOM_RST

O

Monitor microprocessor reset control

137

SMPOWHOLD

O

Power holding signal

138

PM_REQ

INT

Panel Maicon REQ

139

N_DBOOTS

I

Microprocessor write request

140

CBOOTS

I

SD card activation detection

141

D3.3V

—

Power supply(+3.3V)

142

N_DBG_RST

I

Debugger (Partner) reset

143

N_SRESET

I

System reset

144

GND_B

—

Ground

LC-32X20E/S/RU, LC-37X20E/S/RU

5 – 39

14

BOOST

O

Gate drive voltage for the high side N-channel MOSFET.
The BOOST voltage is 9 V greater than the input voltage.
A 0.1-

µF ceramic capacitor should be connected from this pin to the drain of the lower MOSFET.

3

BP5

O

5-V reference.
This pin should be bypassed to ground with a 0.1-

µF ceramic capacitor.

This pin may be used with an external DC load of 1 mA or less.

11

BP10

O

10-V reference used for gate drive of the N-channel synchronous rectifier.
This pin should be bypassed by a 1-

µf ceramic capacitor.

This pin may be used with an external DC load of 1 mA or less.

8

COMP

O

Output of the error amplifier, input to the PWM comparator.
A feedback network is connected from this pin to the VFB pin to compensate the overall loop.
The comp pin is internally clamped above the peak of the ramp to improve large signal transient response.

13

HDRV

O

Floating gate drive for the high-side N-channel MOSFET.
This pin switches from BOOST (MOSFET on) to SW (MOSFET off).

16

ILIM

I

Current limit pin, used to set the overcurrent threshold.
An internal current sink from this pin to ground sets a voltage drop across an external resistor connected from 
this pin to VCC.
The voltage on this pin is compared to the voltage drop (VIN-SW) across the high side MOSFET during con-
duction.

1

KFF

I

A resistor is connected from this pin to VIN to program the amount of voltage feed-forward.
The current fed into this pin is internally divided and used to control the slope of the PWM ramp.

10

LDRV

O

Gate drive for the N-channel synchronous rectifier.
This pin switches from BP10 (MOSFET on) to ground (MOSFET off).

9

PGND

—

Power ground reference for the device.
There should be a low-impedance path from this pin to the source (s) of the lower MOSFET (s).

2

RT

I

A resistor is connected from this pin to ground to set the internal oscillator and switching frequency.

5

SGND

—

Signal ground reference for the device.

6

SS/SD

I

Soft-start programming pin.
A capacitor connected from this pin to ground programs the soft-start time.
The capacitor is charged with an internal current source of 2.3 

µA.

The resulting voltage ramp on the SS pin is used as a second non-inverting input to the error amplifier.
The output voltage begins to rise when VSS/SD is approximately 0.85 V.
The output continues to rise and reaches regulation when VSS/SD is approximately 1.55 V.
The controller is considered shut down when VSS/SD is 125 mV or less. All internal circuitry is inactive.
The internal circuitry is enabled when VSS/SD is 210 mV or greater.
When VSS/SD is less than approximately 0.85 V, the outputs cease switching and the output voltage (VOUT) 
decays while the internal circuitry remains active.

12

SW

I

This pin is connected to the switched node of the converter and used for overcurrent sensing. 

4

SYNC

I

Syncronization input for the device.
This pin can be used to synchronize the oscillator to an external master frequency.
If synchronization is not used, connect this pin to SGND.

7

VFB

I

Inverting input to the error amplifier.
In normal operation the voltage on this pin is equal to the internal reference voltage, 0.7 V.

15

VIN

I

Supply voltage for the device.

LC-32X20E/S/RU, LC-37X20E/S/RU

5 – 40

1

BS

I

High-Side Gate Drive Boost Input. BS supplies the drive for the high-side N-Channel MOSFET switch.
Connect a 0.01

µF or greater capacitor from SW to BS to power the high side switch.

2

IN

I

Power Input. IN supplies the power to the IC, as well as the step-down converter switches.

3

SW

Drive IN with a 4.45V to 28V power source. Bypass IN to GND with a suitably large capacitor to eliminate noise 
on the input to the IC.

4

GND

Ground.

5

FB

Feedback Input. FB senses the output voltage to regulate that voltage. Drive FB with a resistive voltage divider 
from the output voltage. The feedback reference voltage is 0.8V.

6

COMP

Compensation Node. COMP is used to compensate the regulation control loop. Connect a series RC network 
from COMP to GND to compensate the regulation control loop. In same cases, an additional capacitor from 
COMP to GND is required.

7

EN

Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator, drive 
it low to turn it off.

8

SS

Soft-start Control Input. SS controls the soft-start period. Connect a capacitor from SS to GND to set the soft-
start period.