DOWNLOAD Sharp MX-6201N / MX-7001N (serv.man45) Service Manual ↓ Size: 18.45 MB | Pages: 127 in PDF or view online for FREE

Model
MX-6201N MX-7001N (serv.man45)
Pages
127
Size
18.45 MB
Type
PDF
Document
Service Manual
Brand
Device
Copying Equipment / MX6201 MX7001- Circuit Diagram
File
mx-6201n-mx-7001n-sm45.pdf
Date
PREV: Sharp MX-6201N / MX-7001N (serv.man44) Service Manual

Sharp MX-6201N / MX-7001N (serv.man45) Service Manual ▷ View online

MX-7001N  CIRCUIT DIAGRAM / 回路図  2 – 6
SA_VCCNG_3
.3V
DGND
DGND
+
3
.3V
DGND
+
3
.3V
DGND
+
3
.3V
DGND
+
3
.3V
DGND
DGND
+
3
.3V
DGND
DGND
DGND
DGND
+
3
.3V
+
3
.3V
DGND
+
5V_IN
+
3
.3V
DGND
DGND
DGND
+
3
.3V
DGND
DGND
DGND
+
3
.3V
DGND
+
3
.3V
SRAM_CE2_BASE
{18
,51
}
GPO_SELFRST
{43
}
RES_MFP_MT
{31
}
RES_MFP_FAX2
{2
9}
nIFASIC_RST_BASE
{18
}
JTAGICE_RESET
{7}
V33_RTN_JIG1
{2
0}
CPU_MODECLK_2
.5V
{7}
CPU_MODECLK_3
.3V
{2
0}
GPO_nSOFTRST_PCI2
{43
}
GPO_nSOFTRST_IMG
{43
}
GPO_nSOFTRST_PCI1
{43
}
nPCI1_RST
{1
7,
23
,33
}
nPCI2_RST
{1
6,
3
6,
4
7}
nIMGASIC_RST
{4
0,
42
}
SA_VCCOK_2
.5V
{7,
8
}
nIOGA_RST
{43
,51
}
SA_CPURST_2
.5V
{7,
8
}
RESET_GOOD
{2
0}
nSYSTEM_RST
{13
}
SRAM_CE2_DELAY
{51
}
nFROM_RST
{25
,2
6}
SELF_RESET
b
y
MPU
Force
Reset
by
Anot
h
er
PWB
CP1
07
R1
09
1
00
J
CP
9
4
CP
97
CP
90
C4
0.
1uF(B)
CP112
5
6
14
7
IC1
6
C
SN
7
4LVC14APWR
E
B
C
Q
7
DTC114YUA
1
0
K
4
7
K
CP
9
1
CP
9
1
E
B
C
1
0
K
4
7
K
Q
8
DTC114YUA
11
1
0
14
7
IC1
6
E
SN
7
4LVC14APWR
8
1
7
2
6
3
5
4
BR3
1
0
KJ
x4
C
60
0.
1uF(B)
C5
X_1
000
pF
CP1
00
R1
06
1
0
KJ
8
1
7
2
6
3
5
4
BR4
4
7
KJ
x4
E
B
C
1
0
K
4
7
K
Q
6
DTC114YUA
CP1
0
4
C52
0.
1uF(B)
9
8
14
7
IC1
6
D
SN
7
4LVC14APWR
CP1
0
5
CP115
R142
33J
CP
9
2
CP11
0
CP111
CP
9
5
C5
7
1
000
pF
CP
9
8
R111
1KJ
3
4
14
7
IC1
6
B
SN
7
4LVC14APWR
CP1
09
NC
1
A
2
GND
3
Y
4
VCC
5
IC11
SN
7
4LVC1G
0
4DCK
Y=/A
C
7
4
0
1uF(1
60
8:B)
CP1
0
8
CP1
0
3
CP1
06
CP
96
13
12
14
7
IC1
6
F
SN
7
4LVC14APWR
R113
1
0
KJ
R113
1
0
KJ
E
B
C
1
0
K
4
7
K
Q
9
DTC114YUA
CP1
0
2
CP1
0
1
CP
99
R1
07
33J
R1
07
33J
CP114CP114
GND
1
VDD
2
CT
3
VOUT
4
IC15
BU4242F
CP
9
3
E
B
C
Q
5
DTC114YUA
1
0
K
4
7
K
CP113
1
2
14
7
IC1
6
A
SN
7
4LVC14APWR
C5
9
0.
1uF(B)
1A1
2
1A2
4
1A3
6
1A4
8
2A1
11
2A2
13
2A3
15
2A4
1
7
1G
1
2G
1
9
1Y1
18
1Y2
1
6
1Y3
14
1Y4
12
2Y1
9
2Y2
7
2Y3
5
2Y4
3
VCC
2
0
GND
1
0
IC18
SN
7
4LVC244APWR
C
6
2
0.
1uF(B)
C55
0.
1uF(1
60
8:B)
5
5
4
4
43
32
2
1
1
D
D
C
C
B
B
A
A
MFPC
PWB
(R
eSet
Tree
)
4/52
(6
)
MX-7001N  CIRCUIT DIAGRAM / 回路図  2 – 7
CPU_JTDO
SA_SYSAD32
SA_SYSAD31
SA_SYSAD36
SA_SYSAD56
SA_SYSAD41
SA_SYSAD54
SA_SYSAD21
SA_SYSAD2
SA_SYSAD27
SA_SYSAD39
SA_SYSAD63
SA_SYSAD29
SA_SYSAD37
SA_SYSAD44
SA_SYSAD45
SA_SYSAD18
SA_SYSAD35
SA_SYSAD9
SA_SYSAD34
SA_SYSAD26
SA_SYSAD57
SA_SYSAD25
SA_SYSAD20
SA_SYSAD46
SA_SYSAD8
SA_SYSAD49
SA_SYSAD33
SA_SYSAD10
SA_SYSAD53
SA_SYSAD13
SA_SYSAD19
SA_SYSAD61
SA_SYSAD6
SA_SYSAD40
SA_SYSAD48
SA_SYSAD62
SA_SYSAD0
SA_SYSAD7
SA_SYSAD14
SA_SYSAD3
SA_SYSAD58
SA_SYSAD22
SA_SYSAD47
SA_SYSAD30
SA_SYSAD38
SA_SYSAD1
SA_SYSAD4
SA_SYSAD43
SA_SYSAD52
SA_SYSAD50
SA_SYSAD5
SA_SYSAD60
SA_SYSAD16
SA_SYSAD17
SA_SYSAD28
SA_SYSAD59
SA_SYSAD42
SA_SYSAD11
SA_SYSAD55
SA_SYSAD12
SA_SYSAD24
SA_SYSAD23
SA_SYSAD51
SA_SYSAD15
SA_JTCLK_PU
ICU_INT_2.5V
SA_JTDI_PU
SA_JTMS_PU
PCI1_PME_2.5V
SA_JTRST_PD
IF_INT_2.5V
SYSAD44
SYSAD45
SYSAD46
SYSAD47
SYSAD52
SYSAD53
SYSAD54
SYSAD55
SYSAD28
SYSAD29
SYSAD30
SYSAD31
SYSAD40
SYSAD41
SYSAD42
SYSAD43
SYSAD4
SYSAD5
SYSAD6
SYSAD7
SYSAD12
SYSAD13
SYSAD14
SYSAD15
SYSAD48
SYSAD49
SYSAD50
SYSAD51
SYSAD24
SYSAD25
SYSAD26
SYSAD27
SYSAD36
SYSAD37
SYSAD38
SYSAD39
SYSAD0
SYSAD1
SYSAD2
SYSAD3
SYSAD8
SYSAD9
SYSAD10
SYSAD11
SYSAD20
SYSAD21
SYSAD22
SYSAD23
SYSAD32
SYSAD33
SYSAD34
SYSAD35
SYSAD16
SYSAD17
SYSAD18
SYSAD19
SYSAD60
SYSAD61
SYSAD62
SYSAD63
SYSAD56
SYSAD57
SYSAD58
SYSAD59
SA_SYSCMD1
SA_SYSCMD4
SA_SYSCMD7
SA_SYSCMD5
SA_SYSCMD6
SA_SYSCMD2
SA_SYSCMD0
SA_SYSCMD3
SA_SYSCMD8
SYSCMD8
SYSCMD7
SYSCMD6
SYSCMD5
SYSCMD4
SYSCMD3
SYSCMD2
SYSCMD1
SYSCMD0
nPOF_2.5V
PCI_INT1_2.5V
PCI1_PME_2.5V
nPOF_2.5V
MODEDAT_2.5V
PCI_INT2_2.5V
nEFI_WU_2.5V
nEFI_WU_2.5V
nIMGINT
IF_INT_2.5V
PCI_INT2_2.5V
PCI_INT1_2.5V
SA_EXTRQST
SA_RSPSWAP
CPU_VC
+2.5V
+2.5V
+2.5V
+2.5V
+2.5V
+3.3V
+2.5V
+3.3V
S
S
S
S
S
SA_NMI_2.5V {8}
SA_CPURST
SA_VCCOK_
SA_COLDRS
S
SA_SYSAD[63:0]
{8}
SA_SYSCMD[8:0]
{8}
CPU_MODECLK_2.5V {6}
CPU_JTDO {53}
CPU_JTDI_PU {53}
TEST_JTCK1 {13,53}
TEST_JTRST1 {13,20,53}
TEST_JTMS1 {13,53}
JTAGICE_RESET
{6}
SA_INT_2.5V {8}
nREQ_PIC_INT_OC
8
1
7
2
6
3
5
4
BR8
47Jx4
BR8
47Jx4
8
1
7
2
6
3
5
4
BR37
10KJx4
C66
1000pF
8
1
7
2
6
3
5
4
BR36
47Jx4
BR36
47Jx4
8
1
7
2
6
3
5
4
BR42
47Jx4
C67
0.1uF(B)
KP1
1
2
L7
BLM15AG121SN1(10
CP133
8
1
7
2
6
3
5
4
BR26
47Jx4
BR26
47Jx4
CP135
R114
47J
8
1
7
2
6
3
5
4
BR22
47Jx4
BR22
47Jx4
CP116
8
1
7
2
6
3
5
4
BR28
47Jx4
BR28
47Jx4
8
1
7
2
6
3
5
4
BR12
47Jx4
BR12
47Jx4
C94
220pF
8
1
7
2
6
3
5
4
BR34
47Jx4
BR34
47Jx4
CP126
RJ1
0J
R130
10KJ
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
CN1
X_SM08B-SRSS-TB
R118
47J
CP118
C98
220pF
8
1
7
2
6
3
5
4
BR30
47Jx4
BR30
47Jx4
C100
220pF
C68
10uF(2012)
CP128
8
1
7
2
6
3
5
4
BR18
47Jx4
BR18
47Jx4
8
1
7
2
6
3
5
4
BR41
47Jx4
CP131
R132
47J
CP130
CP140
8
1
7
2
6
3
5
4
BR32
47Jx4
BR32
47Jx4
8
1
7
2
6
3
5
4
BR38
10KJx4
R117
47J
R11
6
1
0
KJ
R145
4
.7
KJ
8
1
7
2
6
3
5
4
BR20
47Jx4
BR20
47Jx4
8
1
7
2
6
3
5
4
BR45
22Jx4
CP139
R133
10KJ
R143
2
.2KJ
8
1
7
2
6
3
5
4
BR11
47Jx4
BR11
47Jx4
CP125
C99
220pF
SYSAD35
A5
SYSAD33
A7
SYSAD32
A8
SYSADC1
A10
SYSADC2
A13
SYSAD62
A14
SYSAD60
A16
SYSAD3
B6
SYSAD2
B7
SYSAD1
B8
SYSADC5
B9
SYSADC0
B10
SYSADC3
B11
SYSADC6
B12
SYSAD30
B14
SYSAD29
B15
SYSAD34
C7
SYSAD0
C9
SYSADC4
C10
SYSADC7
C11
SYSAD31
C13
SYSAD61
C14
SYSAD63
D13
SYSAD28
D15
SYSAD5
E1
SYSAD59
E20
SYSAD36
F2
SYSAD4
F3
SYSAD27
F18
SYSAD58
F19
SYSAD38
G1
SYSAD6
G2
SYSAD37
G3
SYSAD26
G18
SYSAD57
G19
SYSAD25
G20
SYSAD7
H1
SYSAD39
H2
SYSAD40
H3
SYSAD8
H4
SYSAD24
H17
SYSAD56
H18
SYSAD55
H19
SYSAD23
H20
SYSAD9
J2
SYSAD54
J18
SYSAD22
J19
SYSAD41
K1
SYSAD10
K2
SYSAD42
K3
SYSAD11
K4
SYSAD53
K17
SYSAD21
K18
SYSAD52
K19
SYSAD20
K20
SYSAD43
L1
SYSAD44
L2
SYSAD12
L3
SYSAD51
L18
SYSAD19
L19
SYSAD50
L20
SYSAD13
M2
SYSAD45
M3
SYSAD18
M18
SYSAD49
M19
SYSAD14
N1
SYSAD46
N2
SYSAD47
N4
SYSAD48
N18
SYSAD16
N19
SYSAD17
N20
SYSAD15
P1
RSPSWAP
P2
PACK
P3
COLDRESET
P17
BIGENDIAN
P19
RESET
P20
JTDI
R3
JTCK
R4
EXTRQST
R18
NMI
R19
PRQST
T1
JTDO
T2
INT9
T19
INT8
T20
MODECLOCK
U1
JTMS
U3
VALIDIN
U6
SYSCMD7
U13
INT3
U15
INT6
U18
INT7
U20
RDTYPE
V4
RDRDY
V5
SYSCMD3
V12
SYSCMD6
V13
INT2
V15
INT5
V16
INT4
V17
WRRDY
W5
RELEASE
W6
SYSCLK
W7
SYSCMD1
W11
SYSCMD2
W12
SYSCMD5
W13
SYSCMDP
W14
INT1
W16
MODEIN
Y4
VALIDOUT
Y5
SYSCMD0
Y11
SYSCMD4
Y13
SYSCMD8
Y14
INT0
Y17
VCCOK
P18
VCCP
Y7
VCCP
V6
VSSP
U7
VREF_IN
V10
SYSCLK
V7
VREF_IN
B13
HSTL_SEL
A11
JTRST
T4
VCCIO/JTAGSEL
U5
RM7065C/7965 1/2
IC19A
RM7965
IC19A
R115
1
0
KJ
8
1
7
2
6
3
5
4
BR16
47Jx4
BR16
47Jx4
8
1
7
2
6
3
5
4
BR14
47Jx4
BR14
47Jx4
CP124
R135
X_10J
CP123
8
1
7
2
6
3
5
4
A1
2
A2
4
A3
6
A4
8
1OE
1
Y1
18
Y2
16
Y3
14
Y4
12
VCC
20
GND
10
A5
11
A6
13
A7
15
A8
17
Y5
9
Y6
7
Y7
5
Y8
3
2OE
19
IC20
SN74LVC244APWR
8
1
7
2
6
3
5
4
BR23
47Jx4
BR23
47Jx4
8
1
7
2
6
3
5
4
BR5
47Jx4
BR5
47Jx4
CP45
C121
0.01uF
C121
0.01uF
5
5
4
4
4
3
3
D
C
B
A
MFPC PWB (CPU RM7065C/7965)
MX-7001N  CIRCUIT DIAGRAM / 回路図  2 – 8
SA_JTDI_PU
SA_JTCLK_PU
SA_JTMS_PU
SA_JTRST_PD
GINT
CPU_JTDO
ICU_INT_2.5V
+2.5V_CPU
U_VCCINT
+3.3V
+2.5V_CPU
CPU_VCCINT
+3.3V
CPU_VCCINT
CPU_CORE1.3V
+2.5V
+2.5V
DGND
DGND
+2.5V
+2.5V
SA_RELEASE_2.5V {8}
SA_VALIDIN_2.5V {8}
SA_RDY_2.5V {8}
SA_VALIDOUT_2.5V {8}
SA_PRQST_2.5V {8}
SA_CPUCLK_2.5V {8}
{8}
URST_2.5V {6,8}
COK_2.5V {6,8}
LDRST_2.5V {8}
SA_PACK_2.5V {8}
MODEDAT_3.3V {20}
{8}
nPOF
{32}
nEFI_WU_INT {29}
nRTCINT
{27}
_OC
{29}
nIMGINT
{40}
PCI1_INTA_PU {12,17,23,33}
PCI1_PME {17,23,33}
IF_INT1
{21}
PCI2_INTA_PU {12,16,36,47}
ICU1_INTR {37}
ICUB_INTR {48}
8
7
2
6
3
5
4
1
BC10
0.1uFx4(B)
BC10
8
7
2
6
3
5
4
1
BC12
0.1uFx4(B)
CP35
N1(1005)
R7
4.7KJ
CP41
A
1
B
2
GND
3
Y
4
VCC
5
IC112
SN74LVC1G08DCK
Y
=
AB
8
7
2
6
3
5
4
1
BC20
0.1uFx4(B)
8
7
2
6
3
5
4
1
BC13
0.1uFx4(B)
C831
1uF(1608:B)
C95
10uF(2012)
8
7
2
6
3
5
4
1
BC6
0.1uFx4(B)
C69
0.1uF(B)
8
7
2
6
3
5
4
1
BC5
0.1uFx4(B)
8
7
2
6
3
5
4
1
BC7
0.1uFx4(B)
8
7
2
6
3
5
4
1
BC16
0.1uFx4(B)
CP137
6
1
2
L8
BLM18PG121SN1(1608)
RJ2
X_0J
CP120
CP120
C65
10uF(2012)
CP138
CP134
1
2
L6
BLM21PG220SN1(2012)
8
7
2
6
3
5
4
1
BC4
0.1uFx4(B)
C863
1uF(1608:B)
C830
1uF(1608:B)
8
7
2
6
3
5
4
1
BC15
0.1uFx4(B)
CP34
8
7
2
6
3
5
4
1
BC1
0.1uFx4(B)
BC1
CP129
CP117
R131
4.7KJ
R144 0J
CP141
8
7
2
6
3
5
4
1
BC14
0.1uFx4(B)
CP143
CP121
8
1
7
2
6
3
5
4
BR265
10KJx4
CP119
R125
X_10KJ
8
7
2
6
3
5
4
1
BC2
0.1uFx4(B)
BC2
5
C64
10uF(2012)
VCCIO
A1
VSS
A2
VSS
A3
NC
A4
VSS
A6
VSS
A9
VSS
A12
VSS
A15
NC
A17
VSS
A18
VSS
A19
VCCIO
A20
VSS
B1
VCCIO
B2
VSS
B3
VSS
B4
NC
B5
NC
B16
VSS
B17
VSS
B18
VCCIO
B19
VSS
B20
VSS
C1
VSS
C2
VCCIO
C3
NC
C4
NC
C5
NC
C6
VCCINT
C8
VCCINT
C12
VCCINT
C15
NC
C16
NC
C17
VCCIO
C18
VSS
C19
VSS
C20
NC
D1
VSS
D2
NC
D3
VCCIO
D4
VCCIO
D5
NC
D6
VCCINT
D7
VCCINT
D8
VCCIO
D9
VCCINT
D10
VCCINT
D11
VCCIO
D12
VCCINT
D14
VCCIO
D16
VCCIO
D17
NC
D18
VSS
D19
NC
D20
NC
E2
VCCINT
E3
VCCIO
E4
VCCIO
E17
NC
E18
NC
E19
VSS
F1
VCCINT
F4
VCCINT
F17
VSS
F20
VCCINT
G4
VCCINT
G17
VSS
J1
VCCINT
J3
VCCIO
J4
VCCIO
J17
VSS
J20
VCCINT
L4
VCCINT
L17
VSS
M1
VCCIO
M4
VCCIO
M17
VSS
M20
VCCINT
N3
VCCINT
N17
VCCINT
P4
VSS
R1
NC
R2
VCCINT
R17
VSS
R20
VCCIO
T3
VCCIO
T17
VCCINT
T18
VSS
U2
VCCIO
U4
VCCINT
U8
VCCIO
U9
VCCINT
U10
VCCINT
U11
VCCIO
U12
VCCINT
U14
VCCIO
U16
VCCIO
U17
VSS
U19
VSS
V1
VSS
V2
VCCIO
V3
VCCINT
V8
NC
V9
VCCINT
V11
VCCINT
V14
VCCIO
V18
VSS
V19
VSS
V20
VSS
W1
VCCIO
W2
VSS
W3
VSS
W4
VCCINT
W8
NC
W9
NC
W10
VCCINT
W15
VSS
W17
VSS
W18
VCCIO
W19
VSS
W20
VCCIO
Y1
VSS
Y2
VSS
Y3
VSS
Y6
NC
Y8
VSS
Y9
NC
Y10
VSS
Y12
VSS
Y15
VCCJ
Y16
VSS
Y18
VSS
Y19
VCCIO
Y20
RM7065C/7965 2/2
IC19B
RM7965
RM7965
C96
10uF(2012)
C1079
0.1uF(B)
8
7
2
6
3
5
4
1
BC3
0.1uFx4(B)
8
7
2
6
3
5
4
1
BC8
0.1uFx4(B)
4
8
7
2
6
3
5
4
1
BC18
0.1uFx4(B)
3
5
4
BR43
4.7KJx4
CP132
8
7
2
6
3
5
4
1
BC9
0.1uFx4(B)
BC9
1
1
2
2
G
3
C6
X_PFAD200E336MTE
8
7
2
6
3
5
4
1
BC19
0.1uFx4(B)
8
7
2
6
3
5
4
1
BC11
0.1uFx4(B)
8
7
2
6
3
5
4
1
BC17
0.1uFx4(B)
3
3
2
2
1
1
D
C
B
A
5/52 (7)
MX-7001N  CIRCUIT DIAGRAM / 回路図  2 – 9
SA_SYSAD4
7
SA_SYSAD
6
1
SA_SYSAD2
SA_SYSAD52
SA_SYSAD2
6
SA_SYSAD
6
SA_SYSAD2
7
SA_SYSAD43
SA_SYSAD2
0
SA_SYSAD
60
SA_SYSAD11
SA_SYSAD15
SA_SYSAD45
SA_SYSAD14
SA_SYSAD34
SA_SYSAD4
9
SA_SYSAD1
SA_SYSAD22
SA_SYSAD41
SA_SYSAD
9
SA_SYSAD24
SA_SYSAD18
SA_SYSAD5
0
SA_SYSAD3
7
SA_SYSAD54
SA_SYSAD
6
2
SA_SYSAD3
6
SA_SYSAD55
SA_SYSAD5
6
SA_SYSAD32
SA_SYSAD4
0
SA_SYSAD23
SA_SYSAD4
6
SA_SYSAD44
SA_SYSAD4
SA_SYSAD2
9
SA_SYSAD53
SA_SYSAD51
SA_SYSAD31
SA_SYSAD
6
3
SA_SYSAD48
SA_SYSAD13
SA_SYSAD1
0
SA_SYSAD42
SA_SYSAD1
9
SA_SYSAD
7
SA_SYSAD35
SA_SYSAD38
SA_SYSAD3
9
SA_SYSAD58
SA_SYSAD1
6
SA_SYSAD5
SA_SYSAD5
9
SA_SYSAD1
7
SA_SYSAD
0
SA_SYSAD33
SA_SYSAD28
SA_SYSAD8
SA_SYSAD3
0
SA_SYSAD5
7
SA_SYSAD21
SA_SYSAD3
SA_SYSAD12
SA_SYSAD25
SA_SYSCMD2
SA_SYSCMD8
SA_SYSCMD
0
SA_SYSCMD
7
SA_SYSCMD5
SA_SYSCMD4
SA_SYSCMD
6
SA_SYSCMD3
SA_SYSCMD1
+
2
.5V
+
2
.5V
SA_RELEASE_2
.5V
{7}
SA_RDY_2
.5V
{7}
SA_VALIDIN_2
.5V
{7}
SA_VALIDOUT_2
.5V
{7}
SA_PR
Q
ST_2
.5V
{7}
SA_PACK_2
.5V
{7}
SA_CPUCLK_2
.5V
{7}
SA_INT_2
.5V
{7}
SA_NMI_2
.5V
{7}
SA_VCCOK_2
.5V
{6,7}
SA_COLDRST_2
.5V
{7}
SA_CPURST_2
.5V
{6,7}
SA_SYSAD
[6
3:
0
]
{7}
SA_SYSCMD
[8:
0
]
{7}
R31
7
1
0
KJ
R14
0
22J
cpu_sysad
[6
3
]
C3
0
cpu_sysad
[6
2
]
E31
cpu_sysad
[6
1
]
E25
cpu_sysad
[60
]
E2
7
cpu_sysad
[5
9
]
E2
9
cpu_sysad
[58
]
F31
cpu_sysad
[5
7
]
F23
cpu_sysad
[5
6
]
F2
6
cpu_sysad
[55
]
F2
7
cpu_sysad
[54
]
F2
9
cpu_sysad
[53
]
F34
cpu_sysad
[52
]
F33
cpu_sysad
[51
]
C33
cpu_sysad
[5
0
]
D34
cpu_sysad
[4
9
]
B32
cpu_sysad
[48
]
B3
0
cpu_sysad
[4
7
]
E18
cpu_sysad
[4
6
]
D18
cpu_sysad
[45
]
D2
0
cpu_sysad
[44
]
A18
cpu_sysad
[43
]
B18
cpu_sysad
[42
]
A2
0
cpu_sysad
[41
]
A1
9
cpu_sysad
[4
0
]
F21
cpu_sysad
[3
9
]
E2
0
cpu_sysad
[38
]
E23
cpu_sysad
[3
7
]
C22
cpu_sysad
[3
6
]
D22
cpu_sysad
[35
]
C25
cpu_sysad
[34
]
C2
6
cpu_sysad
[33
]
D2
7
cpu_sysad
[32
]
C2
9
cpu_sysad
[31
]
D3
0
cpu_sysad
[3
0
]
E32
cpu_sysad
[2
9
]
E2
6
cpu_sysad
[28
]
E28
cpu_sysad
[2
7
]
E3
0
cpu_sysad
[2
6
]
F32
cpu_sysad
[25
]
F24
cpu_sysad
[24
]
F25
cpu_sysad
[23
]
F28
cpu_sysad
[22
]
G2
9
cpu_sysad
[21
]
E34
cpu_sysad
[2
0
]
E33
cpu_sysad
[1
9
]
C34
cpu_sysad
[18
]
A32
cpu_sysad
[1
7
]
B31
cpu_sysad
[1
6
]
A31
cpu_sysad
[15
]
C18
cpu_sysad
[14
]
D1
9
cpu_sysad
[13
]
C21
cpu_sysad
[12
]
D21
cpu_sysad
[11
]
F1
9
cpu_sysad
[1
0
]
B1
9
cpu_sysad
[9
]
E1
9
cpu_sysad
[8
]
F22
cpu_sysad
[7
]
F2
0
cpu_sysad
[6
]
E24
cpu_sysad
[5
]
D23
cpu_sysad
[4
]
D24
cpu_sysad
[3
]
D25
cpu_sysad
[2
]
D2
6
cpu_sysad
[1
]
D28
cpu_sysad
[0
]
D2
9
cpu_sysc
m
d
[8
]
A2
7
cpu_sysc
m
d
[7
]
B2
6
cpu_sysc
m
d
[6
]
A2
6
cpu_sysc
m
d
[5
]
B25
cpu_sysc
m
d
[4
]
A25
cpu_sysc
m
d
[3
]
B24
cpu_sysc
m
d
[2
]
A24
cpu_sysc
m
d
[1
]
B23
cpu_sysc
m
d
[0
]
A23
cpu_bus
6
4en(PU)
H3
0
cpu_osrd_en(PU)
J2
9
cpu_cl
ko
A3
0
cpu_vcco
k
A2
9
cpu_rst_s
kip_l(PU)
AP32
cpu_release_l(PU)
A22
cpu_pac
k_l
B22
cpu_validout_l
B2
0
cpu_ready_l
A21
cpu_validin_l
B21
cpu_n
m
i_l
A28
cpu_pr
q
st_l(PU)
F18
cpu_reset_l
B2
9
cpu_intr_l
B2
7
cpu_coldrst_l
B28
fun
k_test
AE32
bisr_test
C4
Im
a
g
e_Syste
m
_C
h
ip
6
/8
SYSAD
I/F
PU
PU
IC21F
Im
a
g
e_Syste
m
_C
h
ip_15
IC21F
R2
07
1
0
KJ
R13
9
22J
8
1
7
2
6
3
5
4
BR4
6
1
0
KJ
x4
8
1
7
2
6
3
5
4
BR4
7
4
7
KJ
x4
R138
22J
5
5
4
43
32
2
1
1
D
D
C
C
B
B
A
A
MFPC
PWB
(S
YST
EM
ASI
C1
-1C
P
U
B
US
)
6/52
(8
)
Page of 127
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