Sharp MX-6201N / MX-7001N (serv.man45) Service Manual ▷ View online
MX-7001N CIRCUIT DIAGRAM / 回路図 2 – 2
DC_ON_OFF_CTL_CORE
DC_ON_OFF_CTL_IO
DC_ON_OFF_CTL_CORE
+5V_IN
DGND
DGND
DGND
DGND
+5V_IN
+5V_IN
+5V_IN
+5V_IN
DGND
DGND
DGND
DGND
+5V_IN
DGND
DGND
+1.8V
DGND
or LQH32CN2R2M33L
C1075
10uF(2012)
10uF(2012)
GND
1
VDD
2
CT
3
VOUT
4
IC1
BU4240F
C1072
22pF(CH)
22pF(CH)
C22
X_1000pF
F
C17
0.01uF
R903
267KF
267KF
CP718
CP142
BP26
C803
1000pF
1000pF
F
BP28
GND
1
VDD
2
CT
3
VOUT
4
IC2
BU4238F
C1074
10uF(2012)
C24
1uF(1608:B)
1uF(1608:B)
R700
47KJ
47KJ
C19
0.01uF
R901
267KF
R20
4.7KJ
4.7KJ
BP27
C21
0.01uF
CP26
CP18
1
2
L65
LQH32CN2R2M53L
LQH32CN2R2M53L
BP25
BP29
C18
0.01uF
C1073
1uF(1608:B)
R21
4.7KJ
4.7KJ
R902
267KF
CP136
CP17
SW
3
GND
2
RUN
1
VIN
4
FB
5
IC106
LTC3406ES5
C802
1000pF
1000pF
F
CP717
C993
0.1uF(B)
CP22
C20
1uF(1608:B)
1uF(1608:B)
3
3
2
2
1
1
D
C
B
A
1/52 (3)
MX-7001N CIRCUIT DIAGRAM / 回路図 2 – 3
MAINCLK
CLK33BASE
+3.3V
DGND
DGND
+3.3V
DGND
DGND
+3.3V
+3.3V
DGND
+3.3V
DGND
DGND
DGND
+3.3V
DGND
IMG_OCCLKI {41}
IMG_OBCLKI {41}
Down -1.9%
CP53
OE
1
GND
2
OUT
3
VDD
4
X14
SG9001JC(64.2000MHz/-1.5%down)
CP62
GP3
CP42
CP29
R46
22J
CP46
GP12
CP64
CP37
OE
1
GND
2
OUT
3
VDD
4
X6
SG9001JC(58.000MHz/-1.5%down)
CP47
R31
CP27
R51
47J
R24
10J
10J
R30
CP30
REFIN
1
VDD
4
OUTA2
3
OUTA1
2
OUTB2
7
OUTB1
6
GND
5
S2
8
S1
9
OUTB3
10
OUTB4
11
GND
12
VDD
13
OUTA3
14
OUTA4
15
CLKOUT
16
IC107
CY23S09SXC1T
C25
0.1uF(B)
CP52
1
2
3
X3
16.600MHz(CSTCE-V-L)
16.600MHz(CSTCE-V-L)
CP31
C873
0.1uF(B)
0.1uF(B)
GP2
CP204
R97
22J
22J
R43
22J
R48
S1
3
FRSEL
6
XIN/CLK
1
SSCLK
5
S0
4
VSS
2
VDD
7
XOUT
8
IC3
CY25812SXC
IC3
CP36
GP13
CP33
R731
22J
GP1
R22
470J
470J
C29
0.1uF(
0.1uF(
CP28
C36
7pF
7pF
C50
0.1uF(B)
C30
0.1uF(B)
0.1uF(B)
R49
GP11
5
5
4
4
3
3
D
C
B
A
MFPC PWB (
GLOBAL CLOCK 1
)
MX-7001N CIRCUIT DIAGRAM / 回路図 2 – 4
DGND
+3.3V
DGND
DGND
+3.3V
+3.3V
DGND
DGND
+3.3V
DGND
SA_MST_CLK {13}
CLOCK3333 {43,51}
IF_PCI1_CLK {23}
PCI1_EXTCLK {33}
ICUSYSCLK33_1 {38}
ICUBSYSCLK33_1 {49}
SA_PCI2_CLK {12}
IDE_PCI2_CLK {16}
IMGSYSCLK33
{40}
SA_PCI1_CLK {12}
MAC_PCI1_CLK {17}
ICU_PCI2_CLK {36}
PCI2_EXTCLK {47}
ICU_SOCLK
{36}
R26
33J
33J
C31
0.1uF(B)
0.1uF(B)
C374
7pF(CH)
7pF(CH)
CP50
CP55
CP40
R31
33J
R27
33J
33J
CP44
R30
33J
R94
33J
R29
33J
R2
33J
CP32
CP43
CP49
C32
0.1uF(B)
0.1uF(B)
R48
22J
CP54
R32
33J
R33
33J
R28
33J
CP56
C29
0.1uF(B)
0.1uF(B)
CP39
C36
7pF(CH)
7pF(CH)
REFIN
1
VDD
4
OUTA2
3
OUTA1
2
OUTB2
7
OUTB1
6
GND
5
S2
8
S1
9
OUTB3
10
OUTB4
11
GND
12
VDD
13
OUTA3
14
OUTA4
15
CLKOUT
16
IC5
CY23S09SXC1T
R49
22J
CP205
3
3
2
2
1
1
D
C
B
A
2/52 (4)
MX-7001N CIRCUIT DIAGRAM / 回路図 2 – 5
CLK5
0
CLKUARTBASE
DGND
+
3
.3V
DGND
+
3
.3V
DGND
+
3
.3V
+
3
.3V
DGND
DGND
+
3
.3V
DGND
+
3
.3V
DGND
+
3
.3V
DGND
DGND
+
3
.3V
+
3
.3V
+
3
.3V
DGND
+
3
.3V
DGND
SMIC_CLK
{13
}
IF_SYSCLK
{2
0}
SA_UART_CLK
{13
}
IF_UART_CLK
{2
0}
IBVSYNCB
{41
}
SEGOVSYNC_N_P
{48
}
VSYNC_RESET
{4
0}
VSYNC_SET
{4
0}
Do
w
n-
1
.5
%
Center
+
/-
0.9%
1
2
3
X1
0
12
.5
00
MH
z(CSTCE-G-L)
C1
07
8
0.
1uF(B)
C1
07
8
CP8
0
R
69
4
70
J
CP
6
8
C4
9
0.
1uF(B)
R
7
5
33J
R
9
1
1
0
J
R
9
54
7
J
S1
3
FRSEL
6
XIN/CLK
1
SSCLK
5
S
0
4
VSS
2
VDD
7
XOUT
8
IC8
CY25811SXC
CP
7
2
CP84
CP83
CP82
R
99
1
0
J
1
2
3
X15
14
.7
4
6
MH
z(CSTCE-V-L)
NC
1
A
2
GND
3
Y
4
VCC
5
IC1
0
8
SN
7
4LVC1G
0
4DCK
Y=/A
CP
66
CP
70
CP
7
3
R
7
33
3
J
NC
1
A
2
GND
3
Y
4
VCC
5
IC1
09
SN
7
4LVC1G
0
4DCK
Y=/A
CP88
8
CP
76
D1
2
CK1
3
Q
1
5
Q
B1
6
VCC
14
GND
7
S1
4
R1
1
D2
12
CK2
11
S2
1
0
R2
13
Q
2
9
Q
B2
8
IC12
SN
7
4LVC
7
4APWR
CP
7
8
C2
6
0.
1uF(B)
C1
077
0.
1uF(B)
C1
076
0.
1uF(B)
CP
7
5
S1
3
FRSEL
6
XIN/CLK
1
SSCLK
5
S
0
4
VSS
2
VDD
7
XOUT
8
IC
7
CY25814SXC
IC
7
CP
77
CP
CP
77
CP
69
R84
5
6
J
4
CP8
66
R
79
33J
C2
7
0.
1uF(B)
GP14
CP85
5
NC
1
A
2
GND
3
Y
4
VCC
5
Y=/A
IC11
0
SN
7
4LVC1G
0
4DCK
GP15
CP81
GP5
CP
79
CP
67
GP4
R8
7
4
70
J
5
5
4
4
43
32
2
D
D
C
C
B
B
MFPC
PWB
(GL
OB
AL
C
LOC
K
2)
3/52
(5)
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