DOWNLOAD Sharp DV-720H (serv.man19) Service Manual ↓ Size: 204.52 KB | Pages: 21 in PDF or view online for FREE

Model
DV-720H (serv.man19)
Pages
21
Size
204.52 KB
Type
PDF
Document
Service Manual
Brand
Device
DVD / IC Function List
File
dv-720h-sm19.pdf
Date
PREV: Sharp DV-720H (serv.man18) Service Manual

Sharp DV-720H (serv.man19) Service Manual ▷ View online

17
DV-720S/DV-720S(K)
DV-720H
10. IC FUNCTION LIST
10-1. IC301 IX1461GE
RF PRE AMP
Pin No.
Terminal name
I/O
Operation function
1
EIN
I
RF signal input. Input of RF signal output of optical pickup.
2
GND1
–
Ground
3
S/DUAL
I
Single layer/dual layer selection signal input.
4
AIN
I
RF signal input. Input of RF signal output of optical pickup.
5
BIN
I
RF signal input. Input of RF signal output of optical pickup.
6
DIN
I
RF signal input. Input of RF signal output of optical pickup.
7
CIN
I
RF signal input. Input of RF signal output of optical pickup.
8
VrefIN
I
Reference voltage input. (2.1V)
9
FIN
I
RF signal input. Input of RF signal output of optical pickup.
10
GAINsel1
I
Amp gain selection input 1.
11
VCC1
–
Power terminal. (5.0V)
12
GAINsel2
I
Amp gain selection input 2.
13
FOUT
O
RF signal output. Input RF signal is current-voltage-converted and output.
14
EOUT
O
RF signal output. Input RF signal is current-voltage-converted and output.
15
COUT
O
RF signal output. Input RF signal is current-voltage-converted and output.
16
DOUT
O
RF signal output. Input RF signal is current-voltage-converted and output.
17
BOUT
O
RF signal output. Input RF signal is current-voltage-converted and output.
18
AOUT
O
RF signal output. Input RF signal is current-voltage-converted and output.
19
VCC2
–
Power terminal. (5.0V)
20
RFPOUT
O
Data read signal output. The same phase as MIXIN.
21
RFNOUT
O
Data read signal output. Reverse phase with respect to MIXIN.
22
MIXIN
I
Data read signal input.
23
MIXOUT
O
Data read signal output.
24
GND2
–
Ground
• Mode selection table
GAINsel1 (Terminal 10)
GAINsel2 (Terminal 12)
Amp gain
L
L
+6dB
H, OPEN
L
-2dB
L
H, OPEN
+2dB
H, OPEN
H, OPEN
-6dB
Amp. gain selection
Layer
S/DSEL (Terminal 3)
Amp gain
Single
L, OPEN
0dB
Dual
H
+10dB
Single layer/dual layer selection
• Block Diagram
24
23
22
21
20
19
18
17
16
15
14
13
1
9
8
7
6
5
4
3
2
10
12
11
MIX
EIN
DIN
BIN
AIN
S/DUAL
GND1
FIN
VrefIN
CIN
COUT
FOUT
VCC1
GAINsel1
GAINsel2
RFPOUT
VCC2
AOUT
BOUT
DOUT
EOUT
RFNOUT
GND2
MIXOUT
MIXIN
DV-720S/DV-720S(K)
DV-720H
18
10-2. IC302 IX1517GE
RF PROCESSOR
Pin No. Terminal name
I/O
Operation function
Terminal DC Voltage(TYP.)
Remarks
1
GND
–
GND terminal.
–
2
P2TP
I
TE+input (CD)
VrA
3
P2TN
I
TE–input (CD)
VrA
4
LDO2
O
Drive ouput
–
5
MDI2
I
Monitor input
–
6
VrA
O
Analog VREF
2.1[V]
7
VrD
O
Digital VREF
–
Vdd 1/2
8
Vdd
I
Power terminal
4.2V (3.3V)
9
DPAC
–
DPD AC combination capacity 1
–
10
DPBD
–
DPD AC combination capacity 2
–
11
DPD1
–
DPD integral capacity 1
–
12
DPD2
–
DPD integral capacity 2
–
13
SCB
I
Control line (Bit clock)
2.2[V]
14
SCL
I
Control line (Latch signal)
2.2[V]
15
SCD
I
Control line (Sirial Data)
2.2[V]
16
VRCK
I
Reference clock input
2.3[V]
When frequency is increased, the
filters excepting the servo LPF are
shifted to high frequency side.
17
VCKF
–
Capacity for time constant adjustment
–
18
VccP
–
Power terminal
–
19
LVL
O
Servo addition output
Vrd x (1/2)
20
TEO
O
TE output
VrD
21
FEO
O
FE output
VrD
22
DFTN
I
DPD difect
–
Low DPD output: Mute
23
VccS
–
Power terminal (servo)
–
24
RPZ
O
RF ripple center voltage
VrD
25
RPO
O
RF ripple output
VrD
26
RPB
O
RF ripple bottom
–
27
RPP
O
RF ripple peak
–
28
RFO
O
Equalizing RF output
2.3[V]
29
NC
–
NC terminal
–
To be connected to GND
30
NC
–
NC terminal
–
To be connected to GND
31
VccR
–
Power terminal (RF)
–
32
DPDB
I
Pit depth adjustment
VrD
When D PDB is raised, the A/B
side delay increases.
33
TEB
I
TE balance
VrD
When TEB is raised, the TP side
gain increases and the A+C side
delay increases.
34
FEB
I
FE balance
VrD
When FEB is raised, the A+C (FP)
side gain increases.
35
PSC
I
VRCK frequency division ON/OFF
–
High: Frequency division OFF
36
Vcc2
–
Power terminal
–
37
NC
–
NC terminal
VrD
To be connected to VrD, or to GND
through C
38
EQD
I
Group delay correction
VrD
When EQD is raised, the group
delay increases at the right side.
39
GND2
–
GND terminal.
–
40
RFDC
–
DC feedback capacity
–
41
RFA
O
RF total addition output
2.2[V]
42
EQB
I
Boost adjustment
VrD
When EQB is raised, the boost increases.
43
EQF
I
Frequency adjustment
VrD
When EQF is raised, shift to the
high frequency side occurs.
44
MDI1
I
Monitor input
–
45
LDO1
O
Drive output
–
46
P1TN
I
TE–input (DVD)
VrA
47
P1TP
I
TE+input (DVD)
VrA
19
DV-720S/DV-720S(K)
DV-720H
Pin No. Terminal name
I/O
Operation function
Terminal DC Voltage(TYP.)
Remarks
48
NC
–
NC terminal
–
To be connected to GND
49
P1FN
I
FE–input (DVD)
VrA
50
P1FP
I
FE+input (DVD)
VrA
51
LDP1
I
APC polarity 1
–
Positive polarity when this terminal
is connected to Vcc.
52
P1DI
I
D input (DVD)
53
P1CI
I
C input (DVD)
VrA
54
P1BI
I
B input (DVD)
VrA
55
P1AI
I
A input (DVD)
VrA
56
GNDR
–
GND terminal (RF)
–
57
LDP2
I
APC polarity 2
–
Positive polarity when this terminal
is connected to Vcc.
58
P2AI
I
A input (CD)
VrA
59
P2BI
I
B input (CD)
VrA
60
P2CI
I
C input (CD)
VrA
61
P2DI
I
D input (CD)
VrA
62
GNDS
–
GND terminal (Servo)
–
63
P2FP
I
FE+input (CD)
VrA
64
P2FN
I
FE–input (CD)
VrA
• Block Diagram
P1FN
P1FP
LDP1
P1DI
P1CI
P1BI
P1AI
GNDR
LDP2
P2AI
P2BI
P2CI
P2DI
GNDS
P2FP
P2FN
DPDB
VccR
NC
NC
RFO
RPP
RPB
RPO
RPZ
VccS
DFTN
FEO
TEO
LVL
VccP
VCKF
NC
P1TP
P1TN
LDO1
MDI1
EQF
EQB
RFA
RFDC
GND2
EQD
NC
Vcc2
PSC
FEB
TEB
GND
P2TP
P2TN
LDO2
MDI2
VrA
VrD
Vdd
DPAC
DPBD
DPD1
DPD2
SCB
SCL
SCD
VRCK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
APC1
sel-RF
R-gain
Adjust
EQ
F-gain
Adjust
F-gain
Adjust
RF Ripple
creation
FE creation
DPDTE
creation
FE-gain
Adjust
TE-gain
Adjust
Level detect
T-gain
Adjust
3BTE creation
APC2
B U S
Time
constant 
adjustment
sel-PD
sel-PD
sel-PD
mode-TE
sel-FE
sel-IC
sel-TE
sel-DPD
sel-LVL
DV-720S/DV-720S(K)
DV-720H
20
10-3. IC401 IX1690GE
FRONT END ENGINE
• Block Diagram
Clock
Gen
Auto-
slicer
ADC
        x6
DAC
        x2
PWM
        x8
GPIO
       x16
PWC
Timer
PROM
OAK
DSP
Scan ICE I/F
PRAM
XRAM
CPU I/F
INTC
(CPU)
INTC
(DSP)
CLV
YRAM
System Clock
DSP Clock
CRPLL
Readin
CD
I/F
Host
I/F
Host
CPU
DVD I/F
Audio DAC I/F
IEC958 I/F
ECC
EDO DRAM
(4/8Mbits)
Micon
RAM
intr
Motorola/Intel Bus
x10 bus
intr
intr
intr
intr
intr
intr
intr
Internal bus
27MHz
clock
RF data
Focus err.
Tracking err.
TOT
RF Ripple
RF ref. voltage
RFZ
Focus drive
Tracking drive
Slad control
Spindle drive
EQ control
etc.
Track count
RF comm.
Gain cntl.
Status input
etc.
ICPS2
IVCO
LP2
PLS1P
PLS2N
ISINKOUT
ICPS
INPUTX
COFFSET
VBIAS
FILT1
FILT2
CRVDD
CRVSS
 DRAM8MP
ADCIN[5:0]
ATPP
ATPM
VREFMIN
COMPVREF
IBIAS
ADCVDD[1:0]
ADCVSS[1:0]
DACOUT[1:0]
DACVDD
DACVSS
PWM[7:0]
GPIOP[15:0]
PWC
FSDATAP
SCLKP
HDATP[7:0]
HADRP[9:0]
HIFM
HRD
HWRN
HCSN
HWATN
HDTACKN
HINTN
20
26
25
23
22
15
24
21
19
18
16
17
27
28
134
1-4, 7-8
175
176
5
174
6
10, 173
9, 172
14, 13
11
12
162-169
144-159
141
36
37
117-124
105-114
133
132
131
130
127
126
125
92
85
88
86
87
45
48
46
47
93-98, 73-82
62-70
61
102
101
100
99
136
38
51-58
42
41
40
39
91
35
137
138
140
139
135
34
33
32
31
*1
*2
PLL1TDENP
PLL1REFP
PLL1TDP
PLL1VDD
PLL1VSS
PLL2REFP
PLL2TDP
PLL2VDD
PLL2VSS
DDATP[15:0]
DADRP[8:0]
A9RP
WRN
RASN
UCASN
LCASN
SICEENP
SREQ
SDATP[7:0]
SERR
SSTRP/LRCLKP
SSST/DACLKP
SVAL/ADOP
OVCLKP
DDOP
SCANMODP
SCANENP
IDDTN
ICPTNUN
TESTP
SCLKRSTN
MRSTN
DSPRSTIN
DSPRSTON
DVDD[12:0]
DVSS[12:0]
RF
interface
(15)
PLL
interface
(9)
DRAM
interface
(31)
Source
Decoder
interface
(14)
SPDIF
(1)
Reset/Test
interface
(9)
Digital
Power
Supply
(26)
Audio
DAC
interface
(4)
ADC
interface
(15)
DAC
interface
(4)
Servo
Digital I/O
(27)
Host CPU
interface
(25)
L64060
DVD-Player
Front-End
Engine
*1: 30, 43, 50, 59, 71, 83, 90, 103, 115, 128, 142, 160, 170pin
*2: 29, 44, 49, 60, 72, 84, 89, 104, 116, 129, 143, 161, 171pin
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  • Disassembly, troubleshooting, maintenance, adjustment, installation and setup instructions.
  • Schematics, Circuit, Wiring and Block diagrams.
  • Printed wiring boards (PWB) and printed circuit boards (PCB).
  • Exploded View and Parts List.

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