Sharp UP-5900 (serv.man8) Service Manual ▷ View online
UP-5900VS
CIRCUIT DESCRIPTION
5 – 11
SLOTOCC#
(S.E.P.P. only)
(S.E.P.P. only)
O
SLOTOCC# is defined to allow a system design to detect the presence of a terminator card or processor in a SC242
connector. This pin is not a signal; rather, it is a short to VSS. Combined with the VID combination of VID[4:0]= 11111 ,
a system can determine if a SC242 connector is occupied, and whether a processor core is present. The states and
values for determining the type of cartridge in the SC242 connector is shown below.
SC242 Occupation Truth Table
connector. This pin is not a signal; rather, it is a short to VSS. Combined with the VID combination of VID[4:0]= 11111 ,
a system can determine if a SC242 connector is occupied, and whether a processor core is present. The states and
values for determining the type of cartridge in the SC242 connector is shown below.
SC242 Occupation Truth Table
SLP#
I
The SLP# (Sleep) signal, when asserted in Stop-Grant state, causes processors to enter the Sleep state. During Sleep
state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still
operating.
Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertions of the
SLP#, STPCLK#, and RESET# signals while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and
returns to Stop-Grant state, restarting its internal clock signals to the bus and APIC processor core units.
state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still
operating.
Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertions of the
SLP#, STPCLK#, and RESET# signals while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and
returns to Stop-Grant state, restarting its internal clock signals to the bus and APIC processor core units.
SMI#
I
The SMI# (System Management Interrupt) signal is asserted asynchronously by system logic. On accepting a System
Management Interrupt, processors save the current state and enter System Management Mode (SMM). An SMI
Acknowledge transaction is issued, and the processor begins program execution from the SMM handler.
Management Interrupt, processors save the current state and enter System Management Mode (SMM). An SMI
Acknowledge transaction is issued, and the processor begins program execution from the SMM handler.
STPCLK#
I
The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a low power Stop-Grant state. The pro-
cessor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core
units except the bus and APIC units. The processor continues to snoop bus transactions and may latch interrupts while
in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units, resumes execu-
tion, and services any pending interrupt. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an
asynchronous input.
cessor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core
units except the bus and APIC units. The processor continues to snoop bus transactions and may latch interrupts while
in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units, resumes execu-
tion, and services any pending interrupt. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an
asynchronous input.
TCK
I
The TCK (Test Clock) signal provides the clock input for the Intel Celeron processor Test Access Port.
TDI
I
The TDI (Test Data In) signal transfers serial test data into the processor. TDI provides the serial input needed for
JTAG specification support.
JTAG specification support.
TDO
O
The TDO (Test Data Out) signal transfers serial test data out of the processor. TDO provides the serial output needed
for JTAG specification support.
for JTAG specification support.
TESTHI (S.E.P.P. only)
I
THERMDN
O
Thermal Diode p-n junction. Used to calculate core temperature.
THERMDP
I
Thermal Diode p-n junction. Used to calculate core temperature.
THERMTRIP#
O
The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well
above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution
when the junction temperature exceeds approximately 135°C. This is signaled to the system by the THERMTRIP#
(Thermal Trip) pin. Once activated, the signal remains latched, and the processor stopped, until RESET# goes active.
There is no hysteresis built into the thermal sensor itself; as long as the die temperature drops below the trip level, a
RESET# pulse will reset the processor and execution will continue. If the temperature has not dropped below the trip
level, the processor will reassert THERMTRIP# and remain stopped. The system designer should not act upon THER-
MTRIP# until after the RESET# input is deasserted. Until this time, the THERMTRIP# is indeterminate.
above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution
when the junction temperature exceeds approximately 135°C. This is signaled to the system by the THERMTRIP#
(Thermal Trip) pin. Once activated, the signal remains latched, and the processor stopped, until RESET# goes active.
There is no hysteresis built into the thermal sensor itself; as long as the die temperature drops below the trip level, a
RESET# pulse will reset the processor and execution will continue. If the temperature has not dropped below the trip
level, the processor will reassert THERMTRIP# and remain stopped. The system designer should not act upon THER-
MTRIP# until after the RESET# input is deasserted. Until this time, the THERMTRIP# is indeterminate.
TMS
I
The TMS (Test Mode Select) signal is a JTAG specification support signal used by debug tools.
TRDY#
I
The TRDY# (Target Ready) signal is asserted by the target to indicate that it is ready to receive a write or implicit write-
back data transfer. TRDY# must connect the appropriate pins of all system bus agents.
back data transfer. TRDY# must connect the appropriate pins of all system bus agents.
TRST#
I
The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. Intel Celeron processors require this signal to
be driven low during power on Reset. A 680 ohm resistor is the suggested value for a pull down resistor on TRST#.
be driven low during power on Reset. A 680 ohm resistor is the suggested value for a pull down resistor on TRST#.
VCC1.5
(PGA packages only)
(PGA packages only)
I
The VCCCMOS pin provides the CMOS voltage for use by the platform. The 2.5 V must be provided to the VCC2.5
input and 1.5 V must be provided to the VCC1.5 input.
The processor re-routes the 1.5 V input to the VCCCMOS output via the package. The supply for VCC1.5 must be the
same one used to supply VTT.
input and 1.5 V must be provided to the VCC1.5 input.
The processor re-routes the 1.5 V input to the VCCCMOS output via the package. The supply for VCC1.5 must be the
same one used to supply VTT.
VCC2.5
(PGA packages only)
(PGA packages only)
I
The V pin provides the CMOS voltage for use by the platform. The 2.5 V CCCMOS must be provided to the VCC2.5
input and 1.5 V must be provided to the VCC1.5 input.
The processor re-routes the 2.5 V input to the VCCCMOS output via the package.
input and 1.5 V must be provided to the VCC1.5 input.
The processor re-routes the 2.5 V input to the VCCCMOS output via the package.
VCCCMOS
(PGA packages only)
(PGA packages only)
O
The VCCCMOS pin provides the CMOS voltage for use by the platform. The 2.5 V must be provided to the VCC2.5
input and 1.5 V must be provided to the VCC1.5 input.
input and 1.5 V must be provided to the VCC1.5 input.
VCOREDET
(PGA packages only)
(PGA packages only)
O
The VCOREDET signal will float for 2.0 V core processors and will be grounded for Celeron FC-PGA processor with a
1.5V core voltage.
1.5V core voltage.
VID[4:0]
VID[3:0]
(PGA packages only)
VID[3:0]
(PGA packages only)
O
The VID (Voltage ID) pins can be used to support automatic selection of power supply voltages. These pins are not sig-
nals, but are either an open circuit or a short(S.E.P.P.) circuit to VSS on the processor. The combination of opens and
shorts defines the voltage required by the processor. The VID pins are needed to cleanly support voltage specification
variations on Intel Celeron processors.
nals, but are either an open circuit or a short(S.E.P.P.) circuit to VSS on the processor. The combination of opens and
shorts defines the voltage required by the processor. The VID pins are needed to cleanly support voltage specification
variations on Intel Celeron processors.
VREF[7:0]
(PGA packages only)
(PGA packages only)
I
These input signals are used by the AGTL+ inputs as a reference voltage. AGTL+inputs are differential receivers and
will use this voltage to determine whether the signal is a logic high or logic low.
For the FC-PGA package, VREF is typically 2/3 of VTT
will use this voltage to determine whether the signal is a logic high or logic low.
For the FC-PGA package, VREF is typically 2/3 of VTT
Signal
Type
Description
Signal
Value
Status
SLOTOCC#
VID[4:0]
VID[4:0]
SLOTOCC#
VID[4:0]
VID[4:0]
SLOTOCC#
VID[4:0]
VID[4:0]
1
Any value
Any value
0
Anything other than '1111'
Anything other than '1111'
0
1111
1111
SC242 connector not occupied.
Processor with core in SC242
connector.
connector.
Terminator cartridge in SC242
connector (i.e., no core present).
connector (i.e., no core present).
UP-5900VS
CIRCUIT DESCRIPTION
5 – 12
10. CHIPSET (NORTH BRIDGE)
Intel’s 82443BX is used.
10-1. PIN ASSIGHMENTS
10-2. PIN DISCRIPTION1)HOST INTERFACE SIGNALS
1) Host Interface Signals
■
■
■
■
Host Interface Signals
1
2
3
4
5
6
7
8
9
10
11
12
13
A
VSS
AD20
PCIRST#
AD25
AD29
PREQ0#
HD56#
HD62#
HD55#
HD54#
HD49#
HD47#
HD40#
B
VCC
PCLKIN
AD22
AD27
AD28
PHOLD#
HD50#
HD61#
HD63#
HD53#
HD48#
HD42#
HD36#
C
AD19
REFVCC
AD21
C/BE3#
VSS
AD31
PREQ1#
HD52#
VSS
HD60#
HD59#
HD51#
HD44#
D
AD16
AD18
AD17
AD23
AD26
PHLDA#
PGNT1#
PREQ3#
HD58#
PREQ4#
HD46#
HD41#
HD39#
E
IRDY#
FRAME#
VSS
C/BE2#
AD24
AD30
PGNT0#
PGNT3#
PGNT4#
PGNT2#
HD57#
VSS
HD45#
F
SERR#
PLOCK#
DEVSEL#
STOP#
TRDY#
VSS
VCC
VSS
VCC
PREQ2#
G
AD13
AD14
C/BE1#
AD15
PAR
VCC
H
AD8
AD7
AD10
AD12
AD11
VSS
J
AD5
AD6
VSS
C/BE0#
AD9
VCC
K
SBA0
AD1
AD3
AD2
AD4
AD0
L
ST2
ST1
GGNT#
ST0
GREQ#
VCC
VSS
VCC
M
SBA2
SBA1
PIPE#
RBF#
VSS
VSS
VCC
VSS
N
VSS
SBA3
SBSTB
AGPREF
GCLKIN
VCC
VSS
VSS
P
VCC
SBA4
SBA6
SBA5
GCLKO
VCC
VSS
VSS
R
SBA7
GAD31
GAD29
GAD30
VSS
VSS
VCC
VSS
T
GAD27
GAD26
GAD24
GAD25
ADSTB_B
VCC
VSS
VCC
U
GAD23
GC/BE3#
GAD22
GAD21
GAD19
GAD28
V
GAD20
GAD17
VSS
GC/BE2#
GIRDY#
VCC
W
GAD16
GAD18
GFRAME#
GTRDY#
GDEVSEL#
VSS
Y
GSTOP#
GPAR
GAD15
GC/BE1#
GAD14
VCC
AA
GAD13
GAD12
GAD10
GAD11
GAD9
VSS
VCC
VSS
VCC
MECC1
AB
GAD8
GC/BE0#
VSS
GAD7
GAD0
MD34
MD5
MD8
MD9
MD12
MD46
VSS
SCASB#
AC
GAD6
ADSTB_A
GAD5
CLKRUN#
MD32
MD35
MD6
MD39
MD10
MD13
MD47
WEB#
DQMA1
AD
GAD4
GAD3
GAD2
SUSTAT#
VSS
MD3
MD37
MD40
VSS
MD44
MD15
MECC5
DQMA0
AE
VCC
GAD1
WSC#
MD1
MD33
MD4
MD38
MD42
MD11
MD45
MECC0
WEA#
DQMB1
AF
VSS
VCC
BXPWROK
MD0
MD2
MD36
MD7
MD41
MD43
MD14
MECC4
SCASA#
VSS
14
15
16
17
18
19
20
21
22
23
24
25
26
VSS
HD33#
HD31#
HD27#
HD19#
HD20#
HD10#
HD6#
HD3#
HA29#
HA24#
HA22#
VSS
A
HD43#
HD32#
HD29#
HD25#
HD21#
HD18#
HD12#
HD8#
HD0#
CPURST#
HA27#
HA20#
BREQ0#
B
HD37#
HD28#
HD26#
HD22#
VSS
HD17#
HD7#
HD5#
VSS
HA26#
HA28#
HA23#
HA21#
C
HD34#
HD35#
HD30#
HD24#
HD16#
HD15#
HD14#
HD4#
HD1#
HA31#
HA25#
HA18#
HA19#
D
HD38#
VSS
GTLREFB
HD23#
HD13#
HD11#
HD9#
HD2#
HA30#
HA15#
VSS
HA17#
HA16#
E
VTTB
VCC
VSS
VCC
VSS
HA11#
HA12#
HA13#
HA14#
HA8#
F
VCC
HA10#
HA5#
HA7#
HA3#
HA9#
G
VSS
HA4#
HA6#
BNR#
HTRDY#
BPRI#
H
VCC
HREQ0#
HREQ1#
VSS
HREQ4#
DEFER#
J
ADS#
HLOCK#
DRDY#
HREQ2#
HREQ3#
RS0#
K
VCC
VSS
VCC
HITM#
DBSY#
HIT#
RS2#
RS1#
L
VSS
VCC
VSS
VSS
GTLREFA
VTTA
TESTIN#
CRESET#
M
VSS
VSS
VCC
VCC
HCLKIN
VSS
MD31
VCC
N
VSS
VSS
VCC
NC
MD30
MD62
MD63
VSS
P
VSS
VCC
VSS
VSS
MD60
MD28
MD29
MD61
R
VCC
VSS
VCC
MD25
MD26
MD57
MD58
MD27
T
MD59
MD54
MD24
MD23
MD55
MD56
U
VCC
MD51
MD52
VSS
MD53
MD22
V
VSS
MD50
MD18
MD19
MD21
MD20
W
VCC
MECC7
MD48
MD16
MD17
MD49
Y
SRASB#
VCC
VSS
VCC
VSS
DQMA6
MECC2
DQMA7
MECC6
MECC3
AA
CSA0#
VSS
MAA1
MAB3#
MAB6#
MAB7#
MAB10
DCLKO
NC
CSB5#
VSS
VSS
DQMA3
AB
DQMA5
CSA3#
MAB1#
MAA3
MAA7
MAA8
MAB9#
MAA12
CKE0
CKE4
CSB3#
DQMA2#
CSB4#
AC
DQMB5
CSA4#
MAB0#
MAB2#
VSS
MAB5#
MAA10
MAB12#
VSS
CKE3
CSB1#
DCLKWR
CSB2#
AD
DQMA4
CSA2#
CSA5#
MAA2
MAB4#
MAA5
MAA9
MAB11#
NC
NC
CKE2
CSB0#
VCC
AE
VCC
CSA1#
SRASA#
MAA0
MAA4
MAA6
MAB8#
MAA11
MAB13
CKE1
CKE5
MAA13
VSS
AF
Name
Type
Description
CPURST#
O
GTL+
CPU Reset. The CPURST# pin is an output from the 82443BX. The 82443BX generates this signal based on the
PCIRST# input (from PIIX4E) and also the SUSTAT# pin in mobile mode. The CPURST# allows the CPUs to begin
execution in a known state.
PCIRST# input (from PIIX4E) and also the SUSTAT# pin in mobile mode. The CPURST# allows the CPUs to begin
execution in a known state.
A[31:3]#
I/O
GTL+
Address Bus: A[31:3]# connect to the CPU address bus. During CPU cycles, the A[31:3]# are inputs.
HD[63:0]#
I/O
GTL+
Host Data: These signals are connected to the CPU data bus. Note that the data signals are inverted on the CPU bus.
ADS#
I/O
GTL+
Address Strobe: The CPU bus owner asserts ADS# to indicate the first of two cycles of a request phase.
BNR#
I/O
GTL+
Block Next Request: Used to block the current request bus owner from issuing a new request. This signal is used to
dynamically control the CPU bus pipeline depth.
dynamically control the CPU bus pipeline depth.
BPRI#
O
GTL+
Priority Agent Bus Request: The 82443BX is the only Priority Agent on the CPU bus. It asserts this signal to obtain the
ownership of the address bus. This signal has priority over symmetric bus requests and will cause the current symmet-
ric owner to stop issuing new transactions unless the HLOCK# signal was asserted.
ownership of the address bus. This signal has priority over symmetric bus requests and will cause the current symmet-
ric owner to stop issuing new transactions unless the HLOCK# signal was asserted.
BREQ0#
O
GTL+
Symmetric Agent Bus Request: Asserted by the 82443BX when CPURST# is asserted to configure the symmetric bus
agents. BREQ0# is negated 2 host clocks after CPURST# is negated.
agents. BREQ0# is negated 2 host clocks after CPURST# is negated.
DBSY#
I/O
GTL+
Data Bus Busy: Used by the data bus owner to hold the data bus for transfers requiring more than one cycle.
DEFER#
O
GTL+
Defer: The 82443BX generates a deferred response as defined by the rules of the 82443BXfs dynamic defer policy.
The 82443BX also uses the DEFER# signal to indicate a CPU retry response.
The 82443BX also uses the DEFER# signal to indicate a CPU retry response.
DRDY#
I/O
GTL+
Data Ready: Asserted for each cycle that data is transferred.
HIT#
I/O
GTL+
Hit: Indicates that a caching agent holds an unmodified version of the requested line.
Also driven in conjunction with HITM# by the target to extend the snoop window.
Also driven in conjunction with HITM# by the target to extend the snoop window.
UP-5900VS
CIRCUIT DESCRIPTION
5 – 13
Note:
1. All of the signals in the host interface are described in the CPU External Bus Specification. The preceding table highlights 82443BX specific uses
of these signals.
■
■
■
■
Host Signals Not supported by the 82443BX
2) DRAM Interface
■
■
■
■
DRAM Interface Signals
HITM#
I/O
GTL+
Hit Modified: Indicates that a caching agent holds a modified version of the requested line and that this agent assumes
responsibility for providing the line. Also driven in conjunction with HIT# to extend the snoop window.
responsibility for providing the line. Also driven in conjunction with HIT# to extend the snoop window.
HLOCK#
I
GTL+
Host Lock: All CPU bus cycles sampled with the assertion of HLOCK# and ADS#, until the negation of HLOCK# must
be atomic, i.e. no PCI or AGP snoopable access to DRAM is allowed when HLOCK# is asserted by the CPU.
be atomic, i.e. no PCI or AGP snoopable access to DRAM is allowed when HLOCK# is asserted by the CPU.
HREQ[4:0]#
I/O
GTL+
Request Command: Asserted during both clocks of request phase. In the first clock, the signals define the transaction
type to a level of detail that is sufficient to begin a snoop request. In the second clock, the signals carry additional infor-
mation to define the complete transaction type. The transactions supported by the 82443BX Host Bridge are defined in
the Host Interface section of this document.
type to a level of detail that is sufficient to begin a snoop request. In the second clock, the signals carry additional infor-
mation to define the complete transaction type. The transactions supported by the 82443BX Host Bridge are defined in
the Host Interface section of this document.
HTRDY#
I/O
GTL+
Host Target Ready: Indicates that the target of the CPU transaction is able to enter the data transfer phase.
RS[2:0]#
I/O
GTL+
Response Signals: Indicates type of response according to the following the table:
RS[2:0] Response type
RS[2:0] Response type
000
Idle state
001
Retry response
010
Deferred response
011
Reserved (not driven by 82443BX)
100
Hard Failure (not driven by 82443BX)
101
No data response
110
Implicit Writeback
111
Normal data response
Signal
Function
Not Supported By 82443BX
A[35:32]#
Address
Extended addressing (over 4 GB)
AERR#
Address Parity Error
Parity protection on address bus
AP[1:0]#
Address Parity
Parity protection on address bus
BINIT#
Bus Initialization
Checking for bus protocol violation and protocol recovery mechanism
DEP[7:0]#
Data Bus ECC/Parity
Enhanced data bus integrity
IERR#
Internal Error
Direct internal error observation via IERR# pin
INIT#
Soft Reset
Implemented by PIIX4E, BIST supported by external logic.
BERR#
Bus Error
Unrecoverable error without a bus protocol violation
RP#
Request Parity
Parity protection on ADS# and PREQ[4:0]#
RSP#
Response Parity Signal
Parity protection on RS[2:0]#
Name
Type
Description
Name
Type
Description
RASA[5:0]#
/CSA[5:0]#
/CSA[5:0]#
RASB[5:0]#
/CSB[5:0]#
/CSB[5:0]#
O
CMOS
Row Address Strobe (EDO): These signals are used to latch the row address on the MAxx lines into the DRAMs. Each
signal is used to select one DRAM row.
These signals drive the DRAM array directly without any external buffers.
Chip Select (SDRAM): For the memory row configured with SDRAM these pins perform the function of selecting the
particular SDRAM components during the active state.
Note that there are 2 copies of RAS# per physical memory row to improve the loading.
signal is used to select one DRAM row.
These signals drive the DRAM array directly without any external buffers.
Chip Select (SDRAM): For the memory row configured with SDRAM these pins perform the function of selecting the
particular SDRAM components during the active state.
Note that there are 2 copies of RAS# per physical memory row to improve the loading.
CKE[3:2]
/CSA[7:6]#
/CSA[7:6]#
CKE[5:4]
/CSB[7:6]#
/CSB[7:6]#
O
CMOS
Clock Enable: In mobile mode, SDRAM Clock Enable is used to signal a self-refresh or power-down command to an
SDRAM array when entering system suspend. CKE is also used to dynamically power down inactive SDRAM rows.
This CKE function is not supported with Registered DIMMs.
Chip Select (SDRAM): These pins perform the function of selecting the particular SDRAM components during the
active state.
Note that there are 2 copies of CS# per physical memory row to reduce the loading.
SDRAM array when entering system suspend. CKE is also used to dynamically power down inactive SDRAM rows.
This CKE function is not supported with Registered DIMMs.
Chip Select (SDRAM): These pins perform the function of selecting the particular SDRAM components during the
active state.
Note that there are 2 copies of CS# per physical memory row to reduce the loading.
CASA[7:0]#
/DQMA[7:0]
/DQMA[7:0]
O
CMOS
Column Address Strobe A-side (EDO): The CASA[7:0]# signals are used to latch the column address on the MA[13:0]
lines into the DRAMs of the A half of the memory array. These are active low signals that drive the DRAM array directly
without external buffering.
Input/Output Data Mask A-side (SDRAM): These pins control A half of the memory array and act as synchronized out-
put enables during read cycles and as a byte enables during write cycles.
lines into the DRAMs of the A half of the memory array. These are active low signals that drive the DRAM array directly
without external buffering.
Input/Output Data Mask A-side (SDRAM): These pins control A half of the memory array and act as synchronized out-
put enables during read cycles and as a byte enables during write cycles.
CASB[1,5]#
/DQMB[1,5]
/DQMB[1,5]
O
CMOS
Column Address Strobe B-side (EDO) / Input/Output Data Mask B-side (SDRAM): The same function as a correspond-
ing signals for A side. These signals are used to reduce the loading in an ECC configuration
ing signals for A side. These signals are used to reduce the loading in an ECC configuration
UP-5900VS
CIRCUIT DESCRIPTION
5 – 14
3) PCI Interface (Primary)
■
■
■
■
Primary PCI Interface Signals
GCKE/CKE1
O
CMOS
Global CKE (SDRAM): Global CKE is used in a 4 DIMM configuration requiring power down mode for the SDRAM.
External logic must be used to implement this function.
SDRAM Clock Enable (CKE1): In mobile mode, SDRAM Clock Enable is used to signal a self-refresh or power-down
command to an SDRAM array when entering system suspend. CKE is also used to dynamically power down inactive
SDRAM rows. The combination of SDRAMPWR (SDRAM register) and MMCONFIG (DRAMC register) determine the
functioning of the CKE signals. Refer to the DRAMC register for more details.
External logic must be used to implement this function.
SDRAM Clock Enable (CKE1): In mobile mode, SDRAM Clock Enable is used to signal a self-refresh or power-down
command to an SDRAM array when entering system suspend. CKE is also used to dynamically power down inactive
SDRAM rows. The combination of SDRAMPWR (SDRAM register) and MMCONFIG (DRAMC register) determine the
functioning of the CKE signals. Refer to the DRAMC register for more details.
SRAS[B,A]#
O
CMOS
SDRAM Row Address Strobe (SDRAM): The SRAS[B,A]# signals are multiple copies of the same logical SRASx sig-
nal (for loading purposes) used to generate SDRAM command encoded on SRASx/SCASx/WE signals.
nal (for loading purposes) used to generate SDRAM command encoded on SRASx/SCASx/WE signals.
CKE0/FENA
O
CMOS
SDRAM Clock Enable 0 (CKE0). In mobile mode, CKE0 SDRAM Clock Enable is used to signal a self-refresh or
power-down command to an SDRAM array when entering system suspend. CKE is also used to dynamically power
down inactive SDRAM rows.
FET Enable (FENA): In a 4 DIMM configuration. FENA is used to select the proper MD path through the FET switches.
power-down command to an SDRAM array when entering system suspend. CKE is also used to dynamically power
down inactive SDRAM rows.
FET Enable (FENA): In a 4 DIMM configuration. FENA is used to select the proper MD path through the FET switches.
SCAS[B,A]#
O
CMOS
SDRAM Column Address Strobe (SDRAM): The SCAS[B,A]# signals are multiple copies of the same logical SCASx
signal (for loading purposes) used to generate SDRAM command encoded on SRASx/SCASx/WE signals.
signal (for loading purposes) used to generate SDRAM command encoded on SRASx/SCASx/WE signals.
MAA[13:0]
MAB[12:11]#
MAB[13,10]
MAB[9:0]#
MAB[12:11]#
MAB[13,10]
MAB[9:0]#
O
CMOS
Memory Address(EDO/SDRAM): MAA[13:0] and MAB[13:0]# are used to provide the multiplexed row and column
address to DRAM. There are two sets of MA signals which drive a max. of 2 DIMMs each. MAA[12:11,9:0] are inverted
copies of MAB[12:11,9:0]#. MAA[13,10] and MAB[13,10] are identical copies.
Each MAA/MAB[13:0] line has a programmable buffer strength to optimize for different signal loading conditions.
address to DRAM. There are two sets of MA signals which drive a max. of 2 DIMMs each. MAA[12:11,9:0] are inverted
copies of MAB[12:11,9:0]#. MAA[13,10] and MAB[13,10] are identical copies.
Each MAA/MAB[13:0] line has a programmable buffer strength to optimize for different signal loading conditions.
WEA#
WEB#
WEB#
O
CMOS
Write Enable Signal (EDO/SDRAM): WE# is asserted during writes to DRAM.
The WE# lines have a programmable buffer strength to optimize for different signal loading conditions.
The WE# lines have a programmable buffer strength to optimize for different signal loading conditions.
MD [63:0]
I/O
CMOS
Memory Data (EDO/SDRAM): These signals are used to interface to the DRAM data bus.
MECC[7:0]
I/O
CMOS
Memory ECC Data (EDO/SDRAM): These signals carry Memory ECC data during access to DRAM.
Name
Type
Description
Name
Type
Description
AD[31:0]
I/O
PCI
PCI Address/Data: These signals are connected to the PCI address/data bus.
Address is driven by the 82443BX with FRAME# assertion, data is driven or received in the following clocks. When the
82443BX acts as a target on the PCI Bus, the AD[31:0] signals are inputs and contain the address during the first clock
of FRAME# assertion and input data (writes) or output data (reads) on subsequent clocks.
Address is driven by the 82443BX with FRAME# assertion, data is driven or received in the following clocks. When the
82443BX acts as a target on the PCI Bus, the AD[31:0] signals are inputs and contain the address during the first clock
of FRAME# assertion and input data (writes) or output data (reads) on subsequent clocks.
DEVSEL#
I/O
PCI
Device Select: Device select, when asserted, indicates that a PCI target device has decoded its address as the target
of the current access. The 82443BX asserts DEVSEL# based on the DRAM address range or AGP address range
being accessed by a PCI initiator. As an input it indicates whether any device on the bus has been selected.
of the current access. The 82443BX asserts DEVSEL# based on the DRAM address range or AGP address range
being accessed by a PCI initiator. As an input it indicates whether any device on the bus has been selected.
FRAME#
I/O
PCI
Frame: FRAME# is an output when the 82443BX acts as an initiator on the PCI Bus.
FRAME# is asserted by the 82443BX to indicate the beginning and duration of an access. The 82443BX asserts
FRAME# to indicate a bus transaction is beginning.
While FRAME# is asserted, data transfers continue. When FRAME# is negated, the transaction is in the final data
phase. FRAME# is an input when the 82443BX acts as a PCI target. As a PCI target, the 82443BX latches the C/
BE[3:0]# and the AD[31:0] signals on the first clock edge on which it samples FRAME# active.
FRAME# is asserted by the 82443BX to indicate the beginning and duration of an access. The 82443BX asserts
FRAME# to indicate a bus transaction is beginning.
While FRAME# is asserted, data transfers continue. When FRAME# is negated, the transaction is in the final data
phase. FRAME# is an input when the 82443BX acts as a PCI target. As a PCI target, the 82443BX latches the C/
BE[3:0]# and the AD[31:0] signals on the first clock edge on which it samples FRAME# active.
IRDY#
I/O
PCI
Initiator Ready: IRDY# is an output when 82443BX acts as a PCI initiator and an input when the 82443BX acts as a
PCI target. The assertion of IRDY# indicates the current PCI Bus initiator’s ability to complete the current data phase of
the transaction.
PCI target. The assertion of IRDY# indicates the current PCI Bus initiator’s ability to complete the current data phase of
the transaction.
C/BE[3:0]#
I/O
PCI
Command/Byte Enable: PCI Bus Command and Byte Enable signals are multiplexed on the same pins. During the
address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase C/BE[3:0]# are used as
byte enables. The byte enables determine which byte lanes carry meaningful data. PCI Bus command encoding and
types are listed below.
C/BE[3:0]# Command Type
address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase C/BE[3:0]# are used as
byte enables. The byte enables determine which byte lanes carry meaningful data. PCI Bus command encoding and
types are listed below.
C/BE[3:0]# Command Type
0000 Interrupt Acknowledge
0001 Special Cycle
0010 I/O Read
0011 I/O Write
0100 Reserved
0101 Reserved
0110 Memory Read
0111 Memory Write
1000 Reserved
1001 Reserved
1010 Configuration Read
1011 Configuration Write
1100 Memory Read Multiple
1101 Reserved (Dual Address Cycle)
1110 Memory Read Line
1111 Memory Write and Invalidate
0001 Special Cycle
0010 I/O Read
0011 I/O Write
0100 Reserved
0101 Reserved
0110 Memory Read
0111 Memory Write
1000 Reserved
1001 Reserved
1010 Configuration Read
1011 Configuration Write
1100 Memory Read Multiple
1101 Reserved (Dual Address Cycle)
1110 Memory Read Line
1111 Memory Write and Invalidate
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