Sharp UP-5900 (serv.man8) Service Manual ▷ View online
UP-5900VS
CIRCUIT DESCRIPTION
5 – 23
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CPU INTERFACE SIGNALS
IRQ 12/M
I
INTERRUPT REQUEST 12. In addition to providing the standard interrupt function as described in the pin descrip-
tion for IRQ[3:7,9:11,14:15], this pin can also be programmed to provide the mouse interrupt function.
When the mouse interrupt function is selected, a low to high transition on this signal is latched by PIIX4E and an
INTR is generated to the CPU as IRQ12. An internal IRQ12 interrupt continues to be generated until a Reset or an I/
O read access to address 60h (falling edge of IOR#) is detected.
tion for IRQ[3:7,9:11,14:15], this pin can also be programmed to provide the mouse interrupt function.
When the mouse interrupt function is selected, a low to high transition on this signal is latched by PIIX4E and an
INTR is generated to the CPU as IRQ12. An internal IRQ12 interrupt continues to be generated until a Reset or an I/
O read access to address 60h (falling edge of IOR#) is detected.
PIRQ[A:D]#
I/OD
PCI
PROGRAMMABLE INTERRUPT REQUEST. The PIRQx# signals are active low, level sensitive, shareable interrupt
inputs. They can be individually steered to ISA interrupts IRQ [3:7,9:12,14:15]. The USB controller uses PIRQD# as
its output signal.
inputs. They can be individually steered to ISA interrupts IRQ [3:7,9:12,14:15]. The USB controller uses PIRQD# as
its output signal.
SERIRQ/
GPI7
GPI7
I/O
SERIAL INTERRUPT REQUEST. Serial interrupt input decoder, typically used in conjunction with the Distributed
DMA protocol.
If not using serial interrupts, this pin can be used as a general-purpose input.
DMA protocol.
If not using serial interrupts, this pin can be used as a general-purpose input.
Name
Type
Description
A20M#
OD
ADDRESS 20 MASK. PIIX4E asserts A20M# to the CPU based on combination of Port 92 Register, bit 1
(FAST_A20), and A20GATE input signal.
During Reset: High-Z
(FAST_A20), and A20GATE input signal.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
CPURST
OD
CPU RESET. PIIX4E asserts CPURST to reset the CPU. PIIX4E asserts CPURST during power-up and when a
hard reset sequence is initiated through the RC register.
CPURST is driven inactive a minimum of 2 ms after PWROK is driven active.
CPURST is driven active for a minimum of 2 ms when initiated through the RC register. The inactive edge of
CPURST is driven synchronously to the rising edge of PCICLK. If a hard reset is initiated through the RC register,
PIIX4E resets its internal registers (in both core and suspend wells) to their default state.
This signal is active high for Pentium processor and active-low for Pentium II processor as determined by CONFIG1
signal.
For values During Reset, After Reset, and During POS, see the Suspend/Resume and Resume Control Signaling
section.
hard reset sequence is initiated through the RC register.
CPURST is driven inactive a minimum of 2 ms after PWROK is driven active.
CPURST is driven active for a minimum of 2 ms when initiated through the RC register. The inactive edge of
CPURST is driven synchronously to the rising edge of PCICLK. If a hard reset is initiated through the RC register,
PIIX4E resets its internal registers (in both core and suspend wells) to their default state.
This signal is active high for Pentium processor and active-low for Pentium II processor as determined by CONFIG1
signal.
For values During Reset, After Reset, and During POS, see the Suspend/Resume and Resume Control Signaling
section.
FERR#
I
NUMERIC COPROCESSOR ERROR. This pin functions as a FERR# signal supporting coprocessor errors. This
signal is tied to the coprocessor error signal on the CPU. If FERR# is asserted, PIIX4E generates an internal IRQ13
to its interrupt controller unit. PIIX4E then asserts the INT output to the CPU. FERR# is also used to gate the
IGNNE# signal to ensure that IGNNE# is not asserted to the CPU unless FERR# is active.
signal is tied to the coprocessor error signal on the CPU. If FERR# is asserted, PIIX4E generates an internal IRQ13
to its interrupt controller unit. PIIX4E then asserts the INT output to the CPU. FERR# is also used to gate the
IGNNE# signal to ensure that IGNNE# is not asserted to the CPU unless FERR# is active.
IGNNE#
OD
IGNORE NUMERIC EXCEPTION. This signal is connected to the ignore numeric exception pin on the CPU.
IGNNE# is only used if the PIIX4E coprocessor error reporting function is enabled. If FERR# is active, indicating a
coprocessor error, a write to the Coprocessor Error Register (F0h) causes the IGNNE# to be asserted.
IGNNE# remains asserted until FERR# is negated. If FERR# is not asserted when the Coprocessor Error Register
is written, the IGNNE# signal is not asserted.
During Reset: High-Z
IGNNE# is only used if the PIIX4E coprocessor error reporting function is enabled. If FERR# is active, indicating a
coprocessor error, a write to the Coprocessor Error Register (F0h) causes the IGNNE# to be asserted.
IGNNE# remains asserted until FERR# is negated. If FERR# is not asserted when the Coprocessor Error Register
is written, the IGNNE# signal is not asserted.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
INIT
OD
INITIALIZATION. INIT is asserted in response to any one of the following conditions.
When the System Reset bit in the Reset Control Register is reset to 0 and the Reset CPU bit toggles from 0 to 1,
PIIX4E initiates a soft reset by asserting INIT. PIIX4E also asserts INIT if a Shut Down Special cycle is decoded on
the PCI Bus, if the RCIN# signal is asserted, or if a write occurs to Port 92h, bit 0. When asserted, INIT remains
asserted for approximately 64 PCI clocks before being negated.
This signal is active high for Pentium processor and active-low for Pentium II processor as determined by CONFIG1
signal.
Pentium Processor:
During Reset: Low
When the System Reset bit in the Reset Control Register is reset to 0 and the Reset CPU bit toggles from 0 to 1,
PIIX4E initiates a soft reset by asserting INIT. PIIX4E also asserts INIT if a Shut Down Special cycle is decoded on
the PCI Bus, if the RCIN# signal is asserted, or if a write occurs to Port 92h, bit 0. When asserted, INIT remains
asserted for approximately 64 PCI clocks before being negated.
This signal is active high for Pentium processor and active-low for Pentium II processor as determined by CONFIG1
signal.
Pentium Processor:
During Reset: Low
After Reset: Low
During POS: Low
Pentium II Processor:
During Reset: High
During Reset: High
After Reset: High
During POS: High
INTR
OD
CPU INTERRUPT. INTR is driven by PIIX4E to signal the CPU that an interrupt request is pending and needs to be
serviced. It is asynchronous with respect to SYSCLK or PCICLK and is always an output. The interrupt controller
must be programmed following PCIRST# to ensure that INTR is at a known state.
During Reset: Low
serviced. It is asynchronous with respect to SYSCLK or PCICLK and is always an output. The interrupt controller
must be programmed following PCIRST# to ensure that INTR is at a known state.
During Reset: Low
After Reset: Low
During POS: Low
NMI
OD
NON-MASKABLE INTERRUPT. NMI is used to force a nonmaskable interrupt to the CPU. PIIX4E generates an
NMI when either SERR# or IOCHK# is asserted, depending on how the NMI Status and Control Register is pro-
grammed. The CPU detects an NMI when it detects a rising edge on NMI. After the NMI interrupt routine processes
the interrupt, the NMI status bits in the NMI Status and Control Register are cleared by software. The NMI interrupt
routine must read this register to determine the source of the interrupt. The NMI is reset by setting the corresponding
NMI source enable/disable bit in the NMI Status and Control Register. To enable NMI interrupts, the two NMI
enable/disable bits in the register must be set to 0, and the NMI mask bit in the NMI Enable/Disable and Real Time
Clock Address Register must be set to 0. Upon PCIRST#, this signal is driven low.
During Reset: Low
NMI when either SERR# or IOCHK# is asserted, depending on how the NMI Status and Control Register is pro-
grammed. The CPU detects an NMI when it detects a rising edge on NMI. After the NMI interrupt routine processes
the interrupt, the NMI status bits in the NMI Status and Control Register are cleared by software. The NMI interrupt
routine must read this register to determine the source of the interrupt. The NMI is reset by setting the corresponding
NMI source enable/disable bit in the NMI Status and Control Register. To enable NMI interrupts, the two NMI
enable/disable bits in the register must be set to 0, and the NMI mask bit in the NMI Enable/Disable and Real Time
Clock Address Register must be set to 0. Upon PCIRST#, this signal is driven low.
During Reset: Low
After Reset: Low
During POS: Low
SLP#
OD
SLEEP. This signal is output to the Pentium II processor in order to put it into Sleep state. For Pentium processor it
is a No Connect.
During Reset: High-Z
is a No Connect.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
Name
Type
Description
UP-5900VS
CIRCUIT DESCRIPTION
5 – 24
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CLOCKING SIGNALS
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IDE SIGNALS
SMI#
OD
SYSTEM MANAGEMENT INTERRUPT. SMI# is an active low synchronous output that is asserted by PIIX4E in
response to one of many enabled hardware or software events. The CPU recognizes the falling edge of SMI# as the
highest priority interrupt in the system, with the exception of INIT, CPURST, and FLUSH.
During Reset: High-Z
response to one of many enabled hardware or software events. The CPU recognizes the falling edge of SMI# as the
highest priority interrupt in the system, with the exception of INIT, CPURST, and FLUSH.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
STPCLK#
OD
STOP CLOCK. STPCLK# is an active low synchronous output that is asserted by PIIX4E in response to one of
many hardware or software events. STPCLK# connects directly to the CPU and is synchronous to PCICLK.
During Reset: High-Z
many hardware or software events. STPCLK# connects directly to the CPU and is synchronous to PCICLK.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
Name
Type
Description
CLK48
I
48-MHZ CLOCK. 48-MHz clock used by the internal USB host controller. This signal may be stopped during sus-
pend modes.
pend modes.
PCICLK
I
FREE-RUNNING PCI CLOCK. A clock signal running at 30 or 33 MHz, PCICLK provides timing for all transactions
on the PCI Bus. All other PCI signals are sampled on the rising edge of PCICLK, and all timing parameters are
defined with respect to this edge. Because many of the circuits in PIIX4E run off the PCI clock, this signal MUST be
kept active, even if the PCI bus clock is not active.
on the PCI Bus. All other PCI signals are sampled on the rising edge of PCICLK, and all timing parameters are
defined with respect to this edge. Because many of the circuits in PIIX4E run off the PCI clock, this signal MUST be
kept active, even if the PCI bus clock is not active.
OSC
I
14.31818-MHZ CLOCK. Clock signal used by the internal 8254 timer. This clock signal may be stopped during sus-
pend modes.
pend modes.
RTCX1,
RTCX2
RTCX2
I/O
RTC CRYSTAL INPUTS: These connected directly to a 32.768-kHz crystal. External capacitors are required. These
clock inputs are required even if the internal RTC is not being used.
clock inputs are required even if the internal RTC is not being used.
SUSCLK
O
SUSPEND CLOCK. 32.768-kHz output clock provided to the Host-to-PCI bridge used for maintenance of DRAM
refresh. This signal is stopped during Suspend-to-Disk and Soft Off modes. For values During Reset, After Reset,
and During POS, see the Suspend/Resume and Resume Control Signaling section.
refresh. This signal is stopped during Suspend-to-Disk and Soft Off modes. For values During Reset, After Reset,
and During POS, see the Suspend/Resume and Resume Control Signaling section.
SYSCLK
O
ISA SYSTEM CLOCK. SYSCLK is the reference clock for the ISA bus. It drives the ISA bus directly. The SYSCLK is
generated by dividing PCICLK by 4. The SYSCLK frequencies supported are 7.5 MHz and 8.33 MHz. For PCI
accesses to the ISA bus, SYSCLK may be stretched low to synchronize BALE falling to the rising edge of SYSCLK.
During Reset: Running
generated by dividing PCICLK by 4. The SYSCLK frequencies supported are 7.5 MHz and 8.33 MHz. For PCI
accesses to the ISA bus, SYSCLK may be stretched low to synchronize BALE falling to the rising edge of SYSCLK.
During Reset: Running
After Reset: Running
During POS: Low
Name
Type
Description
PDA[2:0]
O
PRIMARY DISK ADDRESS[2:0]. These signals indicate which byte in either the ATA command block or control
block is being addressed.
If the IDE signals are configured for Primary and Secondary, these signals are connected to the corresponding sig-
nals on the Primary IDE connector.
If the IDE signals are configured for Primary 0 and Primary 1, these signals are used for the Primary 0 connector.
During Reset: High-Z
block is being addressed.
If the IDE signals are configured for Primary and Secondary, these signals are connected to the corresponding sig-
nals on the Primary IDE connector.
If the IDE signals are configured for Primary 0 and Primary 1, these signals are used for the Primary 0 connector.
During Reset: High-Z
After Reset: Undefined
1
During POS: PDA
PDCS1#
O
PRIMARY DISK CHIP SELECT FOR 1F0H-1F7H RANGE. For ATA command register block. If the IDE signals are
configured for Primary and Secondary, this output signal is connected to the corresponding signal on the Primary
IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
During Reset: High
configured for Primary and Secondary, this output signal is connected to the corresponding signal on the Primary
IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
During Reset: High
After Reset: High
During POS: High
PDCS3#
O
PRIMARY DISK CHIP SELECT FOR 3F0-3F7 RANGE. For ATA control register block. If the IDE signals are config-
ured for Primary and Secondary, this output signal is connected to the corresponding signal on the Primary IDE con-
nector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
During Reset: High
ured for Primary and Secondary, this output signal is connected to the corresponding signal on the Primary IDE con-
nector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
During Reset: High
After Reset: High
During POS: High
PDD[15:0]
I/O
PRIMARY DISK DATA[15:0]. These signals are used to transfer data to or from the IDE device. If the IDE signals
are configured for Primary and Secondary, these signals are connected to the corresponding signals on the Primary
IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
During Reset: High-Z
are configured for Primary and Secondary, these signals are connected to the corresponding signals on the Primary
IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
During Reset: High-Z
After Reset: Undefined
1
During POS: PDD
PDDACK#
O
PRIMARY DMA ACKNOWLEDGE. This signal directly drives the IDE device DMACK# signal. It is asserted by
PIIX4E to indicate to IDE DMA slave devices that a given data transfer cycle (assertion of PDIOR# or PDIOW#) is a
DMA data transfer cycle. This signal is used in conjunction with the PCI bus master IDE function. It is not associated
with any AT compatible DMA channel.
If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding signal on
the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
During Reset: High
PIIX4E to indicate to IDE DMA slave devices that a given data transfer cycle (assertion of PDIOR# or PDIOW#) is a
DMA data transfer cycle. This signal is used in conjunction with the PCI bus master IDE function. It is not associated
with any AT compatible DMA channel.
If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding signal on
the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
During Reset: High
After Reset: High
During POS: High
Name
Type
Description
UP-5900VS
CIRCUIT DESCRIPTION
5 – 25
PDDREQ
I
PRIMARY DISK DMA REQUEST. This input signal is directly driven from the IDE device DMARQ signal. It is
asserted by the IDE device to request a data transfer, and used in conjunction with the PCI bus master IDE function.
It is not associated with any AT compatible DMA channel.
If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding signal on
the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
asserted by the IDE device to request a data transfer, and used in conjunction with the PCI bus master IDE function.
It is not associated with any AT compatible DMA channel.
If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding signal on
the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
PDIOR#
O
PRIMARY DISK IO READ. In normal IDE this is the command to the IDE device that it may drive data onto the
PDD[15:0] lines. Data is latched by PIIX4E on the negation edge of PDIOR#. The IDE device is selected either by
the ATA register file chip selects (PDCS1#, PDCS3#) and the PDA[2:0] lines, or the IDE DMA slave arbitration sig-
nals (PDDACK#).
In an Ultra DMA/33 read cycle, this signal is used as DMARDY# which is negated by the PIIX4E to pause Ultra
DMA/33 transfers. In an Ultra DMA/33 write cycle, this signal is used as the STROBE signal, with the drive latching
data on rising and falling edges of STROBE.
If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding signal on
the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
During Reset: High
PDD[15:0] lines. Data is latched by PIIX4E on the negation edge of PDIOR#. The IDE device is selected either by
the ATA register file chip selects (PDCS1#, PDCS3#) and the PDA[2:0] lines, or the IDE DMA slave arbitration sig-
nals (PDDACK#).
In an Ultra DMA/33 read cycle, this signal is used as DMARDY# which is negated by the PIIX4E to pause Ultra
DMA/33 transfers. In an Ultra DMA/33 write cycle, this signal is used as the STROBE signal, with the drive latching
data on rising and falling edges of STROBE.
If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding signal on
the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
During Reset: High
After Reset: High
During POS: High
PDIOW#
O
PRIMARY DISK IO WRITE. In normal IDE mode, this is the command to the IDE device that it may latch data from
the PDD[15:0] lines. Data is latched by the IDE device on the negation edge of PDIOW#. The IDE device is selected
either by the ATA register file chip selects (PDCS1#, PDCS3#) and the PDA[2:0] lines, or the IDE DMA slave arbi-
tration signals (PDDACK#).
For Ultra DMA/33 mode, this signal is used as the STOP signal, which is used to terminate an Ultra DMA/33 trans-
action. If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding
signal on the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
During Reset: High
the PDD[15:0] lines. Data is latched by the IDE device on the negation edge of PDIOW#. The IDE device is selected
either by the ATA register file chip selects (PDCS1#, PDCS3#) and the PDA[2:0] lines, or the IDE DMA slave arbi-
tration signals (PDDACK#).
For Ultra DMA/33 mode, this signal is used as the STOP signal, which is used to terminate an Ultra DMA/33 trans-
action. If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding
signal on the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
During Reset: High
After Reset: High
During POS: High-Z
PIORDY
I
PRIMARY IO CHANNEL READY. In normal IDE mode, this input signal is directly driven by the corresponding IDE
device IORDY signal.
In an Ultra DMA/33 read cycle, this signal is used as STROBE, with the PIIX4E latching data on rising and falling
edges of STROBE. In an Ultra DMA/33 write cycle, this signal is used as the DMARDY# signal which is negated by
the drive to pause Ultra DMA/33 transfers.
If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding signal on
the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
This is a Schmitt triggered input.
device IORDY signal.
In an Ultra DMA/33 read cycle, this signal is used as STROBE, with the PIIX4E latching data on rising and falling
edges of STROBE. In an Ultra DMA/33 write cycle, this signal is used as the DMARDY# signal which is negated by
the drive to pause Ultra DMA/33 transfers.
If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding signal on
the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
This is a Schmitt triggered input.
SDA[2:0]
O
SECONDARY DISK ADDRESS[2:0]. These signals indicate which byte in either the ATA command block or control
block is being addressed. If the IDE signals are configured for Primary and Secondary, these signals are connected
to the corresponding signals on the Secondary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, these signals are used for the Primary Slave
connector.
During Reset: High-Z
block is being addressed. If the IDE signals are configured for Primary and Secondary, these signals are connected
to the corresponding signals on the Secondary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, these signals are used for the Primary Slave
connector.
During Reset: High-Z
After Reset: Undefined
1
During POS: SDA
SDCS1#
O
SECONDARY CHIP SELECT FOR 170H-177H RANGE. For ATA command register block. If the IDE signals are
configured for Primary and Secondary, this output signal is connected to the corresponding signal on the Secondary
IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, these signals are used for the Primary Slave
connector.
During Reset: High
configured for Primary and Secondary, this output signal is connected to the corresponding signal on the Secondary
IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, these signals are used for the Primary Slave
connector.
During Reset: High
After Reset: High
During POS: High
SDCS3#
O
SECONDARY CHIP SELECT FOR 370H-377H RANGE. For ATA control register block. If the IDE signals are con-
figured for Primary and Secondary, this output signal is connected to the corresponding signal on the Secondary
IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, these signals are used for the Primary Slave
connector.
During Reset: High
figured for Primary and Secondary, this output signal is connected to the corresponding signal on the Secondary
IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, these signals are used for the Primary Slave
connector.
During Reset: High
After Reset: High
During POS: High-Z
SDD[15:0]
I/O
SECONDARY DISK DATA[15:0]. These signals are used to transfer data to or from the IDE device. If the IDE sig-
nals are configured for Primary and Secondary, these signals are connected to the corresponding signals on the
Secondary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, these signals are used for the Primary Slave
connector.
During Reset: High-Z
nals are configured for Primary and Secondary, these signals are connected to the corresponding signals on the
Secondary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, these signals are used for the Primary Slave
connector.
During Reset: High-Z
After Reset: Undefined
1
During POS: SDD
Name
Type
Description
UP-5900VS
CIRCUIT DESCRIPTION
5 – 26
Note:
After reset, all undefined signals on the primary channel will default to the same values as the undefined signals on the secondary channel.
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UNIVERSAL SERIAL BUS SIGNALS
SDDACK#
O
SECONDARY DMA ACKNOWLEDGE. This signal directly drives the IDE device DMACK# signal. It is asserted by
PIIX4E to indicate to IDE DMA slave devices that a given data transfer cycle (assertion of SDIOR# or SDIOW#) is a
DMA data transfer cycle. This signal is used in conjunction with the PCI bus master IDE function. It is not associated
with any AT compatible DMA channel.
If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding signal on
the Secondary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, these signals are used for the Primary Slave
connector.
During Reset: High
PIIX4E to indicate to IDE DMA slave devices that a given data transfer cycle (assertion of SDIOR# or SDIOW#) is a
DMA data transfer cycle. This signal is used in conjunction with the PCI bus master IDE function. It is not associated
with any AT compatible DMA channel.
If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding signal on
the Secondary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, these signals are used for the Primary Slave
connector.
During Reset: High
After Reset: High
During POS: High
SDDREQ
I
SECONDARY DISK DMA REQUEST. This input signal is directly driven from the IDE device DMARQ signal. It is
asserted by the IDE device to request a data transfer, and used in conjunction with the PCI bus master IDE function.
It is not associated with any AT compatible DMA channel.
If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding signal on
the Secondary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, these signals are used for the Primary Slave
connector.
asserted by the IDE device to request a data transfer, and used in conjunction with the PCI bus master IDE function.
It is not associated with any AT compatible DMA channel.
If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding signal on
the Secondary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, these signals are used for the Primary Slave
connector.
SDIOR#
O
SECONDARY DISK IO READ. In normal IDE mode, this is the command to the IDE device that it may drive data
onto the SDD[15:0] lines. Data is latched by the PIIX4E on the negation edge of SDIOR#. The IDE device is
selected either by the ATA register file chip selects (SDCS1#, SDCS3#) and the SDA[2:0] lines, or the IDE DMA
slave arbitration signals (SDDACK#).
In an Ultra DMA/33 read cycle, this signal is used as DMARDY# which is negated by the PIIX4E to pause Ultra
DMA/33 transfers. In an Ultra DMA/33 write cycle, this signal is used as the STROBE signal, with the drive latching
data on rising and falling edges of STROBE.
If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding signal on
the Secondary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, these signals are used for the Primary Slave
connector.
During Reset: High
onto the SDD[15:0] lines. Data is latched by the PIIX4E on the negation edge of SDIOR#. The IDE device is
selected either by the ATA register file chip selects (SDCS1#, SDCS3#) and the SDA[2:0] lines, or the IDE DMA
slave arbitration signals (SDDACK#).
In an Ultra DMA/33 read cycle, this signal is used as DMARDY# which is negated by the PIIX4E to pause Ultra
DMA/33 transfers. In an Ultra DMA/33 write cycle, this signal is used as the STROBE signal, with the drive latching
data on rising and falling edges of STROBE.
If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding signal on
the Secondary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, these signals are used for the Primary Slave
connector.
During Reset: High
After Reset: High
During POS: High
SDIOW#
O
SECONDARY DISK IO WRITE. In normal IDE mode, this is the command to the IDE device that it may latch data
from the SDD[15:0] lines. Data is latched by the IDE device on the negation edge of SDIOW#. The IDE device is
selected either by the ATA register file chip selects (SDCS1#, SDCS3#) and the SDA[2:0] lines, or the IDE DMA
slave arbitration signals (SDDACK#).
In read and write cycles this signal is used as the STOP signal, which is used to terminate an Ultra DMA/33 transac-
tion.
If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding signal on
the Secondary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, these signals are used for the Primary Slave
connector.
During Reset: High
from the SDD[15:0] lines. Data is latched by the IDE device on the negation edge of SDIOW#. The IDE device is
selected either by the ATA register file chip selects (SDCS1#, SDCS3#) and the SDA[2:0] lines, or the IDE DMA
slave arbitration signals (SDDACK#).
In read and write cycles this signal is used as the STOP signal, which is used to terminate an Ultra DMA/33 transac-
tion.
If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding signal on
the Secondary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, these signals are used for the Primary Slave
connector.
During Reset: High
After Reset: High
During POS: High
SIORDY
I
SECONDARY IO CHANNEL READY. In normal IDE mode, this input signal is directly driven by the corresponding
IDE device IORDY signal.
In an Ultra DMA/33 read cycle, this signal is used as STROBE, with the PIIX4E latching data on rising and falling
edges of STROBE. In an Ultra DMA write cycle, this signal is used as the DMARDY# signal which is negated by the
drive to pause Ultra DMA/33 transfers.
If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding signal on
the Secondary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, these signals are used for the Primary Slave
connector.
This is a Schmitt triggered input.
IDE device IORDY signal.
In an Ultra DMA/33 read cycle, this signal is used as STROBE, with the PIIX4E latching data on rising and falling
edges of STROBE. In an Ultra DMA write cycle, this signal is used as the DMARDY# signal which is negated by the
drive to pause Ultra DMA/33 transfers.
If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding signal on
the Secondary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, these signals are used for the Primary Slave
connector.
This is a Schmitt triggered input.
Name
Type
Description
Name
Type
Description
OC[1:0]#
I
OVER CURRENT DETECT. These signals are used to monitor the status of the USB power supply lines. The corre-
sponding USB port is disabled when its over current signal is asserted.
sponding USB port is disabled when its over current signal is asserted.
USBP0+,
USBP0
USBP0
I/O
SERIAL BUS PORT 0. This signal pair comprises the differential data signal for USB port 0.
During Reset: High-Z
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
USBP1+,
USBP1
USBP1
I/O
SERIAL BUS PORT 1. This signal pair comprises the differential data signal for USB port 1.
During Reset: High-Z
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
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