Sharp UP-5900 (serv.man8) Service Manual ▷ View online
UP-5900VS
CIRCUIT DESCRIPTION
5 – 19
Note:
All of the signals in the host interface are described in the Pentium Processor data sheet. The preceding table highlights PIIX4E specific uses of these
signals.
signals.
■
■
■
■
ISA BUS INTERFACE
IDSEL
I
INITIALIZATION DEVICE SELECT. IDSEL is used as a chip select during PCI configuration read and write cycles.
PIIX4E samples IDSEL during the address phase of a transaction. If IDSEL is sampled active, and the bus com-
mand is a configuration read or write, PIIX4E responds by asserting DEVSEL# on the next cycle.
PIIX4E samples IDSEL during the address phase of a transaction. If IDSEL is sampled active, and the bus com-
mand is a configuration read or write, PIIX4E responds by asserting DEVSEL# on the next cycle.
IRDY#
I/O
INITIATOR READY. IRDY# indicates PIIX4Efs ability, as an Initiator, to complete the current data phase of the
transaction. It is used in conjunction with TRDY#. A data phase is completed on any clock both IRDY# and TRDY#
are sampled asserted.
During a write, IRDY# indicates PIIX4E has valid data present on AD[31:0]. During a read, it indicates PIIX4E is pre-
pared to latch data. IRDY# is an input to PIIX4E when PIIX4E is the Target and an output when PIIX4E is an Initia-
tor. IRDY# remains tristated until driven by PIIX4E as a master.
During Reset: High-Z
transaction. It is used in conjunction with TRDY#. A data phase is completed on any clock both IRDY# and TRDY#
are sampled asserted.
During a write, IRDY# indicates PIIX4E has valid data present on AD[31:0]. During a read, it indicates PIIX4E is pre-
pared to latch data. IRDY# is an input to PIIX4E when PIIX4E is the Target and an output when PIIX4E is an Initia-
tor. IRDY# remains tristated until driven by PIIX4E as a master.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
PAR
O
CALCULATED PARITY SIGNAL. PAR is gevenh parity and is calculated on 36 bits; AD[31:0] plus C/BE[3:0]#.
“Even” parity means that the number of “1”s within the 36 bits plus PAR are counted and the sum is always even.
PAR is always calculated on 36 bits regardless of the valid byte enables. PAR is generated for address and data
phases and is only guaranteed to be valid one PCI clock after the corresponding address or data phase. PAR is
driven and tri-stated identically to the AD[31:0] lines except that PAR is delayed by exactly one PCI clock. PAR is an
output during the address phase (delayed one clock) for all PIIX4E initiated transactions. It is also an output during
the data phase (delayed one clock) when PIIX4E is the Initiator of a PCI write transaction, and when it is the Target
of a read transaction.
During Reset: High-Z
“Even” parity means that the number of “1”s within the 36 bits plus PAR are counted and the sum is always even.
PAR is always calculated on 36 bits regardless of the valid byte enables. PAR is generated for address and data
phases and is only guaranteed to be valid one PCI clock after the corresponding address or data phase. PAR is
driven and tri-stated identically to the AD[31:0] lines except that PAR is delayed by exactly one PCI clock. PAR is an
output during the address phase (delayed one clock) for all PIIX4E initiated transactions. It is also an output during
the data phase (delayed one clock) when PIIX4E is the Initiator of a PCI write transaction, and when it is the Target
of a read transaction.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
PCIRST#
O
PCI RESET. PIIX4E asserts PCIRST# to reset devices that reside on the PCI bus.
PIIX4E asserts PCIRST# during power-up and when a hard reset sequence is initiated through the RC register.
PCIRST# is driven inactive a minimum of 1 ms after PWROK is driven active. PCIRST# is driven for a minimum of 1
ms when initiated through the RC register. PCIRST# is driven asynchronously relative to PCICLK.
During Reset: Low
PIIX4E asserts PCIRST# during power-up and when a hard reset sequence is initiated through the RC register.
PCIRST# is driven inactive a minimum of 1 ms after PWROK is driven active. PCIRST# is driven for a minimum of 1
ms when initiated through the RC register. PCIRST# is driven asynchronously relative to PCICLK.
During Reset: Low
After Reset: High
During POS: High
PHOLD#
O
PCI HOLD. An active low assertion indicates that PIIX4E desires use of the PCI Bus.
Once the PCI arbiter has asserted PHLDA# to PIIX4E, it may not negate it until PHOLD# is negated by PIIX4E.
PIIX4E implements the passive release mechanism by toggling PHOLD# inactive for one PCICLK.
During Reset: High-Z
Once the PCI arbiter has asserted PHLDA# to PIIX4E, it may not negate it until PHOLD# is negated by PIIX4E.
PIIX4E implements the passive release mechanism by toggling PHOLD# inactive for one PCICLK.
During Reset: High-Z
After Reset: High
During POS: High
PHLDA#
I
PCI HOLD ACKNOWLEDGE. An active low assertion indicates that PIIX4E has been granted use of the PCI Bus.
Once PHLDA# is asserted, it cannot be negated unless PHOLD# is negated first.
Once PHLDA# is asserted, it cannot be negated unless PHOLD# is negated first.
SERR#
I/O
SYSTEM ERROR. SERR# can be pulsed active by any PCI device that detects a system error condition. Upon
sampling SERR# active, PIIX4E can be programmed to generate a non-maskable interrupt (NMI) to the CPU.
During Reset: High-Z
sampling SERR# active, PIIX4E can be programmed to generate a non-maskable interrupt (NMI) to the CPU.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
STOP#
I/O
STOP. STOP# indicates that PIIX4E, as a Target, is requesting an initiator to stop the current transaction. As an Ini-
tiator, STOP# causes PIIX4E to stop the current transaction. STOP# is an output when PIIX4E is a Target and an
input when PIIX4E is an Initiator. STOP# is tri-stated from the leading edge of PCIRST#. STOP# remains tri-stated
until driven by PIIX4E as a slave.
During Reset: High-Z
tiator, STOP# causes PIIX4E to stop the current transaction. STOP# is an output when PIIX4E is a Target and an
input when PIIX4E is an Initiator. STOP# is tri-stated from the leading edge of PCIRST#. STOP# remains tri-stated
until driven by PIIX4E as a slave.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
TRDY#
I/O
TARGET READY. TRDY# indicates PIIX4Efs ability to complete the current data phase of the transaction. TRDY#
is used in conjunction with IRDY#. A data phase is completed when both TRDY# and IRDY# are sampled asserted.
During a read, TRDY# indicates that PIIX4E, as a Target, has place valid data on AD[31:0]. During a write, it indi-
cates PIIX4E, as a Target is prepared to latch data. TRDY# is an input to PIIX4E when PIIX4E is the Initiator and an
output when PIIX4E is a Target.
TRDY# is tri-stated from the leading edge of PCIRST#. TRDY# remains tri-stated until driven by PIIX4E as a slave.
During Reset: High-Z
is used in conjunction with IRDY#. A data phase is completed when both TRDY# and IRDY# are sampled asserted.
During a read, TRDY# indicates that PIIX4E, as a Target, has place valid data on AD[31:0]. During a write, it indi-
cates PIIX4E, as a Target is prepared to latch data. TRDY# is an input to PIIX4E when PIIX4E is the Initiator and an
output when PIIX4E is a Target.
TRDY# is tri-stated from the leading edge of PCIRST#. TRDY# remains tri-stated until driven by PIIX4E as a slave.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
Name
Type
Description
Name
Type
Description
AEN
O
ADDRESS ENABLE. AEN is asserted during DMA cycles to prevent I/O slaves from misinterpreting DMA cycles as
valid I/O cycles. When negated, AEN indicates that an I/O slave may respond to address and I/O commands. When
asserted, AEN informs I/O resources on the ISA bus that a DMA transfer is occurring. This signal is also driven high
during PIIX4E initiated refresh cycles.
During Reset: High-Z
valid I/O cycles. When negated, AEN indicates that an I/O slave may respond to address and I/O commands. When
asserted, AEN informs I/O resources on the ISA bus that a DMA transfer is occurring. This signal is also driven high
during PIIX4E initiated refresh cycles.
During Reset: High-Z
After Reset: Low
During POS: Low
BALE
O
BUS ADDRESS LATCH ENABLE. BALE is asserted by PIIX4E to indicate that the address (SA[19:0], LA[23:17])
and SBHE# signal lines are valid. The LA[23:17] address lines are latched on the trailing edge of BALE. BALE
remains asserted throughout DMA and ISA master cycles.
During Reset: High-Z
and SBHE# signal lines are valid. The LA[23:17] address lines are latched on the trailing edge of BALE. BALE
remains asserted throughout DMA and ISA master cycles.
During Reset: High-Z
After Reset: Low
During POS: Low
IOCHK#/
GPI0
GPI0
I
I/O CHANNEL CHECK. IOCHK# can be driven by any resource on the ISA bus. When asserted, it indicates that a
parity or an uncorrectable error has occurred for a device or memory on the ISA bus. A NMI will be generated to the
CPU if the NMI generation is enabled. If the EIO bus is used, this signal becomes a general purpose input.
parity or an uncorrectable error has occurred for a device or memory on the ISA bus. A NMI will be generated to the
CPU if the NMI generation is enabled. If the EIO bus is used, this signal becomes a general purpose input.
UP-5900VS
CIRCUIT DESCRIPTION
5 – 20
IOCHRDY
I/O
I/O CHANNEL READY. Resources on the ISA Bus negate IOCHRDY to indicate that wait states are required to
complete the cycle. This signal is normally high.
IOCHRDY is an input when PIIX4E owns the ISA Bus and the CPU or a PCI agent is accessing an ISA slave, or dur-
ing DMA transfers. IOCHRDY is output when an external ISA Bus Master owns the ISA Bus and is accessing DRAM
or a PIIX4E register. As a PIIX4E output, IOCHRDY is driven inactive (low) from the falling edge of the ISA com-
mands. After data is available for an ISA master read or PIIX4E latches the data for a write cycle, IOCHRDY is
asserted for 70 ns. After 70 ns, PIIX4E floats IOCHRDY. The 70 ns includes both the drive time and the time it takes
PIIX4E to float IOCHRDY. PIIX4E does not drive this signal when an ISA Bus master is accessing an ISA Bus slave.
During Reset: High-Z
complete the cycle. This signal is normally high.
IOCHRDY is an input when PIIX4E owns the ISA Bus and the CPU or a PCI agent is accessing an ISA slave, or dur-
ing DMA transfers. IOCHRDY is output when an external ISA Bus Master owns the ISA Bus and is accessing DRAM
or a PIIX4E register. As a PIIX4E output, IOCHRDY is driven inactive (low) from the falling edge of the ISA com-
mands. After data is available for an ISA master read or PIIX4E latches the data for a write cycle, IOCHRDY is
asserted for 70 ns. After 70 ns, PIIX4E floats IOCHRDY. The 70 ns includes both the drive time and the time it takes
PIIX4E to float IOCHRDY. PIIX4E does not drive this signal when an ISA Bus master is accessing an ISA Bus slave.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
IOCS16#
I
16-BIT I/O CHIP SELECT. This signal is driven by I/O devices on the ISA Bus to indicate support for 16-bit I/O bus
cycles.
cycles.
IOR#
I/O
I/O READ. IOR# is the command to an ISA I/O slave device that the slave may drive data on to the ISA data bus
(SD[15:0]). The I/O slave device must hold the data valid until after IOR# is negated. IOR# is an output when PIIX4E
owns the ISA Bus. IOR# is an input when an external ISA master owns the ISA Bus.
During Reset: High-Z
(SD[15:0]). The I/O slave device must hold the data valid until after IOR# is negated. IOR# is an output when PIIX4E
owns the ISA Bus. IOR# is an input when an external ISA master owns the ISA Bus.
During Reset: High-Z
After Reset: High
During POS: High
IOW#
I/O
I/O WRITE. IOW# is the command to an ISA I/O slave device that the slave may latch data from the ISA data bus
(SD[15:0]). IOW# is an output when PIIX4E owns the ISA Bus. IOW# is an input when an external ISA master owns
the ISA Bus.
During Reset: High-Z
(SD[15:0]). IOW# is an output when PIIX4E owns the ISA Bus. IOW# is an input when an external ISA master owns
the ISA Bus.
During Reset: High-Z
After Reset: High
During POS: High
LA[23:17]/
GPO[7:1]
GPO[7:1]
I/O
ISA LA[23:17]. LA[23:17] address lines allow accesses to physical memory on the ISA Bus up to 16 Mbytes.
LA[23:17] are outputs when PIIX4E owns the ISA Bus.
The LA[23:17] lines become inputs whenever an ISA master owns the ISA Bus. If the EIO bus is used, these signals
become a general purpose output.
During Reset: High-Z
LA[23:17] are outputs when PIIX4E owns the ISA Bus.
The LA[23:17] lines become inputs whenever an ISA master owns the ISA Bus. If the EIO bus is used, these signals
become a general purpose output.
During Reset: High-Z
After Reset: Undefined
During POS: Last LA/GPO
MEMCS16#
I/O
MEMORY CHIP SELECT 16. MEMCS16# is a decode of LA[23:17] without any qualification of the command signal
lines. ISA slaves that are 16-bit memory devices drive this signal low. PIIX4E ignores MEMCS16# during I/O access
cycles and refresh cycles. MEMCS16# is an input when PIIX4E owns the ISA Bus. PIIX4E drives this signal low dur-
ing ISA master to PCI memory cycles.
During Reset: High-Z
lines. ISA slaves that are 16-bit memory devices drive this signal low. PIIX4E ignores MEMCS16# during I/O access
cycles and refresh cycles. MEMCS16# is an input when PIIX4E owns the ISA Bus. PIIX4E drives this signal low dur-
ing ISA master to PCI memory cycles.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
MEMR#
I/O
MEMORY READ. MEMR# is the command to a memory slave that it may drive data onto the ISA data bus. MEMR#
is an output when PIIX4E is a master on the ISA Bus. MEMR# is an input when an ISA master, other than PIIX4E,
owns the ISA Bus. This signal is also driven by PIIX4E during refresh cycles. For DMA cycles, PIIX4E, as a master,
asserts MEMR#.
During Reset: High-Z
is an output when PIIX4E is a master on the ISA Bus. MEMR# is an input when an ISA master, other than PIIX4E,
owns the ISA Bus. This signal is also driven by PIIX4E during refresh cycles. For DMA cycles, PIIX4E, as a master,
asserts MEMR#.
During Reset: High-Z
After Reset: High
During POS: High
MEMW#
I/O
MEMORY WRITE. MEMW# is the command to a memory slave that it may latch data from the ISA data bus.
MEMW# is an output when PIIX4E owns the ISA Bus.
MEMW# is an input when an ISA master, other than PIIX4E, owns the ISA Bus. For DMA cycles, PIIX4E, as a mas-
ter, asserts MEMW#.
During Reset: High-Z
MEMW# is an output when PIIX4E owns the ISA Bus.
MEMW# is an input when an ISA master, other than PIIX4E, owns the ISA Bus. For DMA cycles, PIIX4E, as a mas-
ter, asserts MEMW#.
During Reset: High-Z
After Reset: High
During POS: High
REFRESH#
I/O
REFRESH. As an output, REFRESH# is used by PIIX4E to indicate when a refresh cycle is in progress. It should be
used to enable the SA[7:0] address to the row address inputs of all banks of dynamic memory on the ISA Bus. Thus,
when MEMR# is asserted, the entire expansion bus dynamic memory is refreshed.
Memory slaves must not drive any data onto the bus during refresh. As an output, this signal is driven directly onto
the ISA Bus. This signal is an output only when PIIX4E DMA refresh controller is a master on the bus responding to
an internally generated request for refresh.
As an input, REFRESH# is driven by 16-bit ISA Bus masters to initiate refresh cycles.
During Reset: High-Z
used to enable the SA[7:0] address to the row address inputs of all banks of dynamic memory on the ISA Bus. Thus,
when MEMR# is asserted, the entire expansion bus dynamic memory is refreshed.
Memory slaves must not drive any data onto the bus during refresh. As an output, this signal is driven directly onto
the ISA Bus. This signal is an output only when PIIX4E DMA refresh controller is a master on the bus responding to
an internally generated request for refresh.
As an input, REFRESH# is driven by 16-bit ISA Bus masters to initiate refresh cycles.
During Reset: High-Z
After Reset: High
During POS: High
RSTDRV
O
RESET DRIVE. PIIX4E asserts RSTDRV to reset devices that reside on the ISA/EIO Bus. PIIX4E asserts this signal
during a hard reset and during power-up.
RSTDRV is asserted during power-up and negated after PWROK is driven active.
RSTDRV is also driven active for a minimum of 1 ms if a hard reset has been programmed in the RC register.
During Reset: High
during a hard reset and during power-up.
RSTDRV is asserted during power-up and negated after PWROK is driven active.
RSTDRV is also driven active for a minimum of 1 ms if a hard reset has been programmed in the RC register.
During Reset: High
After Reset: Low
During POS: Low
SA[19:0]
I/O
SYSTEM ADDRESS[19:0]. These bi-directional address lines define the selection with the granularity of 1 byte
within the 1-Megabyte section of memory defined by the LA[23:17] address lines. The address lines SA[19:17] that
are coincident with LA[19:17] are defined to have the same values as LA[19:17] for all memory cycles.
For I/O accesses, only SA[15:0] are used, and SA[19:16] are undefined. SA[19:0] are outputs when PIIX4E owns
the ISA Bus. SA[19:0] are inputs when an external ISA Master owns the ISA Bus.
During Reset: High-Z
within the 1-Megabyte section of memory defined by the LA[23:17] address lines. The address lines SA[19:17] that
are coincident with LA[19:17] are defined to have the same values as LA[19:17] for all memory cycles.
For I/O accesses, only SA[15:0] are used, and SA[19:16] are undefined. SA[19:0] are outputs when PIIX4E owns
the ISA Bus. SA[19:0] are inputs when an external ISA Master owns the ISA Bus.
During Reset: High-Z
After Reset: Undefined
During POS: Last SA
SBHE#
I/O
SYSTEM BYTE HIGH ENABLE. SBHE# indicates, when asserted, that a byte is being transferred on the upper byte
(SD[15:8]) of the data bus. SBHE# is negated during refresh cycles. SBHE# is an output when PIIX4E owns the ISA
Bus. SBHE# is an input when an external ISA master owns the ISA Bus.
During Reset: High-Z
(SD[15:8]) of the data bus. SBHE# is negated during refresh cycles. SBHE# is an output when PIIX4E owns the ISA
Bus. SBHE# is an input when an external ISA master owns the ISA Bus.
During Reset: High-Z
After Reset: Undefined
During POS: High
SD[15:0]
I/O
SYSTEM DATA. SD[15:0] provide the 16-bit data path for devices residing on the ISA Bus. SD[15:8] correspond to
the high order byte and SD[7:0] correspond to the low order byte. SD[15:0] are undefined during refresh.
During Reset: High-Z
the high order byte and SD[7:0] correspond to the low order byte. SD[15:0] are undefined during refresh.
During Reset: High-Z
After Reset: Undefined
During POS: High-Z
Name
Type
Description
UP-5900VS
CIRCUIT DESCRIPTION
5 – 21
■
■
■
■
X-BUS INTERFACE
SMEMR#
O
STANDARD MEMORY READ. PIIX4E asserts SMEMR# to request an ISA memory slave to drive data onto the
data lines. If the access is below the 1-Mbyte range (00000000h 000FFFFFh) during DMA compatible, PIIX4E mas-
ter, or ISA master cycles, PIIX4E asserts SMEMR#. SMEMR# is a delayed version of MEMR#.
During Reset: High-Z
data lines. If the access is below the 1-Mbyte range (00000000h 000FFFFFh) during DMA compatible, PIIX4E mas-
ter, or ISA master cycles, PIIX4E asserts SMEMR#. SMEMR# is a delayed version of MEMR#.
During Reset: High-Z
After Reset: High
During POS: High
SMEMW#
O
STANDARD MEMORY WRITE. PIIX4E asserts SMEMW# to request an ISA memory slave to accept data from the
data lines. If the access is below the 1-Mbyte range (00000000h 000FFFFFh) during DMA compatible, PIIX4E mas-
ter, or ISA master cycles, PIIX4E asserts SMEMW#. SMEMW# is a delayed version of MEMW#.
During Reset: High-Z
data lines. If the access is below the 1-Mbyte range (00000000h 000FFFFFh) during DMA compatible, PIIX4E mas-
ter, or ISA master cycles, PIIX4E asserts SMEMW#. SMEMW# is a delayed version of MEMW#.
During Reset: High-Z
After Reset: High
During POS: High
ZEROWS#
I
ZERO WAIT STATES. An ISA slave asserts ZEROWS# after its address and command signals have been decoded
to indicate that the current cycle can be shortened. A 16-bit ISA memory cycle can be reduced to two SYSCLKs. An
8-bit memory or I/O cycle can be reduced to three SYSCLKs. ZEROWS# has no effect during 16-bit I/O cycles.
If IOCHRDY is negated and ZEROWS# is asserted during the same clock, then ZEROWS# is ignored and wait
states are added as a function of IOCHRDY.
to indicate that the current cycle can be shortened. A 16-bit ISA memory cycle can be reduced to two SYSCLKs. An
8-bit memory or I/O cycle can be reduced to three SYSCLKs. ZEROWS# has no effect during 16-bit I/O cycles.
If IOCHRDY is negated and ZEROWS# is asserted during the same clock, then ZEROWS# is ignored and wait
states are added as a function of IOCHRDY.
Name
Type
Description
A20GATE
I
ADDRESS 20 GATE. This input from the keyboard controller is logically combined with bit 1 (FAST_A20) of the Port
92 Register, which is then output via the A20M# signal.
92 Register, which is then output via the A20M# signal.
BIOSCS#
O
BIOS CHIP SELECT. This chip select is driven active during read or write accesses to enabled BIOS memory
ranges. BIOSCS# is driven combinatorially from the ISA addresses SA[16:0] and LA[23:17], except during DMA
cycles. During DMA cycles, BIOSCS# is not generated.
During Reset: High
ranges. BIOSCS# is driven combinatorially from the ISA addresses SA[16:0] and LA[23:17], except during DMA
cycles. During DMA cycles, BIOSCS# is not generated.
During Reset: High
After Reset: High
During POS: High
KBCCS#/
GPO26
GPO26
O
KEYBOARD CONTROLLER CHIP SELECT. KBCCS# is asserted during I/O read or write accesses to KBC loca-
tions 60h and 64h. It is driven combinatorially from the ISA addresses SA[19:0] and LA[23:17].
If the keyboard controller does not require a separate chip select, this signal can be programmed to a general pur-
pose output.
During Reset: High
tions 60h and 64h. It is driven combinatorially from the ISA addresses SA[19:0] and LA[23:17].
If the keyboard controller does not require a separate chip select, this signal can be programmed to a general pur-
pose output.
During Reset: High
After Reset: High
During POS: High/GPO
MCCS#
O
MICROCONTROLLER CHIP SELECT. MCCS# is asserted during I/O read or write accesses to IO locations 62h
and 66h. It is driven combinatorially from the ISA addresses SA[19:0] and LA[23:17].
During Reset: High
and 66h. It is driven combinatorially from the ISA addresses SA[19:0] and LA[23:17].
During Reset: High
After Reset: High
During POS: High
PCS0#
PCS1#
O
PROGRAMMABLE CHIP SELECTS. These active low chip selects are asserted for ISA I/O cycles which are gener-
ated by PCI masters and which hit the programmable I/O ranges defined in the Power Management section. The X-
Bus buffer signals (XOE# and XDIR#) are enabled while the chip select is active. (i.e., it is assumed that the periph-
eral which is selected via this pin resides on the X-Bus.)
During Reset: High
ated by PCI masters and which hit the programmable I/O ranges defined in the Power Management section. The X-
Bus buffer signals (XOE# and XDIR#) are enabled while the chip select is active. (i.e., it is assumed that the periph-
eral which is selected via this pin resides on the X-Bus.)
During Reset: High
After Reset: High
During POS: High
RCIN#
I
RESET CPU. This signal from the keyboard controller is used to generate an INIT signal to the CPU.
RTCALE/
GPO25
GPO25
O
REAL TIME CLOCK ADDRESS LATCH ENABLE. RTCALE is used to latch the appropriate memory address into
the RTC. A write to port 70h with the appropriate RTC memory address that will be written to or read from causes
RTCALE to be asserted. RTCALE is asserted on falling IOW# and remains asserted for two SYSCLKs.
If the internal Real Time Clock is used, this signal can be programmed as a general purpose output.
During Reset: Low
the RTC. A write to port 70h with the appropriate RTC memory address that will be written to or read from causes
RTCALE to be asserted. RTCALE is asserted on falling IOW# and remains asserted for two SYSCLKs.
If the internal Real Time Clock is used, this signal can be programmed as a general purpose output.
During Reset: Low
After Reset: Low
During POS: Low/GPO
RTCCS#/
GPO24
GPO24
O
REAL TIME CLOCK CHIP SELECT. RTCCS# is asserted during read or write I/O accesses to RTC location 71h.
RTCCS# can be tied to a pair of external OR gates to generate the real time clock read and write command signals.
If the internal Real Time Clock is used, this signal can be programmed as a general purpose output.
During Reset: High
RTCCS# can be tied to a pair of external OR gates to generate the real time clock read and write command signals.
If the internal Real Time Clock is used, this signal can be programmed as a general purpose output.
During Reset: High
After Reset: High
During POS: High/GPO
XDIR#/
GPO22
GPO22
O
X-BUS TRANSCEIVER DIRECTION. XDIR# is tied directly to the direction control of a 74f245 that buffers the X-Bus
data, XD[7:0]. XDIR# is asserted (driven low) for all I/O read cycles regardless if the accesses is to a PIIX4E sup-
ported device. XDIR# is asserted for memory cycles only if BIOS or APIC space has been decoded. For PCI master
initiated read cycles, XDIR# is asserted from the falling edge of either IOR# or MEMR# (from MEMR# only if BIOS or
APIC space has been decoded), depending on the cycle type. For ISA master-initiated read cycles, XDIR# is
asserted from the falling edge of either IOR# or MEMR# (from MEMR# only if BIOS space has been decoded),
depending on the cycle type. When the rising edge of IOR# or MEMR# occurs, PIIX4E negates XDIR#. For DMA
read cycles from the X-Bus, XDIR# is driven low from DACKx# falling and negated from DACKx# rising. At all other
times, XDIR# is negated high.
If the X-Bus is not used, then this signal can be programmed to be a general purpose output.
During Reset: High
data, XD[7:0]. XDIR# is asserted (driven low) for all I/O read cycles regardless if the accesses is to a PIIX4E sup-
ported device. XDIR# is asserted for memory cycles only if BIOS or APIC space has been decoded. For PCI master
initiated read cycles, XDIR# is asserted from the falling edge of either IOR# or MEMR# (from MEMR# only if BIOS or
APIC space has been decoded), depending on the cycle type. For ISA master-initiated read cycles, XDIR# is
asserted from the falling edge of either IOR# or MEMR# (from MEMR# only if BIOS space has been decoded),
depending on the cycle type. When the rising edge of IOR# or MEMR# occurs, PIIX4E negates XDIR#. For DMA
read cycles from the X-Bus, XDIR# is driven low from DACKx# falling and negated from DACKx# rising. At all other
times, XDIR# is negated high.
If the X-Bus is not used, then this signal can be programmed to be a general purpose output.
During Reset: High
After Reset: High
During POS: High/GPO
XOE#/
GPO23
GPO23
O
X-BUS TRANSCEIVER OUTPUT ENABLE. XOE# is tied directly to the output enable of a 74f245 that buffers the X-
Bus data, XD[7:0], from the system data bus, SD[7:0]. XOE# is asserted anytime a PIIX4E supported X-Bus device
is decoded, and the devices decode is enabled in the X-Bus Chip Select Enable Register (BIOSCS#, KBCCS#,
RTCCS#, MCCS#) or the Device Resource B (PCCS0#) and Device Resource C (PCCS1#). XOE# is asserted from
the falling edge of the ISA commands (IOR#, IOW#, MEMR#, or MEMW#) for PCI Master and ISA master-initiated
cycles. XOE# is negated from the rising edge of the ISA command signals for PCI Master initiated cycles and the
SA[16:0] and LA[23:17] address for ISA master-initiated cycles. XOE# is not generated during any access to an X-
Bus peripheral in which its decode space has been disabled.
If an X-Bus not used, then this signal can be programmed to be a general purpose output.
During Reset: High
Bus data, XD[7:0], from the system data bus, SD[7:0]. XOE# is asserted anytime a PIIX4E supported X-Bus device
is decoded, and the devices decode is enabled in the X-Bus Chip Select Enable Register (BIOSCS#, KBCCS#,
RTCCS#, MCCS#) or the Device Resource B (PCCS0#) and Device Resource C (PCCS1#). XOE# is asserted from
the falling edge of the ISA commands (IOR#, IOW#, MEMR#, or MEMW#) for PCI Master and ISA master-initiated
cycles. XOE# is negated from the rising edge of the ISA command signals for PCI Master initiated cycles and the
SA[16:0] and LA[23:17] address for ISA master-initiated cycles. XOE# is not generated during any access to an X-
Bus peripheral in which its decode space has been disabled.
If an X-Bus not used, then this signal can be programmed to be a general purpose output.
During Reset: High
After Reset: High
During POS: High/GPO
Name
Type
Description
UP-5900VS
CIRCUIT DESCRIPTION
5 – 22
■
■
■
■
DMA SIGNALS
■
■
■
■
INTERRUPT CONTROLLER/APIC SIGNALS
Name
Type
Description
DACK[0,1,2,3]#
DACK[5,6,7]#
O
DMA ACKNOWLEDGE. The DACK# output lines indicate that a request for DMA service has been granted by
PIIX4E or that a 16-bit master has been granted the bus. The active level (high or low) is programmed via the DMA
Command Register. These lines should be used to decode the DMA slave device with the IOR# or IOW# line to indi-
cate selection. If used to signal acceptance of a bus master request, this signal indicates when it is legal to assert
MASTER#. If the DREQ goes inactive prior to DACK# being asserted, the DACK# signal will not be asserted.
During Reset: High
PIIX4E or that a 16-bit master has been granted the bus. The active level (high or low) is programmed via the DMA
Command Register. These lines should be used to decode the DMA slave device with the IOR# or IOW# line to indi-
cate selection. If used to signal acceptance of a bus master request, this signal indicates when it is legal to assert
MASTER#. If the DREQ goes inactive prior to DACK# being asserted, the DACK# signal will not be asserted.
During Reset: High
After Reset: High
During POS: High
DREQ[0,1,2,3]
DREQ[5,6,7]
I
DMA REQUEST. The DREQ lines are used to request DMA service from PIIX4Efs DMA controller or for a 16-bit
master to gain control of the ISA expansion bus. The active level (high or low) is programmed via the DMA Com-
mand Register. All inactive to active edges of DREQ are assumed to be asynchronous. The request must remain
active until the appropriate DACKx# signal is asserted.
master to gain control of the ISA expansion bus. The active level (high or low) is programmed via the DMA Com-
mand Register. All inactive to active edges of DREQ are assumed to be asynchronous. The request must remain
active until the appropriate DACKx# signal is asserted.
REQ[A:C]#/
GPI[2:4]
GPI[2:4]
I
PC/PCI DMA REQUEST. These signals are the DMA requests for PC/PCI protocol. They are used by a PCI agent
to request DMA services and follow the PCI Expansion Channel Passing protocol as defined in the PCI DMA sec-
tion.
If the PC/PCI request is not needed, these pins can be used as general-purpose inputs.
to request DMA services and follow the PCI Expansion Channel Passing protocol as defined in the PCI DMA sec-
tion.
If the PC/PCI request is not needed, these pins can be used as general-purpose inputs.
GNT[A:C]#/
GPO[9:11]
GPO[9:11]
O
PC/PCI DMA ACKNOWLEDGE. These signals are the DMA grants for PC/PCI protocol. They are used by a PIIX4E
to acknowledge DMA services and follow the PCI Expansion Channel Passing protocol as defined in the PCI DMA
section.
If the PC/PCI request is not needed, these pins can be used as general-purpose outputs.
During Reset: High
to acknowledge DMA services and follow the PCI Expansion Channel Passing protocol as defined in the PCI DMA
section.
If the PC/PCI request is not needed, these pins can be used as general-purpose outputs.
During Reset: High
After Reset: High
During POS: High/GPO
TC
O
TERMINAL COUNT. PIIX4E asserts TC to DMA slaves as a terminal count indicator. PIIX4E asserts TC after a new
address has been output, if the byte count expires with that transfer. TC remains asserted until AEN is negated,
unless AEN is negated during an autoinitialization. TC is negated before AEN is negated during an autoinitialization.
During Reset: Low
address has been output, if the byte count expires with that transfer. TC remains asserted until AEN is negated,
unless AEN is negated during an autoinitialization. TC is negated before AEN is negated during an autoinitialization.
During Reset: Low
After Reset: Low
During POS: Low
Name
Type
Description
APICACK#/
GPO12
GPO12
O
APIC ACKNOWLEDGE. This active low output signal is asserted by PIIX4E after its internal buffers are flushed in
response to the APICREQ# signal. When the I/O APIC samples this signal asserted it knows that PIIX4Efs buffers
are flushed and that it can proceed to send the APIC interrupt. The APICACK# output is synchronous to PCICLK.
If the external APIC is not used, then this is a general-purpose output.
During Reset: High
response to the APICREQ# signal. When the I/O APIC samples this signal asserted it knows that PIIX4Efs buffers
are flushed and that it can proceed to send the APIC interrupt. The APICACK# output is synchronous to PCICLK.
If the external APIC is not used, then this is a general-purpose output.
During Reset: High
After Reset: High
During POS: High/GPO
APICCS#/
GPO13
GPO13
O
APIC CHIP SELECT. This active low output signal is asserted when the APIC Chip Select is enabled and a PCI orig-
inated cycle is positively decoded within the programmed I/O APIC address space.
If the external APIC is not used, this pin is a general-purpose output.
During Reset: High
inated cycle is positively decoded within the programmed I/O APIC address space.
If the external APIC is not used, this pin is a general-purpose output.
During Reset: High
After Reset: High
During POS: High/GPO
APICREQ#/
GPI5
GPI5
I
APIC REQUEST. This active low input signal is asserted by an external APIC device prior to sending an interrupt
over the APIC serial bus. When PIIX4E samples this pin active it will flush its F-type DMA buffers pointing towards
PCI.
Once the buffers are flushed, PIIX4E asserts APICACK# which indicates to the external APIC that it can proceed to
send the APIC interrupt. The APICREQ# input must be synchronous to PCICLK.
If the external APIC is not used, this pin is a general-purpose input.
over the APIC serial bus. When PIIX4E samples this pin active it will flush its F-type DMA buffers pointing towards
PCI.
Once the buffers are flushed, PIIX4E asserts APICACK# which indicates to the external APIC that it can proceed to
send the APIC interrupt. The APICREQ# input must be synchronous to PCICLK.
If the external APIC is not used, this pin is a general-purpose input.
INTR
OD
INTERRUPT.
IRQ0/
GPO14
GPO14
O
INTERRUPT REQUEST 0. This output reflects the state of the internal IRQ0 signal from the system timer.
If the external APIC is not used, this pin is a general-purpose output.
During Reset: Low
If the external APIC is not used, this pin is a general-purpose output.
During Reset: Low
After Reset: Low
During POS: IRQ0/GPO
IRQ1
I
INTERRUPT REQUEST 1. IRQ1 is always edge triggered and can not be modified by software to level sensitive. A
low to high transition on IRQ1 is latched by PIIX4E.
IRQ1 must remain asserted until after the interrupt is acknowledged. If the input goes inactive before this time, a
default IRQ7 is reported in response to the interrupt acknowledge cycle.
low to high transition on IRQ1 is latched by PIIX4E.
IRQ1 must remain asserted until after the interrupt is acknowledged. If the input goes inactive before this time, a
default IRQ7 is reported in response to the interrupt acknowledge cycle.
IRQ 3:7, 9:11,
14:15
14:15
I
INTERRUPT REQUESTS 3:7, 9:11, 14:15. The IRQ signals provide both system board components and ISA Bus I/
O devices with a mechanism for asynchronously interrupting the CPU. These interrupts may be programmed for
either an edge sensitive or a high level sensitive assertion mode. Edge sensitive is the default configuration.
An active IRQ input must remain asserted until after the interrupt is acknowledged. If the input goes inactive before
this time, a default IRQ7 is reported in response to the interrupt acknowledge cycle.
O devices with a mechanism for asynchronously interrupting the CPU. These interrupts may be programmed for
either an edge sensitive or a high level sensitive assertion mode. Edge sensitive is the default configuration.
An active IRQ input must remain asserted until after the interrupt is acknowledged. If the input goes inactive before
this time, a default IRQ7 is reported in response to the interrupt acknowledge cycle.
IRQ8#/
GPI6
GPI6
I/O
IRQ 8#. IRQ8# is always an active low edge triggered interrupt and can not be modified by software.
IRQ8# must remain asserted until after the interrupt is acknowledged. If the input goes inactive before this time, a
default IRQ7 is reported in response to the interrupt acknowledge cycle.
If using the internal RTC, then this can be programmed as a general-purpose input. If enabling an APIC, this signal
becomes an output and must not be programmed as a general purpose input.
IRQ8# must remain asserted until after the interrupt is acknowledged. If the input goes inactive before this time, a
default IRQ7 is reported in response to the interrupt acknowledge cycle.
If using the internal RTC, then this can be programmed as a general-purpose input. If enabling an APIC, this signal
becomes an output and must not be programmed as a general purpose input.
IRQ9OUT#/
GPO29
GPO29
O
IRQ9OUT#. IRQ9OUT# is used to route the internally generated SCI and SMBus interrupts out of the PIIX4E for
connection to an external IO APIC. If APIC is disabled, this signal pin is a General Purpose Output.
During Reset: High
connection to an external IO APIC. If APIC is disabled, this signal pin is a General Purpose Output.
During Reset: High
After Reset: High
During POS: IRQ9OUT#/GPO
Click on the first or last page to see other UP-5900 (serv.man8) service manuals if exist.