Sharp UP-5900 (serv.man8) Service Manual ▷ View online
UP-5900VS
CIRCUIT DESCRIPTION
5 – 15
Note:
1.
All PCI interface signals conform to the PCI Rev 2.1 specification.
4) Primary PCI Sideband Interface
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Primary PCI Sideband Interface Signals
5) AGP Interface Signals
There are 17 new signals added to the normal PCI group of signals that together constitute the AGP interface.
The sections below describe their operation and use, and are organized in five groups:
• AGP Addressing Signals
• AGP Flow Control Signals
• AGP Status Signals
• AGP Clocking Signals- Strobes
• PCI Signals
PAR
I/O
PCI
Parity: PAR is driven by the 82443BX when it acts as a PCI initiator during address and data phases for a write cycle,
and during the address phase for a read cycle. PAR is driven by the 82443BX when it acts as a PCI target during each
data phase of a PCI memory read cycle. Even parity is generated across AD[31:0] and C/BE[3:0]#.
and during the address phase for a read cycle. PAR is driven by the 82443BX when it acts as a PCI target during each
data phase of a PCI memory read cycle. Even parity is generated across AD[31:0] and C/BE[3:0]#.
PLOCK#
I/O
PCI
Lock: PLOCK# indicates an exclusive bus operation and may require multiple transactions to complete. When
PLOCK# is asserted, non-exclusive transactions may proceed. The 82443BX supports lock for CPU initiated cycles
only. PCI initiated locked cycles are not supported.
PLOCK# is asserted, non-exclusive transactions may proceed. The 82443BX supports lock for CPU initiated cycles
only. PCI initiated locked cycles are not supported.
TRDY#
I/O
PCI
Target Ready: TRDY# is an input when the 82443BX acts as a PCI initiator and an output when the 82443BX acts as a
PCI target. The assertion of TRDY# indicates the target agent’s ability to complete the current data phase of the trans-
action.
PCI target. The assertion of TRDY# indicates the target agent’s ability to complete the current data phase of the trans-
action.
SERR#
I/O
PCI
System Error: The 82443BX asserts this signal to indicate an error condition. The SERR# assertion by the 82443BX is
enabled globally via SERRE bit of the PCICMD register.
SERR# is asserted under the following conditions:
In an ECC configuration, the 82443BX asserts SERR#, for single bit (correctable) ECC errors or multiple bit (non-cor-
rectable) ECC errors if SERR# signaling is enabled via the ERRCMD control register. Any ECC errors received during
initialization should be ignored.
enabled globally via SERRE bit of the PCICMD register.
SERR# is asserted under the following conditions:
In an ECC configuration, the 82443BX asserts SERR#, for single bit (correctable) ECC errors or multiple bit (non-cor-
rectable) ECC errors if SERR# signaling is enabled via the ERRCMD control register. Any ECC errors received during
initialization should be ignored.
• The 82443BX asserts SERR# for one clock when it detects a target abort during 82443BX initiated PCI cycle.
• The 82443BX can also assert SERR# when a PCI parity error occurs during the address or data phase.
• The 82443BX can assert SERR# when it detects a PCI address or data parity error on AGP.
• The 82443BX can assert SERR# upon detection of access to an invalid entry in the Graphics Aperture Translation
Table.
• The 82443BX can assert SERR# upon detecting an invalid AGP master access outside of AGP aperture and outside
of main DRAM range (i.e. in the 640k - 1M range or above TOM).
• The 82443BX can assert SERR# upon detecting an invalid AGP master access outside of AGP aperture.
• The 82443BX asserts SERR# for one clock when it detects a target abort during 82443BX initiated AGP cycle.
STOP#
I/O
PCI
Stop: STOP# is an input when the 82443BX acts as a PCI initiator and an output when the 82443BX acts as a PCI tar-
get. STOP# is used for disconnect, retry, and abort sequences on the PCI Bus.
get. STOP# is used for disconnect, retry, and abort sequences on the PCI Bus.
Name
Type
Description
Name
Type
Description
PHOLD#
I
PCI
PCI Hold: This signal comes from the PIIX4E. It is the PIIX4E request for PCI bus ownership.
The 82443BX will flush and disable the CPU-to-PCI write buffers before granting the PIIX4E the PCI bus via PHLDA#.
This prevents bus deadlock between PCI and ISA.
The 82443BX will flush and disable the CPU-to-PCI write buffers before granting the PIIX4E the PCI bus via PHLDA#.
This prevents bus deadlock between PCI and ISA.
PHLDA#
O
PCI
PCI Hold Acknowledge: This signal is driven by the 82443BX to grant PCI bus ownership to the PIIX4E after CPU-PCI
post buffers have been flushed and disabled.
post buffers have been flushed and disabled.
WSC#
O
CMOS
Write Snoop Complete. This signal is asserted active to indicate that all that the snoop activity on the CPU bus on the
behalf of the last PCI-DRAM write transaction is complete and that is safe to send the APIC interrupt message.
behalf of the last PCI-DRAM write transaction is complete and that is safe to send the APIC interrupt message.
PREQ[4:0]#
I
PCI
PCI Bus Request: PREQ[4:0]# are the PCI bus request signals used as inputs by the internal PCI arbiter.
PGNT[4:0]#
O
PCI
PCI Grant: PGNT[4:0]# are the PCI bus grant output signals generated by the internal PCI arbiter.
UP-5900VS
CIRCUIT DESCRIPTION
5 – 16
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AGP Interface Signals
Name
Type
Description
AGP Sideband Addressing Signals
1
PIPE#
I
AGP
Pipelined Read: This signal is asserted by the current master to indicate a full width address is to be queued by the
target. The master queues one request each rising clock edge while PIPE# is asserted. When PIPE# is deasserted
no new requests are queued across the AD bus. PIPE# is a sustained tri-state signal from masters (graphics con-
troller) and is an input to the 82443BX. Note that initial AGP designs may not use PIPE#.
target. The master queues one request each rising clock edge while PIPE# is asserted. When PIPE# is deasserted
no new requests are queued across the AD bus. PIPE# is a sustained tri-state signal from masters (graphics con-
troller) and is an input to the 82443BX. Note that initial AGP designs may not use PIPE#.
SBA[7:0]
I
AGP
Sideband Address: This bus provides an additional bus to pass address and command to the 82443BX from the
AGP master. Note that, when sideband addressing is disabled, these signals are isolated (no external/internal pull-
ups are required).
AGP master. Note that, when sideband addressing is disabled, these signals are isolated (no external/internal pull-
ups are required).
AGP Flow Control Signals
RBF#
I
AGP
Read Buffer Full. This signal indicates if the master is ready to accept previously requested low priority read data.
When RBF# is asserted the 82443BX is not allowed to return low priority read data to the AGP master on the first
block. RBF# is only sampled at the beginning of a cycle.
If the AGP master is always ready to accept return read data then it is not required to implement this signal.
When RBF# is asserted the 82443BX is not allowed to return low priority read data to the AGP master on the first
block. RBF# is only sampled at the beginning of a cycle.
If the AGP master is always ready to accept return read data then it is not required to implement this signal.
AGP Status Signals
ST[2:0]
O
AGP
Status Bus: This bus provides information from the arbiter to a AGP Master on what it may do. ST[2:0] only have
meaning to the master when its GGNT# is asserted.
When GGNT# is deasserted these signals have no meaning and must be ignored.
meaning to the master when its GGNT# is asserted.
When GGNT# is deasserted these signals have no meaning and must be ignored.
000 Indicates that previously requested low priority read data is being returned to the master.
001 Indicates that previously requested high priority read data is being returned to the master.
010 Indicates that the master is to provide low priority write data for a previously queued write command.
011 Indicates that the master is to provide high priority write data for a previously queued write command.
100 Reserved
101 Reserved
110 Reserved
111 Indicates that the master has been given permission to start a bus transaction.
001 Indicates that previously requested high priority read data is being returned to the master.
010 Indicates that the master is to provide low priority write data for a previously queued write command.
011 Indicates that the master is to provide high priority write data for a previously queued write command.
100 Reserved
101 Reserved
110 Reserved
111 Indicates that the master has been given permission to start a bus transaction.
The master may queue AGP requests by asserting PIPE# or start a PCI transaction by asserting FRAME#.
ST[2:0] are always an output from the 82443BX and an input to the master.
ST[2:0] are always an output from the 82443BX and an input to the master.
AGP Clocking Signals - Strobes
ADSTB_A
I/O
AGP
AD Bus Strobe A: This signal provides timing for double clocked data on the AD bus.
The agent that is providing data drives this signal. This signal requires an 8.2K ohm external pull-up resistor.
The agent that is providing data drives this signal. This signal requires an 8.2K ohm external pull-up resistor.
ADSTB_B
I/O
AGP
AD Bus Strobe B: This signal is an additional copy of the AD_STBA signal. This signal requires an 8.2K ohm exter-
nal pull-up resistor.
nal pull-up resistor.
SBSTB
I
AGP
Sideband Strobe: THis signal provides timing for a side-band bus. This signal requires an 8.2K ohm external pull-
up resistor.
up resistor.
AGP FRAME# Protocol SIgnals (similar to PCI)
2
GFRAME#
I/O
AGP
Graphics Frame: Same as PCI. Not used by AGP. GFRAME# remains deasserted by its own pull up resistor.
GIRDY#
I/O
AGP
Graphics Initiator Ready: New meaning. GIRDY# indicates the AGP compliant master is ready to provide all write
data for the current transaction. Once IRDY# is asserted for a write operation, the master is not allowed to insert
wait states. The assertion of IRDY# for reads indicates that the master is ready to transfer to a subsequent block
(32 bytes) of read data. The master is never allowed to insert wait states during the initial data transfer (32 bytes) of
a read transaction. However, it may insert wait states after each 32 byte block is transferred.
(There is no GFRAME# -- GIRDY# relationship for AGP transactions.)
data for the current transaction. Once IRDY# is asserted for a write operation, the master is not allowed to insert
wait states. The assertion of IRDY# for reads indicates that the master is ready to transfer to a subsequent block
(32 bytes) of read data. The master is never allowed to insert wait states during the initial data transfer (32 bytes) of
a read transaction. However, it may insert wait states after each 32 byte block is transferred.
(There is no GFRAME# -- GIRDY# relationship for AGP transactions.)
GTRDY#
I/O
AGP
Graphics Target Ready: New meaning. GTRDY# indicates the AGP compliant target is ready to provide read data
for the entire transaction (when the transfer size is less than or equal to 32 bytes) or is ready to transfer the initial or
subsequent block (32 bytes) of data when the transfer size is greater than 32 bytes. The target is allowed to insert
wait states after each block (32 bytes) is transferred on both read and write transactions.
for the entire transaction (when the transfer size is less than or equal to 32 bytes) or is ready to transfer the initial or
subsequent block (32 bytes) of data when the transfer size is greater than 32 bytes. The target is allowed to insert
wait states after each block (32 bytes) is transferred on both read and write transactions.
GSTOP#
I/O
AGP
Graphics Stop: Same as PCI. Not used by AGP.
GDEVSEL#
I/O
AGP
Graphics Device Select: Same as PCI. Not used by AGP.
GREQ#
I
AGP
Graphics Request: Same as PCI. (Used to request access to the bus to initiate a PCI or AGP request.)
GGNT#
O
AGP
Graphics Grant: Same meaning as PCI but additional information is provided on ST[2:0]. The additional informa-
tion indicates that the selected master is the recipient of previously requested read data (high or normal priority), it
is to provide write data (high or normal priority), for a previously queued write command or has been given permis-
sion to start a bus transaction (AGP or PCI).
tion indicates that the selected master is the recipient of previously requested read data (high or normal priority), it
is to provide write data (high or normal priority), for a previously queued write command or has been given permis-
sion to start a bus transaction (AGP or PCI).
GAD[31:0]
I/O
AGP
Graphics Address/Data: Same as PCI.
GC/BE[3:0]#
I/O
AGP
Graphics Command/Byte Enables: Slightly different meaning. Provides command information (different commands
than PCI) when requests are being queued when using PIPE#. Provide valid byte information during AGP write
transactions and are not used during the return of read data.
than PCI) when requests are being queued when using PIPE#. Provide valid byte information during AGP write
transactions and are not used during the return of read data.
GPAR
I/O
AGP
Graphics Parity: Same as PCI. Not used on AGP transactions, but used during PCI transactions as defined by the
PCI specification.
PCI specification.
UP-5900VS
CIRCUIT DESCRIPTION
5 – 17
Note:
1.
AGP Sideband Addressing Signals. The above table contains two mechanisms to queue requests by the AGP master. Note that the master can
only use one mechanism. When PIPE# is used to queue addresses the master is not allowed to queue addresses using the SBA bus. For exam-
only use one mechanism. When PIPE# is used to queue addresses the master is not allowed to queue addresses using the SBA bus. For exam-
ple, during configuration time, if the master indicates that it can use either mechanism, the configuration software will indicate which mechanism
the master will use. Once this choice has been made, the master will continue to use the mechanism selected until the master is reset (and repro-
grammed) to use the other mode. This change of modes is not a dynamic mechanism but rather a static decision when the device is first being
grammed) to use the other mode. This change of modes is not a dynamic mechanism but rather a static decision when the device is first being
configured after reset.
2.
PCI signals are redefined when used in AGP transactions carried using AGP protocol extension. For transactions on the AGP interface carried
using PCI protocol these signals completely preserve PCI semantics. The exact role of all PCI signals during AGP transactions is in Table 2-6.
3.
The LOCK# signal is not supported on the AGP interface (even for PCI operations).
4.
PCI signals described in Table 2-4 behave according to PCI 2.1 specifications when used to perform PCI transactions on the AGP Interface.
6) Clocks, Reset, and Miscellaneous
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Clocks, Reset, and Miscellaneous
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Power Management Interface
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Reference Pins
Name
Type
Description
HCLKIN
I
CMOS
Host Clock In: This pin receives a buffered host clock. This clock is used by all of the 82443BX logic that is in the
Host clock domain.
When SUSTAT# is active, there is an internal 100K ohm pull down on this signal.
Host clock domain.
When SUSTAT# is active, there is an internal 100K ohm pull down on this signal.
PCLKIN
I
CMOS
PCI Clock In: This is a buffered PCI clock reference that is synchronously derived by an external clock synthesizer
component from the host clock. This clock is used by all of the 82443BX logic that is in the PCI clock domain.
When SUSTAT# is active, there is an internal 100K ohm pull down on this signal.
component from the host clock. This clock is used by all of the 82443BX logic that is in the PCI clock domain.
When SUSTAT# is active, there is an internal 100K ohm pull down on this signal.
DCLKO
O
CMOS
SDRAM Clock Out: 66 or 100 MHz SDRAM clock reference. It feeds an external buffer clock device that produces
multiple copies for the DIMMs.
multiple copies for the DIMMs.
DCLKWR
I
CMOS
SDRAM Write Clock: Feedback reference from the external SDRAM clock buffer.
This clock is used by the 82443BX when writing data to the SDRAM array.
This clock is used by the 82443BX when writing data to the SDRAM array.
PCIRST#
I
CMOS
PCI Reset: When asserted, this signal will reset the 82443BX logic. All PCI output and bi-directional signals will also
tri-state compliant to PCI Rev 2.0 and 2.1 specifications.
When SUSTAT# is active, there is an internal 100K ohm pull down on this signal.
tri-state compliant to PCI Rev 2.0 and 2.1 specifications.
When SUSTAT# is active, there is an internal 100K ohm pull down on this signal.
GCLKIN
I
CMOS
AGP Clock In: The GCLKIN input is a feedback reference from the GCLKOUT signal.
GCLKO
O
CMOS
AGP Clock Out: The frequency is 66 MHz. The GCLKOUT output is used to feed both the reference input pin on the
82443BX and the AGP compliant device.
82443BX and the AGP compliant device.
CRESET#
O
CMOS
Delayed CPU Reset: CRESET# is a delayed copy of CPURST#. This signal is used to control the multiplexer for the
CPU strap signals. CRESET# is delayed from CPURST# by two host clocks.
Note: This pin requires an external pull-up resistor. If not used, no pull up is required.
CPU strap signals. CRESET# is delayed from CPURST# by two host clocks.
Note: This pin requires an external pull-up resistor. If not used, no pull up is required.
TESTIN#
I
CMOS
Test Input: This pin is used for manufacturing, and board level test purposes.
Note: This pin has an internal 50K ohm pull-up.
Note: This pin has an internal 50K ohm pull-up.
Name
Type
Description
CLKRUN#
I/OD
CMOS
Primary PCI Clock Run: The 82443BX requests the central resource (PIIX4E) to start or maintain the PCI clock by
the assertion of CLKRUN#. The 82443BX tristates CLKRUN# upon deassertion of PCIRST# (since CLK is running
upon deassertion of reset). If connected to PIIX4E an external 2.7K Ohm pull-up is required for Desktop, Mobile
requires (8.2k 10K) pull-up. Otherwise, a 100 Ohm pull down is required.
the assertion of CLKRUN#. The 82443BX tristates CLKRUN# upon deassertion of PCIRST# (since CLK is running
upon deassertion of reset). If connected to PIIX4E an external 2.7K Ohm pull-up is required for Desktop, Mobile
requires (8.2k 10K) pull-up. Otherwise, a 100 Ohm pull down is required.
SUSTAT#
I
CMOS
Suspend Status (from PIIX): SUSTAT# signals the system suspend state transition from the PIIX4E. It is used to iso-
late the suspend voltage well and enter/exit DRAM self-refresh mode. During POS/STR SUSTAT# is active.
late the suspend voltage well and enter/exit DRAM self-refresh mode. During POS/STR SUSTAT# is active.
BXPWROK
I
CMOS
BX Power OK: BXPWROK input must be connected to the PWROK signal that indicates valid power is applied to
the 82443BX.
the 82443BX.
Name
Description
GTLREF[B:A]
GTL Buffer voltage reference input
VTT[B:A]
GTL Threshold voltage for early clamps
VCC
Power pin @ 3.3V
VSS
Ground
REF5V
PCI 5V reference voltage (for 5V tolerant buffers)
AGPREF
External Input Reference
UP-5900VS
CIRCUIT DESCRIPTION
5 – 18
11. CHIPSET (SOUTH BRIDGE)
Intel’s PIIX4E is used.
11-1. PIN ASSIGHMENTS
11-2. PIN DISCRIPTION
1) PIIX4E Signals
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PCI BUS INTERFACE
M
N
P
R
T
U
V
W
Y
K
L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
B
C
D
E
F
G
H
J
PCIR-
ST#
AD1
PCIR-
EQB#
EQB#
PHLD-
A#
SDD6 SDD4 SDD13 SDDR-
EQ
SDD-
ACK#
SDA2 PDD8 PDD7
AD27 IDSEL AD19
FRA-
ME #
ME #
SERR# AD13
AD9
AD5
AD31
AD0
PCIR-
EQC#
EQC#
PHO-
LD#
SDD9
SDD-
11
SDD1
SDI-
OW#
SDA1
SDC-
S1#
PDD9
AD26
AD23
PDD6
AD18 IRDY#
PAR
AD12
AD8
AD4
AD30 AD25
CLK-
RUN#
PCIR-
EQD#
EQD#
SDD7 SDD5 SDD3 SDD14
SDI-
OR#
OR#
SDA0
SDC-
S3#
PDD10 PDD5
AD22
AD17 TRDY#
C/-
BE1#
AD11
C/-
BE0#
AD3
AD28
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PCI-
CLK
CLK
SDD8
SDD2 SDD15
SIO-
RDY
RDY
PDD-
12
PDD3 PDD-
11
PDD4
C/-
BE3#
AD20
C/-
BE2#
STOP# AD14
AD10
AD6
AD2
AD29
AD24
AD21
PCIR-
EQA#
EQA#
VCC
SDD12 SDD0
VCC PDD14 PDD1 PDD13 PDD2
AD16
DEV-
SEL#
SEL#
AD15
VSS
AD7
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
USB-
P1+
GPO-
28
PDI-
OW#
PDI-
OR#
OR#
PDD-
REQ
PDD15 PDD0
IRQ9-
OUT
GPO-
30
PIR-
QD#
QD#
USB-
P0+
PIO-
RDY
RDY
PDA0 PDA2 PDA1
PDD-
ACK#
ACK#
GP1-
21
GPO-
0
GPO-
27
GPI-
18
USB
P1-
USB
PO-
GPI-
19
GPI-
20
PDC-
S3#
PDC-
S1#
API-
CCS#
THRM# IRQ0
OC0# OC1#
GPI-
14
NC
NC
NC
NC
NC
VSS
(USB)
KBC-
CS#
RTC-
CS#
GPI-
16
GPI-
17
VCC
(USB)
VREF
APIC-
ACK#
ACK#
STP-
CLK#
SER-
IRQ
IRQ1
ZZ
SPKR APIC-
REQ#
FERR# SLP#
RTC-
ALE
VCC
(RTC)
IGN-
NE#
NE#
INIT
INTR
NMI
GPI-
13
PCS0#
CLK-
48
GPI-
15
REQ-
A#
BIOS-
CS#
XDIR# XOE#
NC
RSM-
RST#
RST#
PWR
OK
CPU-
RST
A20-
M#
GNTA# REQ-
B#
MCCS# PCS1#
VCC
(SUS)
SMBAL-
ERT#
RTCX1 RCIN#
A20-
GATE
GNT-
B#
REQ-
C#
GNT-
C#
PIR-
QC#
QC#
LID
SUS-
CLK
RI#
GPI-
1
SMI#
CPU_-
STP#
PCI_-
STP#
STP#
PIR-
QA#
QA#
PIR-
QB#
QB#
VCC
(SUS)
CON-
FIG1
CON-
FIG2
SMB-
CLK
RTC-
X2
SD6
SD3
IOCH-
RDY
IOW#
SA16
SYS-
CLK
SA9
IRQ3
SA4
SA1
LA23
IRQ-
12/M
12/M
LA18 DACK-
5#
SD9
SUS_
STAT1#
SUS_
STAT2#
GPO-
8
SMB-
DATA
IRQ9
BALE
SA0
IRQ10 LA20 DACK-
0#
MEM-
W#
DRE-
Q6
DRE-
Q7
SUSC# BAT-
LOW#
PWR-
BTN#
BTN#
SD2
SME-
MW#
SA18
DRE-
Q3
DRE-
Q1
SA11
IRQ5
SA6
SD7
DRE-
Q2
SD0
SA19 DACK-
3#
SA14
SA12
IRQ6
SA7
TC
OSC
IOCS-
16#
LA21
IRQ14 MEM-
R#
DACK-
6#
SD11 TEST# SUSB# EXT-
SMI#
RST-
DRV
SD4
SD1
SME-
MR#
SA17 DACK-
1#
REFR-
ESH#
SA10
IRQ4
SA5
SA2
SBH-
E#
IRQ11 LA19
DRE-
Q0
SD8
DACK-
7#
SD13
SD15 SUSA#
IOCHK# SD5
ZERO-
WS#
AEN
IOR#
SA15
SA13
IRQ7
SA8
DACK-
2#
SA3
MEM-
CS16#
LA22
IRQ15 LA17
DRE-
Q5
SD10
SD12
SD14 IRQ8#
SDD10
pix4_pin
NOTE:
For multiplexed pins, only one of the two signal names is shown in this figure. For example, the name
for “Y20” only lists IRQ8#(instead of IRQ8#/GPI6). The pin list in Table 69 includes both signal names
for the multiplexed pins.
for “Y20” only lists IRQ8#(instead of IRQ8#/GPI6). The pin list in Table 69 includes both signal names
for the multiplexed pins.
Name
Type
Description
AD[31:0]
I/O
PCI ADDRESS/DATA. AD[31:0] is a multiplexed address and data bus. During the first clock of a transaction,
AD[31:0] contain a physical byte address (32 bits). During subsequent clocks, AD[31:0] contain data.
A PIIX4E Bus transaction consists of an address phase followed by one or more data phases. Little-endian byte
ordering is used. AD[7:0] define the least significant byte (LSB) and AD[31:24] the most significant byte (MSB).
When PIIX4E is a Target, AD[31:0] are inputs during the address phase of a transaction. During the following data
phase(s), PIIX4E may be asked to supply data on AD[31:0] for a PCI read, or accept data for a PCI write.
As an Initiator, PIIX4E drives a valid address on AD[31:2] and 0 on AD[1:0] during the address phase, and drives
write or latches read data on AD[31:0] during the data phase.
During Reset: High-Z
AD[31:0] contain a physical byte address (32 bits). During subsequent clocks, AD[31:0] contain data.
A PIIX4E Bus transaction consists of an address phase followed by one or more data phases. Little-endian byte
ordering is used. AD[7:0] define the least significant byte (LSB) and AD[31:24] the most significant byte (MSB).
When PIIX4E is a Target, AD[31:0] are inputs during the address phase of a transaction. During the following data
phase(s), PIIX4E may be asked to supply data on AD[31:0] for a PCI read, or accept data for a PCI write.
As an Initiator, PIIX4E drives a valid address on AD[31:2] and 0 on AD[1:0] during the address phase, and drives
write or latches read data on AD[31:0] during the data phase.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
C/BE#[3:0]
I/O
BUS COMMAND AND BYTE ENABLES. The command and byte enable signals are multiplexed on the same PCI
pins. During the address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase C/
BE[3:0]# are used as Byte Enables. The Byte Enables determine which byte lanes carry meaningful data.
C/BE0# applies to byte 0, C/BE1# to byte 1, etc. PIIX4E drives C/BE[3:0]# as an Initiator and monitors C/BE[3:0]#
as a Target.
During Reset: High-Z
pins. During the address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase C/
BE[3:0]# are used as Byte Enables. The Byte Enables determine which byte lanes carry meaningful data.
C/BE0# applies to byte 0, C/BE1# to byte 1, etc. PIIX4E drives C/BE[3:0]# as an Initiator and monitors C/BE[3:0]#
as a Target.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
CLKRUN#
I/O
CLOCK RUN#. This signal is used to communicate to PCI peripherals that the PCI clock will be stopped. Peripher-
als can assert CLKRUN# to request that the PCI clock be restarted or to keep it from stopping. This function follows
the protocol described in the PCI Mobile Design Guide, Revision 1.0.
During Reset: Low
als can assert CLKRUN# to request that the PCI clock be restarted or to keep it from stopping. This function follows
the protocol described in the PCI Mobile Design Guide, Revision 1.0.
During Reset: Low
After Reset: Low
During POS: High
DEVSEL#
I/O
DEVICE SELECT. PIIX4E asserts DEVSEL# to claim a PCI transaction through positive decoding or subtractive
decoding (if enabled). As an output, PIIX4E asserts DEVSEL# when it samples IDSEL active in configuration cycles
to PIIX4E configuration registers. PIIX4E also asserts DEVSEL# when an internal PIIX4E address is decoded or
when PIIX4E subtractively or positively decodes a cycle for the ISA/EIO bus or IDE device. As an input, DEVSEL#
indicates the response to a PIIX4E initiated transaction and is also sampled when deciding whether to subtractively
decode the cycle. DEVSEL# is tri-stated from the leading edge of PCIRST#. DEVSEL# remains tri-stated until
driven by PIIX4E as a target.
During Reset: High-Z
decoding (if enabled). As an output, PIIX4E asserts DEVSEL# when it samples IDSEL active in configuration cycles
to PIIX4E configuration registers. PIIX4E also asserts DEVSEL# when an internal PIIX4E address is decoded or
when PIIX4E subtractively or positively decodes a cycle for the ISA/EIO bus or IDE device. As an input, DEVSEL#
indicates the response to a PIIX4E initiated transaction and is also sampled when deciding whether to subtractively
decode the cycle. DEVSEL# is tri-stated from the leading edge of PCIRST#. DEVSEL# remains tri-stated until
driven by PIIX4E as a target.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
FRAME#
I/O
CYCLE FRAME. FRAME# is driven by the current Initiator to indicate the beginning and duration of an access.
While FRAME# is asserted data transfers continue. When FRAME# is negated the transaction is in the final data
phase. FRAME# is an input to PIIX4E when it is the Target. FRAME# is an output when PIIX4E is the initiator.
FRAME# remains tri-stated until driven by PIIX4E as an Initiator.
During Reset: High-Z
While FRAME# is asserted data transfers continue. When FRAME# is negated the transaction is in the final data
phase. FRAME# is an input to PIIX4E when it is the Target. FRAME# is an output when PIIX4E is the initiator.
FRAME# remains tri-stated until driven by PIIX4E as an Initiator.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
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