Sharp UP-5900 (serv.man8) Service Manual ▷ View online
UP-5900VS
CIRCUIT DESCRIPTION
5 – 7
7. PCI BUS
7-1. DEVICE NUMBER DECODE
7-2. BUS ARBITRATION
7-3. INTERRUPT REQUEST
PIRQ D is connected to the above PCI device and PCIIRQ0 of PCI
SLOT, and connected to IRQ2 by BIOS.
SLOT, and connected to IRQ2 by BIOS.
PIRQ A is connected to PCIIRQ1 of PCI SLOT, and connected to IRQ5
by BIOS.
Interrupt requests which can be used with PCI slot are limited to INTA#
(PCI) and INTB# (PCI). INTC# (PCI) and INTD# (PCI) must not be
(PCI) and INTB# (PCI). INTC# (PCI) and INTD# (PCI) must not be
used.
PCI Interrupt SelectionPIO
8. SM BUS
9. CPU
Intel's embedded Celeron (RB80526RX566128SL4PC) is used.
The clock frequency of CPU is automatically multiplied in the Chip.
The clock frequency of CPU is automatically multiplied in the Chip.
System Bus, Core Frequency
The core voltage of CPU is automatically set by connecting the VID terminal to the power IC.
Voltage Identification Definition
Bus
Device
Number
Func
IDSEL
Device
Remark
0
0000h
0000h
AD11
440BX
Host to PCI Bridge
0001h
0000h
AD12
PCI to PCI Bridge
0007h
0000h
AD18
PIIX4e
PCI to ISA Bridge
0001h
IDE Interface
0002h
USB Interface
0003h
Power Management
000Ah
0000h
AD21
RTL8139C
LAN Controller
0012h
XXXXh
AD29
PCI SLOT
Expansion SLOT
1
0000h
0000h
AD16
Lynx3DM4+ VGA (AGP connection)
Master Device No.
Request allow signal
Device
Device 0
REQ0#, GNT0#
(Not Used)
Device 1
REQ1#, GNT1#
(Not Used)
Device 2
REQ2#, GNT2#
(Not Used)
Device 3
REQ3#, GNT3#
PCI Slot
PIO PCIIRQ
Selection
PCI Interrupt
PIO PCIIRQ0#
IRQ12
INTA#
PIO PCIIRQ1#
IRQ5
INTB#
PIO PCIIRQ2#
Disable
INTC#
PIO PCIIRQ3#
Disable
INTD#
Address
Device
Remark
10100000b
DIMM 0
UP-5900 standard memory supports SPD.
10100010b
DIMM 1
DIMM can be set with SPD.
00110000b
LM84CIM
CPU Temperature SENSOR
11010010b
ICS9248
Clock Generator
PIRQ D
PIRQ A
Lynx3DM4+
VGA
RTL8139CL PCI SLOT
LAN
PIIX4e
USB
Core Frequency (MHz)
BCLK Frequency (MHz)
Frequency Multiplier
566
66
8.5
VID3
VID2
VID1
VID0
VccCore
Celeron566
0
1
1
1
1.70
Step C
UP-5900VS
CIRCUIT DESCRIPTION
5 – 8
9-1. PIN ASSIGNMENTS
9-2. PIN DISCRIPTION
AN
A M
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Z
Y
X
W
V
U
T
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
V S S
V C C
V S S
D 3 5
D 2 9
D 3 3
D 2 6
D 2 8
D 2 1
D 2 3
D 2 5
V S S
V C C
V S S
D 3 1
V C C
D 4 3
V C C
V S S
D 3 4
D 3 8
V C C
V S S
D 3 9
D 3 6
V C C
D 3 7
D 4 4
V C C
V C C
D 3 2
D 2 2
R S V
D 2 7
V S S
D 4 2
D 4 5
D 4 9
V S S
V C C
D 6 3
V R E F 1
V S S
V C C
V S S
V C C
V S S
V C C
V S S
V C C
V S S
V C C
V S S
V C C
V S S
R S V
R S V
D 6 2
S L E W
C T R L
R S V
R S V
V R E F 0
B P M 1
B P 3
D 4 1
D 5 2
V S S
V C C
V S S
V C C
V S S
V C C
V S S
V C C
V S S
V C C
D 4 0
D 5 9
D 5 5
D 5 4
D 5 8
D 5 0
D 5 6
R S V
R S V
R S V
B P M 0
C P U P R E S
V C C
V S S
V C C
V S S
V C C
V S S
V C C
V S S
V C C
V S S
V C C
R S V
D 5 1
D 4 7
D 4 8
D 5 7
D 4 6
D 5 3
D 6 0
D 6 1
R S V
R S V
R S V
P R D Y
V S S
B P 2
R S V
R S V
V C C
V S S
V C C
P I C C L K
P I C D 0
P R E Q
V C C
V C C
V S S
R S V
P I C D 1
L I N T 1
V C C
V S S
L I N T 0
R S V
R S V
R S V
V S S
V C C
V S S
R S V
R S V
R S V
V C C
V S S
V C C
R S V
R T T
C T R L
R S V
V S S
V C C
V S S
P L L 2
R S V
R S V
V C C
V S S
V C C
R S V
V C C
V S S
V C C
V S S
V _ 2 . 5
R S V
R S V
V C C
V S S
V C C
V _ C M O S
V S S
F E R R
R S V
V C C
V S S
V _ 1 . 5
A 2 0 M
I E R R
F L U S H
V S S
V C C
V S S
INIT
V S S
V C C
V S S
P L L 1
R S V
B C L K
S T P C L K
I G N N E
V S S
D 1 6
D 1 9
D 7
D 3 0
V C C
V C C
V R E F 2
D 2 4
D 1 3
D 2 0
V S S
V S S
D 1 1
D 3
D 2
D 1 4
V C C
V C C
D 1 8
D 9
D 1 2
D 1 0
V S S
R S V
D 1 7
V R E F 3
D 8
D 5
V C C
V C C
D 1
D 6
D 4
D 1 5
V S S
V S S
R S V
V R E F 4
D 0
R S V
V C C
R S V
R E S E T
R S V
R S V
A 2 6
V S S
V S S
A 2 9
A 1 8
A 2 7
A 3 0
V C C
V C C
A 2 4
A 2 3
R S V
A 2 0
V S S
V S S
A 3 1
V R E F 5
A 1 7
A 2 2
V C C
V C C
R S V
A 2 5
E D G C T R L
A 1 9
V S S
V S S
R S V
A 1 0
A 5
A 8
A 4
B N R
R E Q 1
R E Q 2
R S V
R S 1
V C C
R S 0
T H E R M
T R I P
S L P
V C C
V S S
V C C
A 2 1
V S S
V C C
V S S
V C C
V S S
V C C
V S S
V C C
V S S
V C C
V S S
V C C
V S S
V C C
B S E L 1
B S E L 0
S M I
V I D 3
V C C
V S S
A 2 8
A 3
A 1 1
V R E F 6
A 1 4
R S V
R E Q 0
L O C K
V R E F 7
R S V
P W R G D R S 2
R S V
T M S
V C C
V S S
V S S
V S S
A 1 5
A 1 3
A 9
R S V
R S V
A 7
R E Q 4
R E Q 3
R S V
H I T M
H I T
D B S Y
T H R M D N
T H R M D P
T C K
V I D 0
V I D 2
R S V
V C C
V S S
V C C
V S S
V C C
V S S
V C C
V S S
V C C
V S S
V C C
V S S
V C C
V S S
V C C
V S S
V I D 1
V S S
A 1 2
A 1 6
A 6
R S V
R S V
R S V
B P R I
D E F E R
R S V
R S V
T R D Y
D R D Y
B R 0
A D S
T R S T
T D I
T D O
P I N S I D E V I E W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24 25
26
27
28
29
30
31 32
33
34
35
36
37
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24 25
26
27
28
29
30
31 32
33
34
35
36
37
AN
A M
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Z
Y
X
W
V
U
T
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Signal
Type
Description
A[31:3]#
I/O
The A[31:3]# (Address) signals define a 2
32
-byte physical memory address space.
When ADS# is active, these pins transmit the address of a transaction; when ADS# is inactive, these pins transmit
transaction type information. These signals must connect the appropriate pins of all agents on the Intel Celeron pro-
cessor system bus. The A[31:24]# signals are parity-protected by the AP1# parity signal, and the A[23:3]# signals are
parity-protected by the AP0# parity signal.
On the active-to-inactive transition of RESET#, the processors sample the A[31:3]# pins to determine their power-on
configuration.
transaction type information. These signals must connect the appropriate pins of all agents on the Intel Celeron pro-
cessor system bus. The A[31:24]# signals are parity-protected by the AP1# parity signal, and the A[23:3]# signals are
parity-protected by the AP0# parity signal.
On the active-to-inactive transition of RESET#, the processors sample the A[31:3]# pins to determine their power-on
configuration.
A20M#
I
If the A20M# (Address-20 Mask) input signal is asserted, the Intel Celeron processor masks physical address bit 20
(A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting
A20M# emulates the 8086 processor’s address wrap-around at the 1MB boundary.
Assertion of A20M# is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it
must be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction.
(A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting
A20M# emulates the 8086 processor’s address wrap-around at the 1MB boundary.
Assertion of A20M# is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it
must be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction.
ADS#
I/O
The ADS# (Address Strobe) signal is asserted to indicate the validity of the transaction address on the A[31:3]# pins.
All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal
snoop, or deferred reply ID match operations associated with the new transaction.
This signal must connect the appropriate pins on all Intel Celeron processor system bus agents.
All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal
snoop, or deferred reply ID match operations associated with the new transaction.
This signal must connect the appropriate pins on all Intel Celeron processor system bus agents.
BCLK
I
The BCLK (Bus Clock) signal determines the bus frequency. All Intel Celeron processor system bus agents must
receive this signal to drive their outputs and latch their inputs on the BCLK rising edge.
All external timing parameters are specified with respect to the BCLK signal.
receive this signal to drive their outputs and latch their inputs on the BCLK rising edge.
All external timing parameters are specified with respect to the BCLK signal.
BNR#
I/O
The BNR# (Block Next Request) signal is used to assert a bus stall by any bus agent who is unable to accept new bus
transactions. During a bus stall, the current bus owner cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same time, BNR# is a wire-OR signal which must con-
nect the appropriate pins of all Intel Celeron processor system bus agents. In order to avoid wire-OR glitches associ-
ated with simultaneous edge transitions driven by multiple drivers, BNR# is activated on specific clock edges and
sampled on specific clock edges.
transactions. During a bus stall, the current bus owner cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same time, BNR# is a wire-OR signal which must con-
nect the appropriate pins of all Intel Celeron processor system bus agents. In order to avoid wire-OR glitches associ-
ated with simultaneous edge transitions driven by multiple drivers, BNR# is activated on specific clock edges and
sampled on specific clock edges.
BP[3:2]#
I/O
The BP[3:2]# (Breakpoint) signals are outputs from the processor that indicate the status of breakpoints.
BPM[1:0]#
I/O
The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance monitor signals. They are outputs from
the processor which indicate the status of breakpoints and programmable counters used for monitoring processor per-
formance.
the processor which indicate the status of breakpoints and programmable counters used for monitoring processor per-
formance.
BPRI#
I
The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the Intel Celeron processor system bus. It
must connect the appropriate pins of all Intel Celeron processor system bus agents. Observing BPRI# active (as
asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of
an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then
releases the bus by deasserting BPRI#.
must connect the appropriate pins of all Intel Celeron processor system bus agents. Observing BPRI# active (as
asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of
an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then
releases the bus by deasserting BPRI#.
UP-5900VS
CIRCUIT DESCRIPTION
5 – 9
BSEL[1:0]
I/O
These signals are used to select the system bus frequency. The frequency is determined by the processor(s), chipset,
and frequency synthesizer capabilities. All system bus agents must operate at the same frequency Individual proces-
sors will only operate at their specified front side bus (FSB) frequency. On motherboards which support operation at
either 66 MHz or 100 MHz, a BSEL[1:0] = “x1” will select a 100 MHz system bus frequency and a BSEL[1:0] = “x0” will
select a 66 MHz system bus frequency.
These signals must be pulled up to 2.5V or 3.3 V with 1 K
and frequency synthesizer capabilities. All system bus agents must operate at the same frequency Individual proces-
sors will only operate at their specified front side bus (FSB) frequency. On motherboards which support operation at
either 66 MHz or 100 MHz, a BSEL[1:0] = “x1” will select a 100 MHz system bus frequency and a BSEL[1:0] = “x0” will
select a 66 MHz system bus frequency.
These signals must be pulled up to 2.5V or 3.3 V with 1 K
Ω
resistor and provided as a frequency selection signal to the
clock driver/synthesizer.
note: BSEL1 is not used by the Celeron processor.
note: BSEL1 is not used by the Celeron processor.
BR0#
I/O
The BR0# (Bus Request) pin drives the BREQ[0]# signal in the system. During power-up configuration, the central
agent asserts the BREQ0# bus signal in the system to assign the symmetric agent ID to the processor. The processor
samples it’s BR0# pin on the active-to-inactive transition of RESET# to obtain it’s symmetric agent ID. The processor
asserts BR0# to request the system bus.
agent asserts the BREQ0# bus signal in the system to assign the symmetric agent ID to the processor. The processor
samples it’s BR0# pin on the active-to-inactive transition of RESET# to obtain it’s symmetric agent ID. The processor
asserts BR0# to request the system bus.
CPUPRES# (PPGA
and FC-PGA only)
and FC-PGA only)
O
The CPUPRES# signal provides the ability for a system board to detect the presence of a processor. This pin is a
ground on the processor indicating to the system that a processor is installed.
The CPUPRES# signal is defined to allow a system design to detect the presence of a terminator device or processor
in a PGA370 socket. Combined with the VID combination of VID[3:0]= 1111, a system can determine if a socket is
occupied, and whether a processor core is present.
PGA370 Socket Occupation Truth Table
ground on the processor indicating to the system that a processor is installed.
The CPUPRES# signal is defined to allow a system design to detect the presence of a terminator device or processor
in a PGA370 socket. Combined with the VID combination of VID[3:0]= 1111, a system can determine if a socket is
occupied, and whether a processor core is present.
PGA370 Socket Occupation Truth Table
D[63:0]#
I/O
The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit data path between the Intel Celeron
processor system bus agents, and must connect the appropriate pins on all such agents. The data driver asserts
DRDY# to indicate a valid data transfer.
processor system bus agents, and must connect the appropriate pins on all such agents. The data driver asserts
DRDY# to indicate a valid data transfer.
DBSY#
I/O
The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving data on the Intel Celeron processor
system bus to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal
must connect the appropriate pins on all Intel Celeron processor system bus agents.
system bus to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal
must connect the appropriate pins on all Intel Celeron processor system bus agents.
DEFER#
I
The DEFER# signal is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion.
Assertion of DEFER# is normally the responsibility of the addressed memory or I/O agent. This signal must connect the
appropriate pins of all Intel Celeron processor system bus agents.
Assertion of DEFER# is normally the responsibility of the addressed memory or I/O agent. This signal must connect the
appropriate pins of all Intel Celeron processor system bus agents.
DRDY#
I/O
The DRDY# (Data Ready) signal is asserted by the data driver on each data transfer, indicating valid data on the data
bus. In a multicycle data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appro-
priate pins of all Intel Celeron processor system bus agents.
bus. In a multicycle data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appro-
priate pins of all Intel Celeron processor system bus agents.
EDGCTRL
I
The EDGCTRL input provides AGTL+ edge control and should be pulled up to VCCCORE with a 51
Ω
m
5% resistor.
NOTE: This signal is NOT used on the FC-PGA package.
EMI
(S.E.P.P. only)
(S.E.P.P. only)
I
EMI pins should be connected to motherboard ground and/or to chassis ground through zero ohm (0
Ω
) resistors. The
zero ohm resistors should be placed in close proximity to the Intel Celeron processor connector. The path to chassis
ground should be short in length and have a low impedance. These pins are used for EMI management purposes.
ground should be short in length and have a low impedance. These pins are used for EMI management purposes.
FERR#
O
The FERR# (Floating-point Error) signal is asserted when the processor detects an unmasked floating-point error.
FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems
using MS-DOS*-type floating-point error reporting.
FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems
using MS-DOS*-type floating-point error reporting.
FLUSH#
I
When the FLUSH# input signal is asserted, the processor writes back all data in the Modified state from the internal
cache and invalidates all internal cache lines. At the completion of this operation, the processor issues a Flush
Acknowledge transaction.
The processor does not cache any new data while the FLUSH# signal remains asserted.
FLUSH# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it
must be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction.
On the active-to-inactive transition of RESET#, the processor samples FLUSH# to determine its power-on configura-
tion.
cache and invalidates all internal cache lines. At the completion of this operation, the processor issues a Flush
Acknowledge transaction.
The processor does not cache any new data while the FLUSH# signal remains asserted.
FLUSH# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it
must be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction.
On the active-to-inactive transition of RESET#, the processor samples FLUSH# to determine its power-on configura-
tion.
HIT#, HITM#
I/O
The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop operation results, and must connect
the appropriate pins of all Intel Celeron processor system bus agents. Any such agent may assert both HIT# and
HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM#
together.
the appropriate pins of all Intel Celeron processor system bus agents. Any such agent may assert both HIT# and
HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM#
together.
IERR#
O
The IERR# (Internal Error) signal is asserted by a processor as the result of an internal error. Assertion of IERR# is
usually accompanied by a SHUTDOWN transaction on the Intel Celeron processor system bus. This transaction may
optionally be converted to an external error signal (e.g., NMI) by system core logic.
The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#.
usually accompanied by a SHUTDOWN transaction on the Intel Celeron processor system bus. This transaction may
optionally be converted to an external error signal (e.g., NMI) by system core logic.
The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#.
IGNNE#
I
The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to ignore a numeric error and continue to
execute noncontrol floating-point instructions.
If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous
floating-point instruction caused an error.
IGNNE# has no effect when the NE bit in control register 0 is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it
must be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction.
execute noncontrol floating-point instructions.
If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous
floating-point instruction caused an error.
IGNNE# has no effect when the NE bit in control register 0 is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it
must be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction.
Signal
Type
Description
Signal
Value
Status
CPUPRES#
VID[3:0]
VID[3:0]
CPUPRES#
VID[3:0]
VID[3:0]
CPUPRES#
VID[3:0]
VID[3:0]
1
Any value
Any value
0
Anything other than '1111'
Anything other than '1111'
0
1111
1111
PGA370 socket not occupied.
Processor core installed in the PGA370
socket.
socket.
Terminator device installed in the
PGA370 socket (i.e., no core present).
PGA370 socket (i.e., no core present).
UP-5900VS
CIRCUIT DESCRIPTION
5 – 10
INIT#
I
The INIT# (Initialization) signal, when asserted, resets integer registers inside all processors without affecting their
internal (L1) caches or floating-point registers.
Each processor then begins execution at the power-on Reset vector configured during power-on configuration. The
processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must con-
nect the appropriate pins of all bus agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-
Test (BIST).
internal (L1) caches or floating-point registers.
Each processor then begins execution at the power-on Reset vector configured during power-on configuration. The
processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must con-
nect the appropriate pins of all bus agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-
Test (BIST).
LINT[1:0]
I
The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins of all APIC Bus agents, including all
processors and the core logic or I/O APIC component. When the APIC is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward
compatible with the signals of those names on the Pentium processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the APIC register space to be used either
as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is
the default configuration.
processors and the core logic or I/O APIC component. When the APIC is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward
compatible with the signals of those names on the Pentium processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the APIC register space to be used either
as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is
the default configuration.
LOCK#
I/O
The LOCK# signal indicates to the system that a transaction must occur atomically.
This signal must connect the appropriate pins of all system bus agents. For a locked sequence of transactions, LOCK#
is asserted from the beginning of the first transaction end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the system bus, it will wait until it observes LOCK#
deasserted. This enables symmetric agents to retain ownership of the system bus throughout the bus locked operation
and ensure the atomicity of lock.
This signal must connect the appropriate pins of all system bus agents. For a locked sequence of transactions, LOCK#
is asserted from the beginning of the first transaction end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the system bus, it will wait until it observes LOCK#
deasserted. This enables symmetric agents to retain ownership of the system bus throughout the bus locked operation
and ensure the atomicity of lock.
PICCLK
I
The PICCLK (APIC Clock) signal is an input clock to the processor and core logic or I/O APIC which is required for
operation of all processors, core logic, and I/O APIC components on the APIC bus.
operation of all processors, core logic, and I/O APIC components on the APIC bus.
PICD[1:0]
I/O
The PICD[1:0] (APIC Data) signals are used for bidirectional serial message passing on the APIC bus, and must con-
nect the appropriate pins of the Intel Celeron processor for proper initialization.
nect the appropriate pins of the Intel Celeron processor for proper initialization.
PLL1, PLL2
(PGA packages only)
(PGA packages only)
I
All Intel Celeron processors have internal analog PLL clock generators that require quiet power supplies. PLL1 and
PLL2 are inputs to the internal PLL and should be connected to VCCCORE through a low-pass filter that minimizes jit-
ter.
PLL2 are inputs to the internal PLL and should be connected to VCCCORE through a low-pass filter that minimizes jit-
ter.
PRDY#
O
The PRDY (Probe Ready) signal is a processor output used by debug tools to determine processor debug readiness.
PREQ#
I
The PREQ# (Probe Request) signal is used by debug tools to request debug operation of the processors.
PWRGOOD
I
The PWRGOOD (Power Good) signal is a 2.5 V tolerant processor input. The processor requires this signal to be a
clean indication that the clocks and power supplies (VCCCORE, etc.) are stable and within their specifications. Clean
implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the
power supplies are turned on until they come within specification. The signal must then transition monotonically to a
high (2.5 V) state.
Figure 39 illustrates the relationship of PWRGOOD to other system signals.
PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising
edge of PWRGOOD. It must also meet the minimum pulse width specification in Table 17 and Table 18, and be fol-
lowed by a 1ms RESET# pulse.
The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage
sequencing issues. It should be driven high throughout boundary scan operation.
PWRGOOD Relationship at Power-On
clean indication that the clocks and power supplies (VCCCORE, etc.) are stable and within their specifications. Clean
implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the
power supplies are turned on until they come within specification. The signal must then transition monotonically to a
high (2.5 V) state.
Figure 39 illustrates the relationship of PWRGOOD to other system signals.
PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising
edge of PWRGOOD. It must also meet the minimum pulse width specification in Table 17 and Table 18, and be fol-
lowed by a 1ms RESET# pulse.
The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage
sequencing issues. It should be driven high throughout boundary scan operation.
PWRGOOD Relationship at Power-On
REQ[4:0]#
I/O
The REQ[4:0]# (Request Command) signals must connect the appropriate pins of all processor system bus agents.
They are asserted by the current bus owner over two clock cycles to define the currently active transaction type.
They are asserted by the current bus owner over two clock cycles to define the currently active transaction type.
RESET#
I
Asserting the RESET# signal resets the processor to a known state and invalidates the L1 cache without writing back
any of the contents. RESET# must stay active for at least one millisecond after VCCCORE and CLK have reached their
proper specifications. On observing active RESET#, all system bus agents will deassert their outputs within two clocks.
A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. These
configuration options are described in the Pentium Pro Family Developerfs Manual, Volume 1: Specifications (Order
Number 242690).
The processor may have its outputs tristated via power-on configuration. Otherwise, if INIT# is sampled active during
the active-to-inactive transition of RESET#, the processor will execute its Built-in Self-Test (BIST). Whether or not BIST
is executed, the processor will begin program execution at the power on Reset vector (default 0_FFFF_FFF0h).
RESET# must connect the appropriate pins of all processor system bus agents.
any of the contents. RESET# must stay active for at least one millisecond after VCCCORE and CLK have reached their
proper specifications. On observing active RESET#, all system bus agents will deassert their outputs within two clocks.
A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. These
configuration options are described in the Pentium Pro Family Developerfs Manual, Volume 1: Specifications (Order
Number 242690).
The processor may have its outputs tristated via power-on configuration. Otherwise, if INIT# is sampled active during
the active-to-inactive transition of RESET#, the processor will execute its Built-in Self-Test (BIST). Whether or not BIST
is executed, the processor will begin program execution at the power on Reset vector (default 0_FFFF_FFF0h).
RESET# must connect the appropriate pins of all processor system bus agents.
RS[2:0]#
I
The RS[2:0]# (Response Status) signals are driven by the response agent (the agent responsible for completion of the
current transaction), and must connect the appropriate pins of all processor system bus agents.
current transaction), and must connect the appropriate pins of all processor system bus agents.
RTTCTRL
I
The RTTCTRL input signal provides AGTL+ termination control. The Celeron FC-PGA processor samples this input to
sense the presence of motherboard AGTL+ termination.
sense the presence of motherboard AGTL+ termination.
SLEWCTRL
I
The SLEWCTRL input signal provides AGTL+ slew rate control. The Celeron FC-PGA processor samples this input to
determine the slew rate for AGTL+ signals when it is the driving agent.
determine the slew rate for AGTL+ signals when it is the driving agent.
Signal
Type
Description
BCLK
PWRGOOD
RESET#
1 ms
VCC
CORE
,
V
REF
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