Sharp ER-A771 (serv.man3) Service Manual ▷ View online
ER-A771VS
CIRCUIT DESCRIPTION
7 – 15
CPU
Note: Signals prefixed with a slash “/” are active in low level.
No.
CPU
Signal
name
I/O
Remarks
1
PE14
PE14
I
N.U. (GND)
2
PE15
/WP
I
FLASH write Status
3
Vss
GND
4
A0
LA0
O
Address Bus
5
A1
LA1
O
6
A2
LA2
O
7
A3
LA3
O
8
A4
LA4
O
9
A5
LA5
O
10
A6
LA6
O
11
A7
LA7
O
12
A8
LA8
O
13
A9
LA9
O
14
A10
LA10
O
15
A11
LA11
O
16
A12
LA12
O
17
A13
LA13
O
18
A14
LA14
O
19
A15
LA15
O
20
A16
LA16
O
21
Vcc
+5V
22
A17
LA17
O
Address Bus
23
Vss
GND
24
/IRQ0
/INTHW
I
Host write end interrupt
25
/IRQ1
/INTHR
I
Host write end interrupt
26
/IRQ2
/INTLAN
I
Interrupt from LANC
27
Vss
GND
28
/IRQ3
/IRQ3
I
N.U. (+5V)
29
A18
LA18
O
Address Bus
30
A19
LA19
O
Address Bus
31
/WAIT
IOCHRDY
I
Wait from LANC
32
PB9
PB9
I
N.U. (GND)
33
Vss
GND
34
/RD
/MRD
O
Memory Read
35
/WDTOVF /WDTOVF
O
N.U. (OPEN)
36
/WRH
/WRH
O
N.U. (OPEN)
37
Vcc
+5V
38
/WRL
/MWE
O
Memory Write
39
Vss
GND
40
/CS1
/CS1
O
SRAM Chip Select
41
/CS0
/CS0
O
FLASH Chip Select
42
PA9
PA9
I
N.U. (GND)
43
PA8
PA8
I
N.U. (GND)
44
/CS3
/CS3
O
LANC Chip Select
45
/CS2
/CS2
O
DP-RAM Chip Select
46
PA5
PA5
I
N.U. (GND)
47
PA4
PA4
I
N.U. (GND)
48
PA3
PA3
I
N.U. (GND)
49
PA2
PA2
I
N.U. (GND)
50
PA1
PA1
I
N.U. (GND)
51
PA0
PA0
I
N.U. (GND)
52
D15
HD15
I/O
N.U. (Pull-Down)
53
D14
HD14
I/O
N.U. (Pull-Down)
54
D13
HD13
I/O
N.U. (Pull-Down)
55
Vss
GND
56
D12
HD12
I/O
N.U. (Pull-Down)
57
D11
HD11
I/O
N.U. (Pull-Down)
58
D10
HD10
I/O
N.U. (Pull-Down)
59
D9
HD9
I/O
N.U. (Pull-Down)
60
D8
HD8
I/O
N.U. (Pull-Down)
61
Vss
GND
62
D7
HD7
I/O
DATA Bus
63
D6
HD6
I/O
64
D5
HD5
I/O
65
Vcc
+5V
66
D4
HD4
I/O
DATA Bus
67
D3
HD3
I/O
68
D2
HD2
I/O
69
D1
HD1
I/O
70
D0
HD0
I/O
s71
Vss
GND
72
XTAL
XTAL
O
Oscillator connection terminal
73
MD3
MD3
I
Mode terminal
74
EXTAL
EXTAL
I
Oscillator connection terminal
75
MD2
MD2
I
Mode terminal 2
76
NMI
NMI
I
N.U. (+5V)
77
Vcc
+5V
78
MD1
MD1
I
Mode terminal 1
79
MD0
MD0
I
Mode terminal 0
80
PLLVcc
PLLVcc
81
PLLCAP
PLLCAP
82
PLLVss
PLLVss
83
PA15
PA15
I
N.U.(Pull-Down)
84
/RES
/LRES
I
Hardware Reset
85
PE0
PE0
I
N.U. (GND)
86
PE1
PE1
I
N.U. (GND)
87
PE2
PE2
I
N.U. (GND)
88
PE3
PE3
I
N.U. (GND)
89
PE4
PE4
I
N.U. (GND)
90
Vss
GND
91
PF0
PF0
I
N.U. (GND)
92
PF1
PF1
I
N.U. (GND)
93
PF2
PF2
I
N.U. (GND)
94
PF3
PF3
I
N.U. (GND)
95
PF4
PF4
I
N.U. (GND)
96
PF5
PF5
I
N.U. (GND)
97
AVss
GND
98
PF6
PF6
I
N.U. (GND)
99
PF7
PF7
I
N.U. (GND)
100
AVcc
+5V
101
Vss
GND
102
PE5
PE5
I
N.U. (GND)
103
Vcc
+5V
104
PE6
PE6
I
N.U. (GND)
105
PE7
PE7
I
N.U. (GND)
106
PE8
/SRRQ
O
Slave read end request
107
PE9
/SWRQ
O
Slave write end request
108
PE10
/HRACK
O
Host read interrupt cancel
109
Vss
GND
110
PE11
/HWACK
O
Host write interrupt cancel
111
PE12
PE12
O
N.U. (OPEN)
112
PE13
/RSTDRV
O
Soft Reset for LANC
No.
CPU
Signal
name
I/O
Remarks
ER-A771VS
CIRCUIT DESCRIPTION
7 – 16
2) LAN CONTROLLER (RTL8019AS)
2)-1. Features:
• 100-pin PQFP
• Supports PnP auto detect mode
• Compliant to Ethernet II and IEEE802.3 10Base5, 10Base2,
10BaseT
• Software compatible with NE2000 on both 8 and 16-bit slots
• Supports both jumper and jumperless modes
• Supports Microsofts Plug and Play configuration for jumperless mode
• Supports Full-Duplex Ethernet function to double channel bandwidth
• Supports three level power down modes:
– Sleep
– Power down with internal clock running
– Power down with internal clock halted
• Built-in data prefetch function to improve performance
• Supports UTP, AUI & BNC auto-detect
• Supports auto polarity correction for 10BaseT
• Supports 8 IRQ lines
• Supports 16 I/O base address options
--- and extra I/O address fully decode mode
• Supports 16K, 32K, 64K and 16K-page mode access to BROM (up to
256 pages with 16K bytes/page)
• Supports BROM disable command to release memory after remote
boot
• Supports flash memory read/write
• 16k byte SRAM built in
• Uses a 9346 (64*16-bit EEPROM) to store resource configurations
and ID parameters
• Capable of programming blank 9346 on board for manufacturing con-
venience
• Support 4 diagnostic LED pins with programmable outputs
2)-2. General Description
The RTL8019AS is a highly integrated Ethernet Controller which offers
a simple solution to implement a Plug and Play NE2000 compatible
adapter with full-duplex and power down features.
With the three level power down control features, the RTL8019AS is
made to be an ideal choice of the network device for a GREEN PC sys-
tem. The full-duplex function enables simultaneously transmission and
tem. The full-duplex function enables simultaneously transmission and
reception on the twisted-pair link to a full-duplex Ethernet switching hub.
This feature not only increases the channel bandwidth from 10 to 20
Mbps but also avoids the performance degrading problem due to the
Mbps but also avoids the performance degrading problem due to the
channel contention characteristics of the Ethernet CSMA/CD protocol.
The RTL8019AS provides the auto-detect capability between the inte-
grated 10BaseT transceiver, BNC and AUI interface. Besides, the
10BaseT transceiver can automatically correct the polarity error on its
receiving pair.
receiving pair.
The RTL8019AS is built in with a 16K-byte SRAM in a single chip. It is
designed not only to provide more friendly functions but also to save the
effort of SRAM sourcing and inventory.
effort of SRAM sourcing and inventory.
2)-3. Pin Configuration
LAN Controller
No.
CPU
Signal
name
I/O
Remarks
1
INT3
INT3
O
N.U. (Pull-Down)
2
INT2
INT2
O
N.U. (Pull-Down)
3
INT1
INT1
O
N.U. (Pull-Down)
4
INT0
/INTLAN
O
Interrupt to CPU
5
SA0
LA0
I
Address Bus
6
VDD
+5V
7
SA1
LA1
I
Address Bus
8
SA2
LA2
I
9
SA3
LA3
I
10
SA4
LA4
I
11
SA5
LA5
I
12
SA6
LA6
I
13
SA7
LA7
I
14
GND
GND
15
SA8
LA8
I
Address Bus
16
SA9
LA9
I
17
VDD
+5V
18
SA10
LA10
I
Address Bus
19
SA11
LA11
I
20
SA12
LA12
I
21
SA13
LA13
I
22
SA14
LA14
I
23
SA15
LA15
I
24
SA16
LA16
I
25
SA17
LA17
I
26
SA18
LA18
I
27
SA19
LA19
I
28
GND
GND
29
IORB
/MRD
I
Memory Read
30
IOWB
/MWE
I
Memory Write
31
SMEMRB
SMEMRB
I
N.U. (Pull-Up)
81 BD3 [IOS0]
82 BD2 [IOS1]
83 GND
83 GND
84 BD1 [IOS2]
85 BD0 [IOS3]
85 BD0 [IOS3]
86 GND
87 SD15
87 SD15
89 VDD
90 SD13
91 SD12
92 SD11
90 SD13
91 SD12
92 SD11
93 SD10
94 SD9
94 SD9
95 SD8
96 IOCS16B [SLOT16]
96 IOCS16B [SLOT16]
97 INT7 [IRQ15]
98 INT6 [IRQ12]
99 INT5 [IRQ11]
100 INT4 [IRQ10]
98 INT6 [IRQ12]
99 INT5 [IRQ11]
100 INT4 [IRQ10]
88 SD14
2 INT2 [IRQ4]
3 INT1 [IRQ3]
4 INT0 [IRQ2/9]
3 INT1 [IRQ3]
4 INT0 [IRQ2/9]
5 SA0
6 VDD
6 VDD
7 SA1
8 SA2
9 SA3
10 SA4
11 SA5
12 SA6
8 SA2
9 SA3
10 SA4
11 SA5
12 SA6
13 SA7
14 GND
15 SA8
14 GND
15 SA8
29 IORB
28 GND
27 SA19
26 SA18
25 SA17
24 SA16
23 SA15
22 SA14
21 SA13
20 SA12
28 GND
27 SA19
26 SA18
25 SA17
24 SA16
23 SA15
22 SA14
21 SA13
20 SA12
30 IOWB
19 SA11
18 SA10
17 VDD
16 SA9
17 VDD
16 SA9
64 AUI
63 LED2 [LED_TX]
62 LED1 [LED_RX] [LED_CRS]
61 LED0 [LED_COL] [LED_LINK]
63 LED2 [LED_TX]
62 LED1 [LED_RX] [LED_CRS]
61 LED0 [LED_COL] [LED_LINK]
60 LEDBNC
59 TPIN+
58 TPIN-
57 VDD
56 RX+
55 RX-
54 CD+
53 CD-
52 GND
51 X2
59 TPIN+
58 TPIN-
57 VDD
56 RX+
55 RX-
54 CD+
53 CD-
52 GND
51 X2
69 BA18 [BS2]
70 VDD
71 BA17 [BS3]
72 BA16 [BS4]
70 VDD
71 BA17 [BS3]
72 BA16 [BS4]
73 BA15
74 BA14 [PL0]
75 BCSB
74 BA14 [PL0]
75 BCSB
76 EECS
77 BD7 [PL1][EEDO]
78 BD6 [IRQS0][EEDI]
79 BD5 [IRQS1][EESK]
80 BD4 [IRQS2]
77 BD7 [PL1][EEDO]
78 BD6 [IRQS0][EEDI]
79 BD5 [IRQS1][EESK]
80 BD4 [IRQS2]
RTL8019AS
1 INT3 [IRQ5]
68 BA19 [BS1]
67 BA20 [BS0]
66 BA21 [PNP]
50 X1
49 TX+
48 TX-
48 TX-
47 VDD
46 TPOUT-
45 TPOUT+
44 GND
43 SD7
42 SD6
46 TPOUT-
45 TPOUT+
44 GND
43 SD7
42 SD6
39 SD3
38 SD2
37 SD1
36 SD0
38 SD2
37 SD1
36 SD0
34 AEN
33 RSTDRV
32 SMEMWB
33 RSTDRV
32 SMEMWB
31 SMEMRB
41 SD5
40 SD4
40 SD4
35 IOCHRDY
65 JP
ER-A771VS
CIRCUIT DESCRIPTION
7 – 17
Note: Signals suffixed with the letter “B” are active in low level.
5. MEMORY MAP
32
SMEMWB SMEMWB
I
N.U. (Pull-Up)
33
RSTDRV
RSTDRV
I
Hardware Reset
34
AEN
/CS3
I
Chip Select
35
IOCHRDY
/WAIT
O
Wait to CPU
36
SD0
LD0
I/O
DATA Bus
37
SD1
LD1
I/O
38
SD2
LD2
I/O
39
SD3
LD3
I/O
40
SD4
LD4
I/O
41
SD5
LD5
I/O
42
SD6
LD6
I/O
43
SD7
LD7
I/O
44
GND
GND
45
TPOUT+
TPOUT+
O
10Base-T output +
46
TPOUT-
TPOUT-
O
10Base-T output -
47
VDD
+5V
48
TX-
TX-
O
N.U. (Pull-Down)
49
TX+
TX+
O
N.U. (Pull-Down)
50
X1
X1
I
Oscillator connection terminal
51
X2
X2
O
Oscillator connection terminal
52
GND
GND
53
CD-
CD-
I
N.U. (OPEN)
54
CD+
CD+
I
N.U. (OPEN)
55
RX-
RX-
I
N.U. (OPEN)
56
RX+
RX+
I
N.U. (OPEN)
57
VDD
+5V
58
TPN-
TPIN-
I
10Base-T input -
59
TPN+
TPIN+
I
10Base-T input +
60
LEDBNC
LEDBNC
O
N.U. (OPEN)
61
LED0
LED0
O
N.U. (OPEN)
62
LED1
LED1
O
N.U. (OPEN)
63
LED2
LED2
O
N.U. (OPEN)
64
AUI
AUI
I
GND
65
JP
JP
I
Pull-Up
66
PNP
PNP
I
OPEN
67
BS0
BS0
I
OPEN
68
BS1
BS1
I
OPEN
69
BS2
BS2
I
OPEN
70
VDD
+5V
71
BS3
BS3
I
OPEN
72
BS4
BS4
I
OPEN
73
BA15
BA15
O
N.U. (OPEN)
74
PL0
PL0
I
OPEN
75
BCSB
BCSB
O
N.U. (OPEN)
76
EECS
EECS
O
N.U. (OPEN)
77
PL1
PL1
I
OPEN
78
IRQS0
IRQS0
I
OPEN
79
IRQS1
IRQS1
I
OPEN
80
IRQS2
IRQS2
I
OPEN
81
IOS0
IOS0
I
OPEN
82
IOS1
IOS1
I
OPEN
83
GND
GND
84
IOS2
IOS2
I
OPEN
85
IOS3
IOS3
I
OPEN
86
GND
GND
87
SD15
SD15
I/O
N.U. (Pull-Down)
88
SD14
SD14
I/O
N.U. (Pull-Down)
89
VDD
+5V
No.
CPU
Signal
name
I/O
Remarks
90
SD13
SD13
I/O
N.U. (Pull-Down)
91
SD12
SD12
I/O
N.U. (Pull-Down)
92
SD11
SD11
I/O
N.U. (Pull-Down)
93
SD10
SD10
I/O
N.U. (Pull-Down)
94
SD9
SD9
I/O
N.U. (Pull-Down)
95
SD8
SD8
I/O
N.U. (Pull-Down)
96
SLOT16
SLOT16
I
Pull-Down
97
INT7
INT7
O
N.U. (Pull-Down)
98
INT6
INT6
O
N.U. (Pull-Down)
99
INT5
INT5
O
N.U. (Pull-Down)
100
INT4
INT4
O
N.U. (Pull-Down)
No.
CPU
Signal
name
I/O
Remarks
Flash
SRAM
CS0 SPACE
CS1 SPACE
CS2 SPACE
CS3 SPACE
Dual-Port SRAM
LAN Controller
H'FFFFFFFF
H'FFFFF000
H'FFFF8800
H'FFFF8000
H'02000000
H'01000000
H'00C*****
H'00C00000
H'00800FFF
H'00800000
H'00407FFF
H'00400000
H'0007FFFF
H'00000000
DRAMS space
Reserved
Reserved
Built-in peripheral
Module
Built-in RAM
2 The CS1 space is a physical
space of 4 MB. Is uses LA0~LA14
alone and thus LAP AROUND
occurs.
The data bus size is 8 bits.
space of 4 MB. Is uses LA0~LA14
alone and thus LAP AROUND
occurs.
The data bus size is 8 bits.
1 The CS0 space is a physical
of 4 MB. It uses LA0~LA16
alone and thus LAP AROUND
occurs.
In addition, the data bus size is
set to 8 bits using the operation
mode setting terminal of the CPU.
of 4 MB. It uses LA0~LA16
alone and thus LAP AROUND
occurs.
In addition, the data bus size is
set to 8 bits using the operation
mode setting terminal of the CPU.
3 The CS2 space is a physical
space of 4 MB. It uses LA0~LA11
alone and thus LAP
AROUND occurs.
The data bus size is 8 bits.
space of 4 MB. It uses LA0~LA11
alone and thus LAP
AROUND occurs.
The data bus size is 8 bits.
4 The CS3 space is a physical
space of 4 MB. Is uses LA0~LA19
alone and thus LAP AROUND
occurs.
The data bus size of the LAN
controller is fixed to 8 bits.
space of 4 MB. Is uses LA0~LA19
alone and thus LAP AROUND
occurs.
The data bus size of the LAN
controller is fixed to 8 bits.
ER-A771VS
CIRCUIT DESCRIPTION
7 – 18
6. INTERFACE WITH HOST CPU
1) SIGNAL LINES
The following signal lines are required for the interface with the host CPU.
Note: Signals prefixed with a slash “/” are active in low level.
Cautions to be taken when designing the host side
1.
It is preferable that /LRES signal to be input into the board can also
be controlled by software.
2.
The access timing satisfies the dual-port SRAM specification.
• Timing Waveform of Read Cycle No. 1, Either Side
(1,2,4)
• Timing Waveform of Read Cycle No. 2, Either Side
(1,3)
NOTES:
1.
Timing depends on which signal is asserted last, OE or CE.
2.
Timing depends on which signal is de-asserted first, OE or CE.
3.
R/W = VIH.
4.
The start of valid data depends on which timing becomes effective,
tAOE, tACE or tAA
5.
tAA is for RAM Address Access and tSAA for is Semaphore
Address Access.
• Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
(1,5,8)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE =VIL and R/
W = VIL.
3. tWR is measured from the earlier of CE or R/W going to VIH to the
end-of-write cycle.
4. During this period, the I/O pins are in the output state, and the input
signals must not be applied.
5. If the CE = VIL transition occurs simultaneously with or after the R/
W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted
last.
7. This parameter is guaranteed by device characterization, but is not
production tested. Transition is measured
m
500mV from the steady
state with the Output Test Load (Figure 2).
8. If OE = VIL during a R/W controlled write cycle, the write pulse
width must be the larger of tWP or (tWZ + tDW) to allow the I/O driv-
ers to turn off data to be placed on the bus for the required tDW. If
ers to turn off data to be placed on the bus for the required tDW. If
OE = VIH during an R/W controlled write cycle, this requirement
does not apply and the write pulse can be as short as the specified
tWP.
tWP.
Signal name
I/O
Description
Connected to
Connection pin
A0~A11
I
Address Bus from host CPU
DP-RAM
A0R~A11R
D0~D7
I/O
Data Bus from host CPU
DP-RAM
D0R~D7R
/RD
I
Read signal from host CPU
DP-RAM
/OER
/WR
I
Write signal from host CPU
DP-RAM
R/WR
/DPCS
I
Chip select from host CPU
DP-RAM
/CER
/LRES
I
Rest signal for this board from host CPU
Board CPU
/RES
/INTSR
O
Data read end interrupt from board CPU
LOGIC
/INTSW
O
Data write end interrupt from board CPU
LOGIC
A13~A15
I
Address bus from host CPU (for decode)
LOGIC
Vcc
Power (+5V)
GND
GND
,
ADDRESS
DATA
OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
(5)
t
OH
t
OH
CE
OE
DATA
OUT
CURRENT
I
SB
ICC
50%
VALID DATA
(4)
50%
t
ACE
t
AOE
(4)
t
LZ
(1)
t
LZ
(1)
t
PU
t
HZ
(2)
t
HZ
(2)
t
PD
ADDRESS
R/W
DATA
OUT
DATA
IN
OE
CE
t
WC
t
AS
(6)
t
AW
t
WP
(2)
(4)
(4)
t
LZ
(7)
t
DW
t
DH
t
OW
t
HZ
(7)
t
HZ
(7)
t
WR
(3)
t
WZ
(7)
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