Sharp ER-A771 (serv.man3) Service Manual ▷ View online
ER-A771VS
CIRCUIT DESCRIPTION
7 – 11
39
CTS2Z
VCC
IS
RS-232 clear to send signal
40
RCVDT2
GND
IS
RS-232 reception to send
signal
signal
41
/CI2
VCC
IS
+5V
42
/CS2
NC
O
RS-232 chip select signal
43
/CD3
VCC
IS
RS-232: /CD, IN-LINE : /P1
44
BRK3
GND
IS
GND
45
TRNEMP3
GND
IS
GND
46
RCVRDY3
GND
IS
GND
47
TRNRDY3
GND
IS
GND
48
/CTS3
GND
IS
GND
49
RCVDT3
GND
IS
GND
50
/CI3
GND
IS
GND
51
/CS3
NC
O
RS-232/INLINE chip select
signal
signal
52
D0
D0
IO
Data bus (CPU)
53
D1
D1
IO
Data bus (CPU)
54
D2
D2
IO
Data bus (CPU)
55
D3
D3
IO
Data bus (CPU)
56
GND
GND
GND
57
D4
D4
IO
Data bus (CPU)
58
D5
D5
IO
Data bus (CPU)
59
D6
D6
IO
Data bus (CPU)
60
D7
D7
IO
Data bus (CPU)
61
GND
GND
GND
62
VCC
VCC
+5V
63
X1
NC
O OSI14 NC
64
X2
#
I OSI14 System clock
65
XOUT
CLK_USART
O
Clock (USART)
66
TRCK
NC
O
NC
67
AB0
AH0
O
Address bus for USART
68
AB1
AH1
O
Address bus for USART
69
US1CH
GND
IS
GND
70
PX
NC
O
NC
71
/POF
/POFF
IS
POFF signal
72
/RSRQ
/IRQ1
3S
RS232 INTERRUPT
73
/TRV
GND
IS
GND
74
RXDATA0
NC
O
NC
75
TXE
/SRESET
O
INLINE TRNS ENABLE
76
/TRRQ
/TRQ2
3S
INLINE INTERRUPT
77
/TRQ1
/TRQ1
ON6
TIMER INTERRUPT
(RS232)
(RS232)
78
/TRQ2
NC
ON6
TIMER INTERRUPT
(INLINE)
(INLINE)
79
A0
A0
I
Address bus for CPU
80
A1
A1
I
Address bus for CPU
81
A2
A2
I
Address bus for CPU
82
A3
A3
I
Address bus for CPU
83
A4
A4
I
Address bus for CPU
84
A5
A5
I
Address bus for CPU
85
/OPTCS
/OPTCS
I
Option chip select (from
MPCA)
MPCA)
86
/RD
/RDO
I
Read signal (from CPU)
87
/WR
/WRO
I
Write signal (from CPU)
88
/RES
/RES
IS
Reset signal (from CPU)
Pin
NO.
Name
ER-A771
I/O
Description
89
DB0
NC
IO
DATA BUS (USART)
90
DB1
NC
IO
DATA BUS (USART)
91
DB2
NC
IO
DATA BUS (USART)
92
DB3
NC
IO
DATA BUS (USART)
93
GND
GND
GND
94
DB4
NC
IO
DATA BUS (USART)
95
DB5
NC
IO
DATA BUS (USART)
96
DB6
NC
IO
DATA BUS (USART)
97
DB7
NC
IO
DATA BUS (USART)
98
/R
/RDH
O
Read signal (to USART)
99
/W
/WRH
O
Write signal (to USART)
100
VCC
VCC
+5V
101
GND
GND
GND
102
RES
RES USART
O
Reset signal (to USART)
103
TRNCLK
GND
I
GND
104
RCVCLK
GND
I
GND
105
DBTST
VCC
ID
RS-232/INLINE USART chip
select
select
106
UTST
VCC
ID
+5V
107
/CSA
/CS1
IS
USART_A chip select
108
TRNDTA
TXD1
O
RS-232 transmission data
signal
signal
109
/DTRA
/DTR1
O
RS-232 data terminal ready
signal
signal
110
/RTSA
NC
O
NC
111
RCVDTA
RCVDT1
IS
RS-232 reception data sig-
nal
nal
112
/CTSA
GND
IS
GND
113
/DSRA
/DSR1
IS
RS-232 data set ready sig-
nal
nal
114 TRNRDYA
TRNRDY1
O
RS-232 data transmission
enable signal
enable signal
115 RCVRDYA
RCVRDY1
O
RS-232 data reception
enable signal
enable signal
116 TRNEMPA
TRNEMP1
O
RS-232 transmission buffer
empty signal
empty signal
117
SYCBKA
BRK1
IO
Break code detection signal
118
GND
GND GND
119
/CSB
/CS2
IS
USART_B chip select
120
TRNDTB
/CLSOUT
O
RS-232 transmission data
signal
signal
121
/DTRB
/CLCOM
O
RS-232 data terminal ready
signal
signal
122
/RTSB
NC
O
NC
123
RCVDTB
/CLSIN
IS
RS-232 reception data sig-
nal
nal
124
/CTSB
GND
IS
GND
125
/DSRB
GND
IS
RS-232 data set ready sig-
nal
nal
126 TRNRDYB
TRNRDY2
O
RS-232 data transmission
enable signal
enable signal
127 RCVRDYB
RCVRDY2
O
RS-232 data reception
enable signal
enable signal
128 TRNEMPB
TRNEMP2
O
RS-232 transmission buffer
empty signal
empty signal
129
SYCBKB
BRK2
IO
Break code detection signal
130
GND
GND
GND
131
/CSC
VCC
IS
USART_C chip select
Pin
NO.
Name
ER-A771
I/O
Description
ER-A771VS
CIRCUIT DESCRIPTION
7 – 12
2-4. TCP/IP Interface
1. GENERAL DESCRIPTION
The Ethernet control supports the TCP/IP protocol.
2. BLOCK DIAGRAM
*
When writing data into FLASH, switch /CS0to EP-ROM and /CS3 to
FLASH Memory.
FLASH Memory.
3. CONFIGURATION
1
1
1
1
CPU : [HitachiSH-2 Series SH7014 (20MHz)]
External memory spaces, CS0 - CS3 and the DRAM space are pro-
vided. This board assigns FLASH Memory to CS0, SRAM to CS1, dual-
port SRAM to CS2, and LAN controller to CS3.
vided. This board assigns FLASH Memory to CS0, SRAM to CS1, dual-
port SRAM to CS2, and LAN controller to CS3.
2
2
2
2
LAN Controller : [RealtekRTL8019AS (20MHz)]
The LAN controller is assigned to the CS space.
Because of the pseudo ISA connection, each register is assigned to
addresses of H00C00300 and after.
Because of the pseudo ISA connection, each register is assigned to
addresses of H00C00300 and after.
3
3
3
3
ROM (FLASH Memory) : [SharpLH28F004BVT(4Mbits)]
<Access Time = 90ns>
<Access Time = 90ns>
The ROM (FLASH Memory) is assigned to CS0 space.
Data is written onto FLASH Memory from UV-EPROM by switching the
CSO space to UV-EPROM and the CS3 space to FALSH Memory.
Data is written onto FLASH Memory from UV-EPROM by switching the
CSO space to UV-EPROM and the CS3 space to FALSH Memory.
The MAC Address is written on FLASH Memory.
• The company code is assigned to “08001FH”.
• The serial number and adjustment byte are stored in an area of 4
bytes from the address H’0007C000.
4
4
4
4
RAM : [S-RAM 1Mbits] <Access Time=70ns>
Assigned to the CS1 space.
[IDT Dual-Port SRAM IDT7134] <Access Time=55ns>
Assigned to the CS2 space.
The IDT7134 does not have any busy signal, access to the same
address from both sides is inhibited.
address from both sides is inhibited.
5
5
5
5
Pulse Trans : [Pulse78Z034]
Is used for the 10Base-T standard and has a choke coil built in at the
output side.
output side.
132
TRNDTC
NC
O
RS-232 transmission data
signal
signal
133
/DTRC
NC
O
RS-232 data terminal ready
signal
signal
134
/RTSC
NC
O
USART_C request to send
135
RCVDTC
GND
IS
RS-232 reception data sig-
nal
nal
136
/CTSC
GND
IS
GND
137
/DSRC
GND
IS
RS-232 data set ready sig-
nal
nal
138 TRNRDYC
NC
O
RS-232 data transmission
enable signal
enable signal
139 RCVRDYC
NC
O
RS-232 data reception
enable signal
enable signal
140 TRNEMPC
NC
O
RS-232 transmission buffer
empty signal
empty signal
141
SYCBKC
NC
IO
NC
142
VCC
VCC
+5V
143
GND
GND
GND
144
/CSD
VCC
IS
USART_D chip select
145
TRNDTD
NC
O
NC
146
/DTRD
NC
O
NC
147
/RTSD
NC
O
NC
148
RCVDTD
GND
IS
GND
149
/CTSD
GND
IS
GND
150
/DSRD
GND
IS
GND
151 TRNRDYD
NC
O
NC
152 RCVRDYD
NC
O
NC
153 TRNEMPD
NC
O
NC
154
SYCBKD
NC
IO
NC
155
/WIN
/WRH
I
Write signal
156
/RIN
/RDH
I
Read signal
157
RSLCT0
AH0
I
Address bus
158
RSLCT1
AH1
I
Address bus
159
RST
RES USART
IS
Reset signal
160
MCLK
CLK USART
I,
I
TTL input
ID
TTL input with pull down
IS
TTL Schmidt input
ISU
TTL Schmidt input with pull up
IO
TTL I/O
3S
3-state Buffer (6mA)
ON6
Open drain (6mA)
Pin
NO.
Name
ER-A771
I/O
Description
Dual-Port
RAM
4k byte
CN
RJ-45
Data Bus
Address Bus
Da
ta
ta
Bus
LOGIC
/CS1
/CS2
/INTHR
/INTHW
/INTSR
/INTSW
10MHz
/CS0
/CS0
/CS3
/CS3
/CS2
/CS1
/CS0
/HWACK
/HRACK
/SWRQ
/SRRQ
CPU
(SH-2)
/DPCS,
/WR,/RD
/WR,/RD
Address
Bus
LD0~LD7
LA0~LA11
FLASH
512k byte
LD0~LD7
LA0~LA18
LD0~LD7
LA0~LA18
SRAM
128k byte
LD0~LD7
LA0~LA19
LD0~LD7
LA0~LA18
LAN Cnt.
(8bit-Bus)
EP-ROM
(Writing in
to FLASH)
512k byte
ER-A771VS
CIRCUIT DESCRIPTION
7 – 13
4. MAIN LSI DESCRIPTION
1) CPU (SH7014)
1)-1. SH7014 Overview
The SH7014 CMOS single-chip microprocessors integrate a Hitachi-
original architecture, with a high-speed CPU with peripheral functions
required for the system configuration.
The CPU has a RISC-type instruction set. Most instructions can be exe-
cuted in one clock cycle, which greatly improves instruction execution
speed. In addition, the 32-bit internal-bus architecture enhances data
speed. In addition, the 32-bit internal-bus architecture enhances data
processing power. With this CPU, it has become possible to assemble
low cost, high performance/high-functioning systems, even for applica-
tions that were previously impossible with microprocessors, such as
tions that were previously impossible with microprocessors, such as
real-time control, which demands high speeds. In particular, the
SH7040 series has a 1-kbyte on-chip cache, which allows an improve-
ment in CPU performance during external memory access.
ment in CPU performance during external memory access.
In addition, this LSI includes on-chip peripheral functions necessary for
system configuration, such as large-capacity ROM (except the SH7014,
system configuration, such as large-capacity ROM (except the SH7014,
which is ROMless) and RAM, timers, a serial communication interface
(SCI), an A/D converter, an interrupt controller, and I/O ports. Memory
or peripheral LSIs can be connected efficiently with an external memory
or peripheral LSIs can be connected efficiently with an external memory
access support function.
This greatly reduces system cost.
1)-1-1. SH7014 Features
CPU:
• Original Hitachi architecture
• 32-bit internal data bus
• General-register machine
– Sixteen 32-bit general registers
– Three 32-bit control registers
– Four 32-bit system registers
• RISC-type instruction set
– Instruction length: 16-bit fixed length for improved code efficiency
– Load-store architecture (basic operations are executed between
registers)
– Delayed branch instructions reduce pipeline disruption during
branch
– Instruction set based on C language
• Instruction execution time: one instruction/cycle (35 ns/instruction at
28.7-MHz operation)
• Address space: Architecture supports 4 Gbytes
• On-chip multiplier: multiplication operations (32 bits x 32 bits
3
64
bits) and multiplication/accumulation operations (32 bits x 32 bits + 64
bits
3
64 bits) executed in two to four cycles
• Five-stage pipeline
Cache Memory:
• 1-kbyte instruction cache
• Caching of instruction codes and PC relative read data
• 4-byte line length (1 longword: 2 instruction lengths)
• 256 entry cache tags
• Direct map method
• On-chip RAM, and on-chip I/O areas (not related to objects of cache)
• Used in common with the on-chip RAM; 2 kbytes of on-chip RAM
used as address array/data array when cache is enabled
Interrupt Controller (INTC):
• Seven external interrupt pins (NMI, IRQ x 6)
• Twenty-eight internal interrupt sources
• Sixteen programmable priority levels
Bus State Controller (BSC):
• Supports external extended memory access
– 8-bit, or 16-bit external data bus
• Memory address space divided into five areas (four areas of SRAM
space, one area of DRAM space) with the following settable features:
– Number of wait cycles
– Outputs chip-select signals for each area
– During DRAM space access:
• Outputs RAS and CAS signals for DRAM
• Can generate a RAS precharge time assurance Tp cycle
• DRAM burst access function
– Supports high-speed access mode for DRAM
• DRAM refresh function
– Programmable refresh interval
– Supports CAS-before-RAS refresh and self-refresh modes
• Wait cycles can be inserted using an external WAIT signal
• Address data multiplex I/O devices can be accessed
Note: No bus release
Direct Memory Access Controller (DMAC) (2 Channels):
• Supports cycle-steal and burst transfers
• Supports single address mode and dual address mode transfers
• Priority order: fixed at channel 0 > channel 1
• Transfer counter: 16 bits
• Transfer request sources: external DREQ input, auto-request, and
on-chip supporting modules
• Address space: 4 Gbytes
• Choice of 8-, 16-, or 32-bit transfer data size
Multifunction Timer/Pulse Unit (MTU) (3 Channels):
• Maximum 8 types of waveform output or maximum 16 types of pulse
I/O processing possible based on 16-bit timer, 3 channels
• 8 dual-use output compare/input capture registers
• 8 independent comparators
• 8 types of counter input clock
• Input capture function
• Pulse output mode
– One shot, toggle, PWM
• Phase calculation mode
– 2-phase encoder calculation processing
Compare Match Timer (CMT) (Two Channels):
• 16-bit free-running counter
• One compare register
• Generates an interrupt request upon compare match
ER-A771VS
CIRCUIT DESCRIPTION
7 – 14
Watchdog Timer (WDT) (One Channel):
• Watchdog timer or interval timer
• A count overflow can generate an internal reset, external signal, or
interrupt
Serial Communication Interface (SCI) (Two Channels):
(Per Channel):
(Per Channel):
• Asynchronous or clock-synchronous mode is selectable
• Can transmit and receive simultaneously (full duplex)
• On-chip dedicated baud rate generator
• Multiprocessor communication function
I/O Ports:
• SH7014
– Input/output: 35
– Input: 8
– Total: 43
A/D Converter:
• 10 bits 8 channels
• The SH7014 has a high-speed A/D converter.
On-Chip Memory:
• ROM
– SH7014: ROMless
• RAM: SH7014: 3 kbytes (1 kbyte when cache is used)
Operating Modes:
• Operating modes
– Non-extended ROM mode
• Processing states
– Program execution state
– Exception processing state
• Power-down modes
– Sleep mode
– Software standby mode
Clock Pulse Generator (CPG):
• On-chip clock pulse generator
– On-chip clock-doubling PLL circuit
1)-2. Block Diagram
Figure 1. is a block diagram of the SH7014.
Figure 1. Block Diagram of the SH7014
1)-3. Pin Arrangement and Pin Functions
1)-3-1. Pin Arrangment
Figure 2. shows the pin arrangement for the SH7014 (top view).
Figure 2. SH7014 Pin Arrangement (QFP-112 Top View)
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MD3
MD2
MD1
MD0
MD2
MD1
MD0
NMI
EXTAL
XTAL
V
CC
V
CC
V
CC
PLLVCC
PLLCAP
PLLVSS
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
AV
CC
AV
SS
RES
WDTOVR
PB9/IR
Q7/
A
2
1
PB8/IR
Q6/
A
2
0/WAIT
PB7/A19
PB6/A18
PB5/IR
Q3/
RDWR
PB4/IR
Q2/
C
ASH
PB3/IR
Q1/
C
ASL
PB2/IR
Q0/
R
AS
A17
A16
PA15/CK
RD
WRH
WRL
CS1
CS0
PA9/TCLKD/I
RQ3
PA8/TCLKC/I
RQ2
PA7/TCLKB/CS3
PA6/TCLKA/CS2
PA5/SCK1/D
REQ1/IR
Q1
PA4/TX
D
1
PA3/RXD1
PA2/SCK0/D
REQ0/IR
Q0
PA1/TX
D
0
PA0/RXD0
PE15/DAC
K1
PE14/DAC
K0/AH
PE13
PE12
PE11
PE10
PE9
PE8
PE7/TIOC
2
B
PE6/TIOC
2
A
PE5/TIOC
1
B
PE4/TIOC
1
A
PE3/TIOC
0
D/D
R
AK1
PE2/TIOC
0
C/D
R
EQ1
PE1/TIO
C0B/DRAK
0
PE0/TIO
C0A/DREQ
0
: Peripheral address bus
: Peripheral data bus
: Internal address bus
: Internal upper data bus
: Internal lower data bus
PLL
PF7/AN7
PF6/AN6
PF5/AN5
PF4/AN4
PF3/AN3
PF2/AN2
PF1/AN1
PF0/AN0
RAM (3 kB)/
cache (1 kB)
CPU
Direct memory
access controller
Interrupt
controller
Bus state controller
Serial communi-
cation interface
(• 2 channels)
Multifunction timer/
pulse unit
Compare match
timer (• 2 channels)
A/D
converter
Watch-
dog
timer
V
SS
V
SS
V
SS
PB13
PE12
PE11
V
SS
PE10
PE9
PE8
PE7/TIOC2B
PE6/TIOC2A
V
CC
PE5/TIOC1B
V
SS
AV
CC
PF7/AN7
PF6/AN6
AV
SS
PF5/AN5
PF4/AN4
PF3/AN3
PF2/AN2
PF1/AN1
PF0/AN0
V
SS
PE4/TIOC1A
PE3/TIOC0D/DRAK1
PE2/TIOC0C/DREQ1
PE1/TIOC0B/DRAK0
PE0/TIOC0A/DREQ0
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
PB6/A18
PB7/A19
PB8/IRQ6/A20/WAIT
PB9/IRQ7/A21
V
SS
RD
WDTOVF
WRH
VCC
WRL
V
SS
CS0
PA9/TCLKD/IRQ3
PA7/TCLKB/CS3
PA6/TCLKA/CS2
PA5/SCK1/DREQ1/IRQ1
PA4/TXD1
PA3/RXD1
PA2/SCK0/DREQ0/IRQ0
PA1/TXD0
PA0/RXD0
D15
D14
D13
V
SS
D12
RES
PA
15/
C
K
PLLV
SS
PLLCA
P
PLLV
CC
MD0
MD1
V
CC
NMI
MD2
EX
TA
L
MD3
XT
AL
V
SS
D0
D1
D2
D3
D4
V
CC
D5
D6
D7
V
SS
D8
D9
D10
D11
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
CS1
PA8/TCLKC/IRQ2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PE
14/
DA
CK0/
A
H
PE
15/
DA
CK1
V
SS
A0
A1
A2
A3
A4
A5
A6
A7
A11
A12
A13
A14
A15
A16
V
CC
A17
P
B
2/
IRQ0/
R
AS
P
B
3/
IRQ1/
C
AS
L
P
B
4/
IRQ2/
C
AS
H
V
SS
PB
5/
IRQ3/
RDWR
A8
A9
A10
V
SS
QFP-112
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