Sharp ER-A771 (serv.man3) Service Manual ▷ View online
ER-A771VS
CIRCUIT DESCRIPTION
7 – 27
10. WAIT CONTROL
The weight control function built in the MPCA8 is used to provide an interface with low-speed devices.
10-1. BLOCK DIAGRAM
The block diagram of the wait control function is shown.
Fig.10
In the figure, the decoder, wait enabling register, AND-OR sections are the same as those in the MPCA6 or 7, but other components are newly incor-
porated in the MPCA7.
EXWAITZ and WAITZ are external weight signals which are to be ORed inside the MPCA8 and output to the WAITZ. The EXWAITZ is a general-pur-
EXWAITZ and WAITZ are external weight signals which are to be ORed inside the MPCA8 and output to the WAITZ. The EXWAITZ is a general-pur-
pose wait request terminal, and WAITZ is the wait request signal from the VGA controller.
11. CKDC9
The ER-A771 on CKDC9 for the CKDC PWB and one CKDC9 for POLE
display (option) to carry out the following control operations.
display (option) to carry out the following control operations.
CKDC PWB CKDC9:
• Clock (second data readable)
• Buzzer
• System reset
• Key/Clerk switch
POLE CKDC9(UP-P16DP or UP-I16DP)
• Customer display tube
11-1. INTERFACE
CKDC9 is connected through the MPCA8.
12. OPTION RAM INTERFACE
12-1. INTERFACE
The expanded RAM connector terminals are shown in the table.
The 72 pin S.O. DIMM is used for the connector.
The 72 pin S.O. DIMM is used for the connector.
Extension RAM connector terminals
Selector
/AS
CLK WAIT RESET Counter
START
/RESET
/EXWAIT
/VWAIT
/LCDWAIT
/WAITZ
φ
WAIT
enable
For
RASP-
/RESET for 1,2,3WAIT
WAIT
enable
For
MISC
WAIT
Count
For
RASP
D
/Q
Selector
Selector
/RESET
/RESET
for
1WAIT
for
1WAIT
/RESET
WAIT
Count
For
MISC
WAIT
Count
For
RASPN
WAIT
Count
For
RASPN
D
/Q
D
/Q
WAIT
enable
For
VRAM
•
VGA
I/O
D
/Q
Terminal autoweight signal
TXD2(P87)
SCK2(P83)
SCK2(P83)
RXD2(P84)
TXDI
SCKI
SCKI
RXDI
H8/510
MPCA8
INT1
IRQ0
IRQ0
RES
STOP
(P57)
RESET
RESET
STH
HTS
SCK
SCK
CKDC9
KRQ
SHEN
SHEN
STOP
HTS2
SCK2
STH2
SCK2
STH2
HTS
SCK
STH
SCK
STH
SRES
RESET
SW
FTI2
CKDC9
HTS1
SCK1
STH1
SCK1
STH1
HTS
SCK
STH
SCK
STH
INT4
SHEN
RESET
reset from MAIN
VFDC
VFD
UP-P16DP/UP-I16DP
Key
Buzzer
Signal
Name
Pin
No.
Signal
Name
Pin
No.
Signal
Name
Pin
No.
Signal
Name
Pin
No.
GND
1
PCE21_E
19
A5
37
D3
55
GND
2
—
20
A4
38
D2
56
—
3
PSREF
21
A3
39
D1
57
—
4
PCE22_O
22
A2
40
D0
58
—
5
PCE21_O
23
A1
41
GND
59
—
6
GND
24
A0
42
NC
60
—
7
—
25
D15
43
OWR
61
—
8
—
26
D14
44
—
62
—
9
—
27
D13
45
—
63
—
10
—
28
D12
46
—
64
A14
11
A13
29
D11
47
—
65
A15
12
A12
30
D10
48
—
66
A16
13
A11
31
D9
49
HWR
67
A17
14
A10
32
D8
50
—
68
A18
15
A9
33
D7
51
VMEM
69
A19
16
A8
34
D6
52
VMEM
70
—
17
A7
35
D5
53
GND
71
PCE22_E
18
A6
36
D4
54
GND
72
ER-A771VS
CIRCUIT DESCRIPTION
7 – 28
13. RESET SEQUENCE
The reset sequence block diagram is shown below. Note that RESET
signal (system reset) and CKDCR signal (CKDC reset) are different
from each other.
Fig.14
13-1. POWER ON/OFF
The flow of signal processing at the time of the power supply turning
On/Off is as follows:
On/Off is as follows:
Table 19
<Power OFF>
Table 20
<Power ON>
The table below shows the timing chart.
Fig.15
13-2. MRS, SRV RESET
The ER-A771 does not have the mode switch. The procedure for reset-
ting MRS, SRV is different from that of conventional cash registers.
ting MRS, SRV is different from that of conventional cash registers.
in the ER-A771, MRS, SRV resetting is selected and executed by the
key which has bee depressed when the CKDC reset is released to start
the system.
(In the case of MRS, security is added by a key operation equivalent to
(In the case of MRS, security is added by a key operation equivalent to
a pass word.)
Flow chart
14. DRAWER
The ER-A771 can use up to 2 optional external drawers.
14-1. DRAWER SOLENOID DRIVE
P34 ~ P37 inside the CPU are allocated for the port output of the drawer
solenoid drive.
One port corresponds to one drawer. Theoretically, it is possible to drive
multiple drawers at the same time, but this processing must be inhibited
softwarewisely because of power supply capacity and driver hardware
softwarewisely because of power supply capacity and driver hardware
factors. If a power failure is detected, the drawer solenoid drive must be
stopped as soon as possible.
*
The drawer solenoid drive time must controlled in the range of 40 ms
to 50 ms by the timer.
to 50 ms by the timer.
Power supply
MPCA8
CPU
CKDC9
1
POFF
3
L
2
IRQ0
3
L
3
STOP
3
L
4
RESET
3
L
(System reset)
Power supply
MPCA8
CPU
CKDC9
1
POFF
3
H
2
RESET
3
H
(System reset)
POFF
CKDCR
(CKDC reset)
VCC
POFF
INT0
IRQ0
STOP
RESET
(System reset)
SLIDE
SW
SW
CKDC9
MPCA8
POWER
SUPPLY
SUPPLY
CPU
PG GOOD
RESET
STOP
SHEN
SCK
+5V,+12V
(POFF)
10ms MIN
8 PULSE
(System)
Power supply On
Power supply Off
Built-in port
Signal name
Remarks
P34
DR0
Drawer 1 (optional drawer)
P35
DR1
Drawer 2 (optional drawer)
P36
DR2
Reserved
P37
DR3
Reserved
Yes
No
*Slide Switch
operation
operation
MRS1 key
ON?
MRS2 key
ON?
CKDC start
SRV reset
MRS reset
Star
t
Normal
start?
condition read
Recovery
No
Yes
OK?
OK?
SRV reset
SRV reset
No
Yes
Yes
No
Yes
Yes
No
Hard reset
start?
PASSWORD
judgement
judgement
judgement
10-key position
input sequence
input sequence
MRS reset
PASSWORD
ER-A771VS
CIRCUIT DESCRIPTION
7 – 29
14-2. DRAWER OPEN/CLOSE SENSE
The drawer open/close sense signal is input into the built-in port of the
CPU. the sense signal of an optional drawer sensor is also wired ORed
before inputting.
before inputting.
• P33=1: Any of the drawers is open.
15. TCP/IP
PENDING
16. RS232
The standard RS232 is fixed to the logic channels 1 and 8. Use the
channels 3, 4, 5 and 6 for the ER-A7RS2.
channels 3, 4, 5 and 6 for the ER-A7RS2.
17. MCR
This paragraph describes MCR option (UP-E12MR) control defined by
ER-A771 hardware architecture.
2 channels of the serial port (interchangeable with 8251) built in the
MPCA8 are used. 2 tracks of data are read simultaneously. Supports
MPCA8 are used. 2 tracks of data are read simultaneously. Supports
the first and second tracks MCR of ISO. (UP-E12MR)
17-1. CPU INTERFACE
The CPU interface for the USART (8251) and magnet card reader
(MCM-21) in the ER-A771 system is shown below.
Signal description
2 chip select signals for 8251 are generated inside MPCA8.
17-2. MCR INTERFACE
The operating timing of the MCR interface signals is given below.
(1) Example of timing
(2) Detailed timing (relation between DATA and CLOCK PULSE)
The “NULL” CODE is basically written prior to the opening code. The
opening code detection algorithm is considered because data may
become corrupt before and after the CARD detection signal due to a
worn magnet stripe.
worn magnet stripe.
RCP1
TRACK 1 CLOCK PULSE
RDD1
TRACK 1 DATA SIGNAL
RCP2
TRACK 2 CLOCK PULSE
RDD2
TRACK 2 DATA SIGNAL
CLS1
TRACK 1 CARD DETECTION SIGNAL
CLS2
TRACK 2 CARD DETECTION SIGNAL
RCVRDY1
TRACK 1 DATA RECEIVING SIGNAL
RCVRDY2
TRACK 2 DATA RECEIVING SIGNAL
INTMCR
INTERRUPT SIGNAL OR-SYNTHESIZED from
RCVRDY and SYNC input
RCVRDY and SYNC input
CPU
ICI
INTMCR
RCVRDY1
RCVCLK2
RDD1
RCP2
RDD2
CLS1
RCVDT1
RCP1
/DSR1
CLS2
RCVDT2
8251 x 2
Integrated as MPCA8
in the ER-A770 system.
in the ER-A770 system.
RCVCLK1
/DSR2
RCVRDY2
CLS1,
CLS2
RCVRDY1
RCVRDY2
INTMCR
SYNC
MPCA7
RCP1
CLS2
RDD1/RDD2
RCP1/RCP2
CLS1/CLS2
"0" "1" "1"
Approx. 16µ s
Min. 5 µ s
RDD1/RDD2
RCP1/RCP2
ER-A771VS
CIRCUIT DIAGRAM
8 – 1
IC2 VCC-
--GND
IC2 14PIN
--- VCC
7PIN --
- GND
CKDC CN
LCD CN
INVERTO
R CN
HARDWARE
RESET
(RUN)
IC1 7PIN --- GND
14PIN --- VCKDC
+20V
/RESA
RESA
SCK2A
/HTS2A
/STH2A
SHEN2A
/RESA
RESA
SCK2A
/HTS2A
VCKDC
A3
+20V
A2
/HWR
D11
A0
A22
A19
A23
D13
D10
A17
A11
A5
A8
D14
A12
A10
D12
A9
A14
A2
D9
A6
A1
A3
A4
A13
D8
A20
A16
A21
A15
A7
A18
D15
VCKDC
DL1A
VEE
CP1
DL2A
C
FP
DCLK
CP2
DL3A
LP
VCKDC
+20V
/POFF
VEE
/STH2A
SHEN2A
DL2
DL0A
DL3
DL0
DL1
VSS
DISP
VSS
WF
A14
A17
A15
A16
A19
A18
A12
A11
A13
A9
A7
A8
A10
A6
A5
A1
A4
A3
A2
A0
D13
D14
D15
D11
D12
D10
D9
D6
D5
D7
D8
D3
D2
D4
D1
D0
/HWR
VCKDC
/RD
/RDO
11,12
/WRO
11,12
A[0..23]
3,4,7,8,9,11,12,16
/EXWAIT
11
/BREQ
4
/BACK
4
/TRQ2
11,12
/TRQ1
11,12
/RFSH
4,9
/RES
3,7,9,11,12
/AS
4,9,11
/OPTCS
11,12
/RD
3,4,7,8,9,11,16
VCKDC
16
/IRQ1
4,12
/IPLON0
3,4,9,11
D[8..15]
3,4,8,9,11,12,16
BANK
4
/RESET
4,11,16
RES
9
/SCK2
11
HTS2
11
/RES
3,7,9,11,12
/POFF
11,12,13
/RESET
4,11,16
LP
9
DCLK
9
VEE
9
DISP
9
FP
9
/SHEN1
4
/KRQ
11
/STOP
4
STH1
11
/SCK1
11
HTS1
11
BKLT
9
/CLRES
4
/CLCOM
12
/CLSOUT
12
/CLSIN
12
+20V
2,9,13
/SHEN2
11
STH2
11
DL[0..3]
9
/OWR
9,16
D[0..15]
3,4,8,9,11,12,16
A[0..19]
3,4,7,8,9,11,12,16
/PCE22E
16
/PCE21E
16
/PCE22O
16
/PCE21O
16
/HWR
3,4,7,8,9,11,16
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
CN1
53015-1010
OPTION DISP CN
1
2
3
4
5
6
7
8
9
10
FB1
CIM31J601NE
R13
1/2W 13
FB6
+
C11
56uF/10V
+
C1
56uF/10V
FB12
CIM31J601NE
IC2E
74LV14A
11
10
C3
0.1uF
D1
RB160L-40
AK
IC2F
13
12
VR2
5K
1
3
2
GND
+5V
+5V
GND
GND
VRAM
GND
GND
VRAM
FROMBY-
FROMWP-
FROMRP-
FROS2-
FROS1-
MROS-
PSREF-
GND
A14
A15
A16
A17
A18
A19
A20
A21
A22
NU
NU
NU
NU
NU
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NU
NU
NU
NU
NU
OWR-
NU
HWR-
REST
PCE2_O-
PCE2_E-
CN3A
MM20-72
B
RAM CN
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1
17
FB9
CIM31J601NE
R8
4.7K
C12
0.1uF
CN6
CON15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FB4
IC1B
74HC00
4
5
6
VR1
5K
13
2
R2
10K
R1
4.7K
R221
10K
IC2A
74LV14A
1
2
FB13
CIM31J601NE
BTCN1
5267-02
BAT CN
2
1
2
1
R4
1K
R7
10K
IC2B
3
4
+
C8
3.3uF/50V
+
C10
3.3uF/50V
IC2C
5
6
S1
RIGHT ANGLE SL-SW
12
FB8
CIM31J601NE
IC2D
9
8
R10
1/5W 220
R14
1.2K
C4
1000pF
FB3
CIM31J601NE
X 4
R11
10K
FB10
CIM31J601NE
CN7
CON4
1
2
3
4
R6
4.7K
FB7
CIM31J601NE
R3
10K
IC1A
74HC00
1
2
3
FB2
CIM31J601NE
C2
470pF
C6
1000pF
FB14
CIM31J601NE
CN4
CON18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
+
C9
10uF/16V
C7
0.1uF
R9
10K
F4A1
T500mA/250V
CN2A
MOTHER CN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
R222
4.7K
CN2B
10 5061 080 053
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
R12
15K
R15
1/2W 13
FB5
FB11
CIM31J601NE
C5
1000pF
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
1/16
MAIN PWB
CONNECT
OR
CHA
PT
ER
8. CIRC
UIT DIA
G
R
A
M
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