Panasonic KX-NCV200BX / KX-TVM204X / KX-TVM296X (serv.man3) Service Manual ▷ View online
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KX-NCV200BX / KX-TVM204X / KX-TVM296X
4.3.1.
LAN
The LAN consists of the SMSC's 91C113 Ethernet driver IC and a SpeedTech P52-P14-31A9 connector with a built-in transformer.
This IC driver provides 10/100base-T Ethernet integrating MAC and PHY in one chip.
This IC driver provides 10/100base-T Ethernet integrating MAC and PHY in one chip.
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KX-NCV200BX / KX-TVM204X / KX-TVM296X
Network Interface
Fully integrated IEEE 802.3/802.3u-100Base-TX/10Base-T Physical Layer
Auto Negotiation: 10/100,Full / Half Duplex
Auto Negotiation: 10/100,Full / Half Duplex
LAN Interface Connector
4.3.2.
USB
The USB employs the Mitsubishi M66591. In accordance with the USB (Universal Serial Bus) standard Rev 2.0, the M66591 is a
USB peripheral controller that supports both Hi-speed and Full-speed transfer modes. The M66591 has a built-in Hi-Speed/Full-
Speed transceiver, supporting control, bulk and interrupt transfers as defined by USB standards. 3.5Kbyte-FIFO is built in for data
transfer which offers up to seven endpoints.
USB peripheral controller that supports both Hi-speed and Full-speed transfer modes. The M66591 has a built-in Hi-Speed/Full-
Speed transceiver, supporting control, bulk and interrupt transfers as defined by USB standards. 3.5Kbyte-FIFO is built in for data
transfer which offers up to seven endpoints.
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KX-NCV200BX / KX-TVM204X / KX-TVM296X
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KX-NCV200BX / KX-TVM204X / KX-TVM296X
4.3.3.
Local Bus Gate
Synchronous and asynchronous buses coexist on the main board of this system. Because a synchronous bus is affected by the sig-
nal line load capacitance and load capacitance due to the pattern of the host, in this system the synchronous bus connects directly
with the CPU acting as the primary bus, and in order to minimize the load capacitance, the board is designed taking pattern and run
lengths into consideration. Other peripheral devices connected to the asynchronous bus are separated by the gate IC, and a gate
control circuit was added to the board to open the bus as needed.
nal line load capacitance and load capacitance due to the pattern of the host, in this system the synchronous bus connects directly
with the CPU acting as the primary bus, and in order to minimize the load capacitance, the board is designed taking pattern and run
lengths into consideration. Other peripheral devices connected to the asynchronous bus are separated by the gate IC, and a gate
control circuit was added to the board to open the bus as needed.
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