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The ROM is 8Mbit NOR Flash ROM x 1. The system implements a bootstrap program in ROM whereby programs necessary for
system operation are loaded into ROM from the HDD on startup.

The SDRAM used is 32Mbyte (4M x 16bit, 4 banks) synchronous DRAM x 1. The SDRAM acts as the work memory of the CPU.
The SDRAM is controlled by the CPU memory controller. The CPU/SDRAM bus is synchronous and operates at a bus speed of
65.536MHz.

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The system uses an ASIC called iVDC (Intelligent Voice & Peripheral Device Controller), which comprises the voice processing
engine of the PCC voice mail system, run in combination with an SH microprocessor and TI DSPs. This ASIC allows the send-
ing and receiving of 24 channels of audio serial data with 12 DSPs and enables data exchange with the HDD through buffer
memory. Necessary logic is imbedded to control other peripheral devices, HDLC, and VM-Link interfaces.

Module Name

Function

Serial Communication Clock Module

Generates bus timing of three types of McBSP0 based interfaces (DPT, APT, VM-Link).
Generates bus timing of McBSP1 based interfaces.

VM-Link Interface Module

PBX interface function and bridge function with McBSP0.

VM-Link Interface Module

Communicates with DSP through McBSP1. Sends and receives the compressed voice data. Controls
voice data by the voice buffer interrupt.

HDLC Module

HDLC  function  consisting  of serial packet switching managing Bch and Dch HDLC and their host
points. 

SRAM Interface Module

Manages timing of SRAM for external connection voice buffer.

Host CPU Interface Module

Access  to  the  CPU control register group, voice buffer access, external device access control,
addressing of external devices such as DSP, ECO, LAN, and USB.

Cch Interrupt Control Module

Cch interrupt function during DPT.

DSP Control Module

Manages and controls DSP interrupt.

Terminal Name

Number of Terminals

System Terminal

2

SH-CPU Interface Terminal (Access Control Terminal)

47

SH-CPU Interface Terminal (Interrupt Terminal)

4

External Device Control Terminal (General-purpose Port)

6

External Device Control Terminal (External Chip Select)

3

External Device Control Terminal (HDD Interface)

2

External Device Control Terminal (DSP)

30

External Device Control Terminal (DPT (ECO) )

16

SRAM Interface Terminal

39

McBSP0 Timing Control Terminal

13

McBSP1 Timing Control Terminal

14

VM-Link Interface Terminal

4

McBSP0 Data (VM-Link Bridge)

2

McBSP1 Data

2

HDLC External Connection Terminal

4

Cch Interrupt

2

Mode Terminal and User Test Terminal

3

JTAG Terminal

5

Development code name

iVDC

Wafer manufacturer

Fujitsu

ASIC specification

0.35 

µþm Embedded Cell Arrays

Number of pins

256

Power-supply voltage

+3.3V

Package

QFP

Operating frequency

65.536MHz for logics and PCM clocks

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System Terminal
N_PRST

input

"L"Act

Power-on reset signal. Asynchronous input for system reset.

SYSCLK

input

posedge System clock. 65.536MHz

SH-CPU interface terminal (access control terminal)
N_IVDC_CS

input

"L"Act

Chip select signal (Area 4:iVDC)

N_CE1A

input

"L"Act

Chip select signal (Area 5 low-order byte)

N_CE2A

input

"L"Act

Chip select signal (Area 5 high-order byte)

N_CE1B

input

"L"Act

Chip select signal (Area 6 low-order byte)

N_RD

input

"L"Act

"Read strobe"

N_WE

input

"L"Act

Write strobe

RD_NWR

input

"L"Act

Read/write status

N_WAIT

output

"L"Act

Wait signal

LA22 - LA1

input

-

CPU address input

LD15 - LD0

inout

-

CPU data bus

SH-CPU interface terminal (interrupt terminal)
N_IVDC_INT

input

"L"Act

Interrupt signal (iVDC)

N_VB_INT

input

"L"Act

Interrupt signal (VB)

N_CDHDL_INT

input

"L"Act

Interrupt signal (DSP)

N_WE

input

"L"Act

Interrupt signal (Cch, HDLC)

External device control terminal (general-purpose port)
GPIO6 - GPIO1

input

-

General-purpose I/O port

External device control terminal (external chip select)
N_GCS1

output

"L"Act

General-purpose chip select (area where wait number setting is possible)

N_LAN_CS

output

"L"Act

External chip select (LAN)

N_USB_CS

output

"L"Act

External chip select (USB)

External device control terminal (HDD interface)
N_IDCS0

input

"L"Act

IDE0 chip select

N_IDCS1

input

"L"Act

IDE1 chip select

External device control terminal (DSP)
HBIL

output

-

Byte select signal

HCNTL1 - HCNTL0

output

-

Register select signal

N_DSP_DS12 - N_DSP_DS1

output

"L"Act

DSP chip select signal (12 devices)

DSP_RW

output

-

Chip select signal (Area 5 high-order byte)

N_DSP_GATE

output

"L"Act

Chip select signal (Area 6 low-order byte)

DSP_HRDY

input

"H"Act

"Read strobe"

N_DSP_HINT12 - 
N_DSP_HINT1

input

"L"Act

Write strobe

External device control terminal (DPT (ECO) )
N_ECO_CS12 - N_ECO_CS1

output

"L"Act

ECO chip select signal (12 devices)

N_ECO_RE

output

"L"Act

ECO read enable

N_ECO_WE

output

"L"Act

ECO write enable

N_ECO_GATE

output

"L"Act

ECO data bus enable signal

N_ECO_WAIT

input

"L"Act

ECO wait signal

SRAM interface terminal
N_MCS2 - N_MCS1

output

"L"Act

SRAM chip select signal

N_MWE

output

"L"Act

SRAM write enable signal

N_MOE

output

"L"Act

SRAM output (read) enable signal

MA18 - MA0

output

-

SRAM address bus

MD15 - MD0

In/out

-

SRAM data bus

McBSP0 timing control terminal
M02M

output

-

2.048MHz, McBSP0 transfer clock

M0FS12 - M0FS1

output

-

McBSP0 frame signal

McBSP1 timing control terminal
M18M

output

-

8.192MHz, McBSP1 transfer clock

M1FS12 - M1FS1

output

-

McBSP1 frame signal

LHWSEL

output

-

HW select signal

VM-Link interface terminal
SHW_CLK

inout

posedge VM-Link timing clock

SHW_FH

inout

-

VM-Link frame head pulse

SHW_UHW1

output

-

VM-Link upstream data

SHW_DHW1

input

-

VM-Link downstream data

McBSP0 data (VM-Link bridge)
LDHW_D

input

-

Voice data output to DSP

LUHW_D

output

-

Voice data input from DSP

McBSP1 data
M1DX

output

-

Output of compressed voice data to DSP