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17

M1DR

input

-

Input of compressed voice data from DSP

HDLC outside connection terminal
DPT_CLK

input

posedge DPT transfer clock

DPT_SYNC

input

-

DPT frame pulse

I_DPTHW

input

-

HDLC input data

O_DPTHW

output

-

HDLC output data

Cch interrupt
OEP0

input

Fall

Cch frame signal. Detects the falling edge.

OSX

input

"H"Act

Highway on which Cch data is carried.

Mode terminal and user test terminal
MODE1 - MODE0

input

-

Mode select signal. The state of this terminal can be read from the CPU
through the iVDC register.

TEST1

input

-

User test signal. Used when testing SIC chip. "L"=normal operation. "H"=
test mode.Test mode has the following actions.

• The input clock frequency is treated as 32MHz. Normally, 64MHz is input

to the SYSCLK terminal and clock inputs are provided by dividing by 2
for 32MHz internal clocks and 4 for 16MHz internal clocks. In test mode,
the SYSCLK input is passed directly at 32MHz. 
Input frequency is then divided by 2 for 16MHz clocks. 

• The reset of the test register is released. The test register is usually

reset so that values are not writable.

JTAG terminal
TRST

input

-

TEST Reset

TMS

input

-

TEST Mode Select

TCK

input

-

TEST Clock

TDI

input

-

TEST Data (IN)

TDO

output

-

TEST Data (OUT)

Additional power supply terminal
ADD_VDD_0001
ADD_VDD_0012

output

-

Additional VDD, 3.3V. Treated as output at the logic design level.

ADD_VSS_0001
ADD_VSS_0011

output

-

Additional GND, 0V. Treated as output at the logic design level

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20

The SRAM used is 8Mbit x 1. This system uses SRAM as the relay buffer for voice data between the DSPs and HDD. The voice
buffer has memory area for four seconds per channel on both A and B sides, giving a total of 24 channels x 4sec (A) x 4sec (B). The
ASIC (iVDC) controls the voice buffer through a bus independent from the system bus.