DOWNLOAD Sony XES-Z50 Service Manual ↓ Size: 15.88 MB | Pages: 127 in PDF or view online for FREE

– 65 –

Pin No.

Pin Name

I/O

Function

76

GFS

I

Guard frame sync signal input from the digital signal processor (IC501)    “L”: NG, “H”: OK

77

SENS

I

Count sense signal input from the digital signal processor (IC501)

78

—

O

79

—

O

Not used (open)

80

—

O

*1  Elevator up/down motor, disc load/save motor control

             

                 

Elevator up

Elevator down

Disc load

Disc save

MA (pin 8)

“L”

“H”

“L”

“H”

MB (pin 7)

“L”

“L”

“H”

“H”

MC (pin 6)

“H”

“H”

“L”

“L”

Terminal

Operation

  Disc load/save motor (M502)

  Elevator up/down motor (M501)

– 66 –

Pin No.

Pin Name

I/O

Function

1

NC

O

Not used (open)

2

NC

O

Not used (open)

3

NC

I

Not used (fixed at “L”)

4

REQ

O

Request signal output to the system controller (IC301)

5

CCLK

I

Serial data transfer clock signal input from the system controller (IC301)

6

CSI

I

Serial data input from the system controller (IC301)

7

CSO

O

Serial data output to the system controller (IC301)

8

SCLK

O

Clock signal output for subcode data reading to the digital signal processor (IC501)

9

SSI

I

Subcode data input from the digital signal processor (IC501)

10

NC

O

Not used (open)

11

ADD0

O

12

ADD1

O

13

ADD2

O

14

ADD3

O

15

ADD4

O

16

ADD5

O

17

ADD6

O

18

ADD7

O

19

RAMSEL

I

Not used (open)

20

DATA0

I/O

21

DATA1

I/O

22

DATA2

I/O

23

DATA3

I/O

24

DATA4

I/O

25

DATA5

I/O

26

DATA6

I/O

27

DATA7

I/O

28

RST

I

System reset signal input from the system controller (IC301), reset signal generator (IC903),
and bus interface (IC951) (for SONY bus)    “L”: reset    For several hundreds msec. after the
power supply rises, “L” is input, then it changes to “H”

29

EXTAL

I

System clock input terminal (10 MHz)

30

XTAL

O

System clock output terminal (10 MHz)

31

VSS

—

Ground terminal

32 to 55

NC

O

Not used (open)

56

BUSY

O

Busy signal output to the system controller (IC301)

57 to 59

NC

O

Not used (open)

60

ADD16

O

Address signal output to the S-RAM (IC304)

61

NC

O

Not used (open)

62

CE

O

Chip enable signal output to the S-RAM (IC304)

63

WE

O

Write enable signal output to the S-RAM (IC304)

64

ADD8

O

65

ADD9

O

66

ADD10

O

67

ADD11

O

68

ADD12

O

69

ADD13

O

Address signal output to the S-RAM (IC304)

Two-way data bus with the S-RAM (IC304)

Address signal output to the S-RAM (IC304)

– 67 –

Pin No.

Pin Name

I/O

Function

70

VDD

—

Power supply terminal (+5V)

71

NC

O

Not used (open)

72

NC

I

Not used (fixed at “L”)

73

NC

I

Not used (fixed at “H”)

74

ADD14

O

Address signal output to the S-RAM (IC304)

75

ADD15

O

Address signal output to the S-RAM (IC304)

76

SCOR

I

Subcode sync (S0+S1) detection signal input from the digital signal processor (IC501)

77

WFCK

I

Write frame clock (7.35 kHz) signal input from the digital signal processor (IC501)

78

BUCK

I

Backup power supply detection signal input terminal (used also to reset standby)

79

NC

I

Not used (fixed at “L”)

80

NC

I

Not used (fixed at “L”)

– 68 –

Pin No.

Pin Name

I/O

Function

1

VSS

—

Ground terminal

2

CRDY

O

Output of ready signal at serial data transfer to the master controller (IC301)
The start cause interruption occurs by a falling edge

3

CCNT

I

Input of control/data from address bus for the master controller (IC301)    “L”: data input

4

XCWR

I

Strobe signal input for data writing from the master controller (IC301)
Data are written by a falling edge

5

XCRD

I

Strobe signal input for data reading from the master controller (IC301)    “L”: data read

6

VDD

—

Power supply terminal (+3.3V)

7

CD0

I/O

Two-way data bus (LSB) with the master controller (IC301)

8

CD1

I/O

9

CD2

I/O

Two-way data bus with the master controller (IC301)

10

CD3

I/O

11

VSS

—

Ground terminal

12

CD4

I/O

13

CD5

I/O

Two-way data bus with the master controller (IC301)

14

CD6

I/O

15

CD7

I/O

Two-way data bus (MSB) with the master controller (IC301)

16

VDD

—

Power supply terminal (+3.3V)

17

MUTE

I

Mute control signal input of the audio data    “L”: mute    Not used (fixed at “H”)

18

CCS

I

Input of chip select signal from address bus for the master controller (IC301)

19

VSS

—

Ground terminal

20

MCKO

O

Master clock signal (18.432 MHz) output terminal    Not used (open)

21

VSS

—

Ground terminal

22

XTO

O

System clock signal (33.8688 MHz) output terminal    Not used (open)

23

XTI

I

System clock signal (33.8688 MHz) input terminal

24

VSS

—

Ground terminal

25

(BIST)

O

Output terminal for the test    Not used (open)

26

(TCK)

O

Output terminal for the test    Not used (open)

27

(TDI)

O

Output terminal for the test    Not used (open)

28

(TENA1)

O

Output terminal for the test    Not used (open)

29

(TDO)

O

Output terminal for the test    Not used (open)

30

(VST)

I

Input terminal for the test    Not used (fixed at “L”)

31

VSS

—

Ground terminal

32

RESET

I

Reset signal input from the master controller (IC301)    “L”: reset

33

BCLK

O

Block clock signal output terminal    Not used (open)

34

LRCK

I

L/R sampling clock signal (44.1 kHz) input of the serial in/out data

35

BCK

I

Bit clock signal (2.8224 MHz) input of the serial in/out data

36

VSS

—

Ground terminal

37

SIA

I

38

SIB

I

Serial audio data input terminal
IC101: Serial data (for front speaker) input from the CXD2710R (IC601)
IC201: Serial data (for sub-woofer speaker) input from the CXD2710R (IC601)

Serial audio data input terminal
IC101: Serial data (for rear speaker) input from the CXD2710R (IC601)
IC201: Not used (fixed at “L”)