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– 57 –

Pin No.

Pin Name

I/O

Function

1

VDD

—

Power supply terminal (+5V)

2

SIRCS

I

Sircs signal input from the remote control receiver in display unit

3

SIRCS

I

Sircs signal input from the remote control receiver in display unit

4

DSPL-RST

O

Reset signal output to the display controller (IC901)    “L”: reset
At the power supply, “L” is output to reset the display controller

5

DSPL-ON

O

Output of power on/off control signal for the display circuit power supply    “H”: power on
Besides power on/off control, the display data and reset signal transmission to the display
controller (IC901) is controlled at the output of “H”

6

TX-SEL

O

Not used (open)

7

NCO

O

Not used (open)

8

CS-CTL

O

Not used (open)

9

DOWN LOAD

I

“H” is input when external flash memory data are rewritten    Normally “L”

10

NIH

I

Reset signal output to the external RAM device    Not used (fixed at “H”)

11

VSS

—

Ground terminal

12

LCD-TX

O

Transmit data output to the display controller (IC901)

13

UNISO

O

Serial data output to the bus interface (IC503) (for SONY bus)

14

LCD-RX

I

Receive data input from the display controller (IC901)

15

UNISI

I

Serial data input from the bus interface (IC503) (for SONY bus)

16

NCO

O

Not used (open)

17

UNICKI

I

Serial data transfer clock signal input from the system controller (IC501)

18

D0

I/O

19

D1

I/O

20

D2

I/O

21

D3

I/O

22

VSS

—

Ground terminal

23

D4

I/O

24

D5

I/O

25

D6

I/O

26

D7

I/O

27

D8

I/O

28

D9

I/O

29

D10

I/O

30

D11

I/O

31

D12

I/O

32

D13

I/O

33

D14

I/O

34

D15

I/O

35

VDD

—

Power supply terminal (+5V)

36

A0

O

Address signal output terminal    Not used

37

A1

O

38

A2

O

39

A3

O

40

A4

O

Address signal output to the flash memory (IC804) and S-RAM (IC805)

41

A5

O

42

A6

O

43

A7

O

Two-way data bus with the flash memory (IC804) and S-RAM (IC805)

Two-way data bus with the flash memory (IC804) and S-RAM (IC805)

– 58 –

Pin No.

Pin Name

I/O

Function

44

VSS

—

Ground terminal

45

A8

O

46

A9

O

47

A10

O

48

A11

O

49

A12

O

50

A13

O

51

A14

O

52

A15

O

53

A16

O

54

A17

O

Address signal output to the flash memory (IC804)

55

A18

O

Address signal output to the flash memory (IC804)

56

A19

O

Address signal output terminal    This set uses the OR level with chip select signal of ROM-CS
(pin (¡) as a chip enable signal for the flash memory (IC804)

57

VSS

—

Ground terminal

58

WAIT

I

Wait signal input terminal (fixed at “H”)

59

BREQ

O

Communication request signal output terminal    Not used (open)

60

BACK

O

Acknowledge output terminal    Not used (open)

61

ø

O

System clock output terminal    Not used (open)

62

STBY

I

Hardware standby signal input terminal (fixed at “H”)

63

SYSRES

I

System reset signal input from the system controller (IC501) and reset signal generator (IC504)
“L”: reset    For several hundreds msec. after the power supply rises, “L” is input, then it
changes to “H”

64

BU-IN

I

Backup power supply detection signal input from the bus interface (IC503) (for SONY bus)

65

VSS

—

Ground terminal

66

EXTAL

I

System clock input terminal (14.745 MHz)

67

XTAL

I

System clock input terminal (14.745 MHz)

68

VDD

—

Power supply terminal (+5V)

69

AS

O

Address strobe signal output terminal    Not used (open)

70

RD

O

Strobe signal output for data reading to the flash memory (IC804) and S-RAM (IC805)

71

HWR

O

Strobe signal output for data writing to the flash memory (IC804) and upper byte data writing
strobe signal output to the S-RAM (IC805)

72

LWR

O

Strobe signal output for data writing to the flash memory (IC804) and lower byte data writing
strobe signal output to the S-RAM (IC805)

73

MD0

I

Input terminal for setting microcomputer operation mode (fixed at “L”)

74

MD1

I

Input terminal for setting microcomputer operation mode (fixed at “L”)

75

MD2

I

Input terminal for setting microcomputer operation mode (fixed at “H”)

76

AVDD

—

Power supply terminal (+5V) (for A/D conversion)

77

AVREF

I

Reference voltage input terminal (+5V) (for A/D conversion)

78

AN0

I

79

AN1

I

80

AN2

I

Input terminal for the test (fixed at “L”)

81

AN3

I

82

AN4

I

83

AN5

I

Input terminal for the test (fixed at “L”)

84

BU-IN

I

Backup power supply detection signal input from the bus interface (IC503) (for SONY bus)

85

PBS

I

Parking brake detection signal input terminal    Not used (fixed at “L”)

Address signal output to the flash memory (IC804) and S-RAM (IC805)

– 59 –

Pin No.

Pin Name

I/O

Function

86

AVSS

—

Ground terminal (for A/D conversion)

87

BUS ON

I

Bus on/off detection interrupt signal input from the system controller (IC501)    “L”: bus on

88

SRAM-CS

O

Chip enable signal output to the S-RAM (IC805)

89

DEC-CS

O

Chip enable signal output terminal    Not used

90

DEC-INT

I

Interrupt signal input terminal    Demodulation data are read by detecting a falling edge
Not used

91

ROM-CS

O

Chip enable signal output to the flash memory (IC804)

92

VSS

—

Ground terminal

93

LCD-BLON

O

Output of power on/off control signal for the back light in display unit    “H”: power on

94

LINK-OFF

O

Bus on/off control signal output to the bus interface (IC503) (for SONY bus)    “L”: bus on

95

DEC-ON

O

Output of power on/off control signal for the external device
“H”: power on    Not used (open)

96

DEC-CLR

O

Reset signal output terminal    “L”: reset

97

A23

O

Address signal output terminal    Not used (open)

98

A22

O

Address signal output terminal    Not used (open)

99

X.TEST

I

100

A20

O

Address signal output terminal    Not used (open)

Input of personal computer connection detection
“H”: When display panel is attached at front panel position
“L”: When personal computer communication accessory is attached

– 60 –

Pin No.

Pin Name

I/O

Function

1

VCC

—

Power supply terminal (+5V)

2

TIR

O

LED drive signal output for the TIR indicator    “H”: LED on    Not used

3

NCO

O

4

NCO

O

5

NCO

O

Not used (open)

6

NCO

O

7

NCO

O

8

LCD-START

O

9

LCD-BUSY

I

Input of busy signal from the LCD controller for liquid crystal module

At the timing of  “H”

®“L”, data transmission to LCD controller for liquid crystal module starts

10

RESO

O

Reset signal output to the external device    Not used (pull-up)

11

VSS

—

Ground terminal

12

TX-LCD

O

Transmit data output to the FM character multiple broadcast display controller (IC802)

13

NCO

O

Not used (open)

14

RX-LCD

I

Receive data input from the FM character multiple broadcast display controller (IC802)

15

NCO

O

16

NCO

O

Not used (open)

17

NCO

O

18

D0

I/O

19

D1

I/O

20

D2

I/O

21

D3

I/O

22

VSS

—

Ground terminal

23

D4

I/O

24

D5

I/O

25

D6

I/O

26

D7

I/O

27

D8

I/O

28

D9

I/O

29

D10

I/O

30

D11

I/O

31

D12

I/O

32

D13

I/O

33

D14

I/O

34

D15

I/O

35

VCC

—

Power supply terminal (+5V)

36

A0

O

Address signal output terminal    This set uses this as a control signal to the LCD controller for
liquid crystal module

37

A1

O

38

A2

O

Address signal output to the flash memory (IC931) and S-RAM (IC932)

39

A3

O

Output of command transmission start control signal to the LCD controller for liquid crystal
module    The OR signal with the busy signal from LCD controller for liquid crystal module is
input to the LCD-BUSY (pin 9)

At the start of command transmission, the signal changes like “L”

®“H”®“L” so as to be a

start trigger for the LCD controller = DMA controller

Two-way data bus with the flash memory (IC931), S-RAM (IC932), and LCD controller for
liquid crystal module

Two-way data bus with the flash memory (IC931) and S-RAM (IC932)

Two-way data bus with the flash memory (IC931) and S-RAM (IC932)