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– 61 –

Pin No.

Pin Name

I/O

Function

40

A4

O

41

A5

O

42

A6

O

43

A7

O

44

VSS

—

Ground terminal

45

A8

O

46

A9

O

47

A10

O

48

A11

O

49

A12

O

50

A13

O

51

A14

O

52

A15

O

53

A16

O

54

A17

O

55

A18

O

56

A19

O

57

VSS

—

Ground terminal

58

NIH

I

Not used (fixed at “H”)

59

NCO

O

Not used (open)

60

NCO

O

Not used (open)

61

Ø

O

System clock output terminal    Not used (open)

62

STBY

I

Hardware standby signal input terminal (fixed at “H”)

63

RES

I

Reset signal input from the display controller (IC802)    “L”: reset

64

BU-IN

I

Not used (fixed at “H”)

65

VSS

—

Ground terminal

66

EXTAL

I

System clock input terminal (14.745 MHz)

67

XTAL

I

System clock input terminal (14.745 MHz)

68

VCC

—

Power supply terminal (+5V)

69

AS

O

Address strobe signal output terminal    Not used (open)

70

RD

O

Data reading strobe signal output to the flash memory (IC931) and S-RAM (IC932)

71

HWR

O

Also, this is used as strobe signal output for data writing to the flash memory (IC931), strobe
signal output for higher byte data writing to the S-RAM (IC932), or latch signal to the LCD
controller for liquid crystal module

72

LWR

O

Also, this is used as strobe signal output for data writing to the flash memory (IC931), strobe
signal output for lower byte data writing to the S-RAM (IC932), or latch signal to the LCD
controller for liquid crystal module

73

MD0

I

Input terminal for setting microcomputer operation mode (fixed at “L”)

74

MD1

I

Input terminal for setting microcomputer operation mode (fixed at “H”)

75

MD2

I

Input terminal for setting microcomputer operation mode (fixed at “H”)

76

AVDD

—

Power supply terminal (+5V) (for A/D conversion)

77

AVREF

I

Reference voltage input terminal (+5V) (for A/D conversion)

78

NIL

I

79

NIL

I

80

NIL

I

81

NIL

I

Address signal output to the flash memory (IC931) and S-RAM (IC932)

Address signal output to the flash memory (IC931) and S-RAM (IC932)

Not used (fixed at “L”)

– 62 –

Pin No.

Pin Name

I/O

Function

82

NIL

I

83

NIL

I

84

CONTR

O

Contrast alignment signal output to the liquid crystal module (D/A output)

85

DIMER

O

Back light brightness control signal output to the liquid crystal module (D/A output)

86

AVSS

—

Ground terminal (for A/D conversion)

87

NCO

O

Not used (open)

88

SRAM-CS

O

Chip enable signal output to the S-RAM (IC932)

89

NIL

I

Not used (fixed at “L”)

90

ROM-CS

O

Chip enable signal output to the flash memory (IC931)

91

BOOT

I

Not used (fixed at “H”)

92

VSS

—

Ground terminal

93

NCO

O

Not used (open)

94

NCO

O

Not used (open)

95

LCD RST

O

Reset signal output terminal    “H”: reset    Not used (open)

96

NCO

O

Not used (open)

97

BEEP

O

Beep sound drive signal output terminal

98

NCO

O

Not used (open)

99

LCD-CS

O

100

A20

O

Address signal output terminal    Not used (open)

Output of chip enable signal to the LCD controller for liquid crystal module The OR signal
with HWR (pin &¡) is used as a latch signal to the LCD controller for liquid crystal module
“L” is output at the LCD controller data transmission

Not used (fixed at “L”)

– 63 –

Pin No.

Pin Name

I/O

Function

1

LED

O

LED drive signal output for the eject indicator    “L”: LED on

2

—

O

Not used (open)

3

—

O

Not used (open)

4

EECLK

O

Serial data transfer clock signal output to the EEPROM (IC302)

5

SINGLE

I

Input terminal for setting CD single mode or CD changer mode
“L”: CD single mode, “H”: CD changer mode (fixed at “H”)

6

MC

O

Elevator up/down motor (M501) and disc load/save motor (M502) drive signal output to the
BA6247FP (IC201)    *1

7

MB

O

Elevator up/down motor (M501) drive signal output to the BA6247FP (IC201)    *1

8

MA

O

Disc load/save motor (M502) drive signal output to the BA6247FP (IC201)    *1

9

PGR

O

Plunger drive signal output for the magazine out

10

M3

O

Disc eject motor (M801) drive signal output to the BA6287F (IC801)

11

M3

O

Disc eject motor (M801) drive signal output to the BA6287F (IC801)

12

ELVON

O

Output of power on/off control signal for the CD section main power supply    “H”: power on

13

CDRST

O

Reset signal output to the D-RAM controller (IC401), digital signal processor (IC501), and
digital servo processor (IC601)    “L”: reset

14

XTLSEL

O

Output terminal for setting DSP crystal    “H”: internal clock, “L”: external clock
Not used (open)

15

APC

O

Laser diode on/off control signal output to the RF amplifier (IC101)    “L”: laser on

16

DPT

I

Detection input from the disc detect sensor (Q702)      Whether a disc is present at the reset
processing or load/save processing is detected (“L” is input while a disc is fed)

17

DOE

I

Detection input from the disc detect sensor (Q701)     Whether a disc is present at the reset
processing or load processing is detected (“L” is input when a disc is above the pickup)

18

CES

I

Detection input from the disc chucking completion detect switch (SW701)
“L” is input when disc chucking is completed

19

HOME

I

Detection input from the home/top position detect switch (SW501)
“L” is input when elevator is at the home position

20

PST

I

Detection input from the magazine detect switch (SW804)    “L”: magazine in

21

LOT

I

Detection input from the liner slide lever position detect switch (SW803)    “L”: magazine in

22

XWRE

O

Enable signal output for data writing to the D-RAM controller (IC401)

23

XRDE

O

Enable signal output for data reading to the D-RAM controller (IC401)

24

XQOK

O

Output of definite subcode Q data to the D-RAM controller (IC401)

25

GRSRST

O

Reset signal output to the D-RAM controller (IC401)    At track jump, “H” is output

26

ESPXLT

O

Serial latch signal output to the D-RAM controller (IC401)

27

XSOE

O

Enable signal output for data reading to the D-RAM controller (IC401)

28

SDTI

I

Serial data input from the D-RAM controller (IC401)

29

—

O

Not used (open)

30

RESET

I

System reset signal input from the reset signal generator (IC903) and bus interface (IC951) (for
SONY bus)    “L”: reset    For several hundreds msec. after the power supply rises, “L” is input,
then it changes to “H”

31

XTLI

I

Main system clock input terminal (8 MHz)

32

XTLO

O

Main system clock output terminal (8 MHz)

33

VSS

—

Ground terminal

34

TX

O

Sub system clock output terminal (32.768 kHz)    Not used (open)

35

TEX

I

Sub system clock input terminal (32.768 kHz)    Not used (fixed at “L”)

– 64 –

Pin No.

Pin Name

I/O

Function

36

AVSS

—

Ground terminal (for A/D conversion)

37

AVREF

I

Reference voltage input terminal (+5V) (for A/D conversion)

38

TEMP H

I

Temperature detect thermistor (TH301) input terminal (A/D input)
Used for high temperature detection data input (for servo gain compensation)

39

TEMP L

I

Temperature detect thermistor (TH302) input terminal (A/D input)
Used for low temperature detection data input (for servo gain compensation)

40

SEL

O

Not used (open)

41

TEMP D

I

Input of temperature compensation inhibit    “L”: inhibit    (fixed at “H”)

42

—

O

Not used (open)

43

RSTO

O

Reset signal output to the CD text decoder (IC303)    “L”: reset

44

BUSY

I

Busy signal input from the CD text decoder (IC303)

45

REQ

I

Request signal input from the CD text decoder (IC303)

46

GRSCOR

I

Subcode sync detection signal input from the D-RAM controller (IC401)

47

EEDATA

I/O

Two-way data bus with the EEPROM (IC302)

48

CCLK

O

Serial data transfer clock signal output to the CD text decoder (IC303)

49

CSO

O

Serial data output to the CD text decoder (IC303)

50

CSI

I

Serial data input from the CD text decoder (IC303)

51

SCK

I

Serial data transfer clock signal input from the bus interface (IC951) (for SONY bus)

52

SI

I

Serial data input from the bus interface (IC951) (for SONY bus)

53

SO

O

Serial data output to the bus interface (IC951) (for SONY bus)

54

BUSON

I

Bus on/off control signal input from the bus interface (IC951) (for SONY bus)
“L”: bus on (used also to reset standby)

55

EJTKEY

I

Eject switch (SW11) input terminal

56

SCOR

I

Subcode sync (S0+S1) detection signal input from the digital signal processor (IC501)

57

EEINIT

I

Initial reset input of the EEPROM    “L”: initial reset (fixed at “L”)

58

—

O

Not used (open)

59

—

O

Not used (open)

60

WUP

I

Key wake-up input terminal    In this set, the signal from EJECT switch (SW11) and bus on
signal from the bus interface (IC951) (for SONY bus) are input

61

LOCK

I

Detection input from the magazine lock detect switch (SW802)    “H”: magazine lock

62

EHS

I

Elevator height detection signal input terminal

63

OPEN

I

Detection input from the door open/close detect switch (SW12)
“H”: door open, “L”: door close

64

B.U.CHECK

I

Backup power supply detection signal input terminal (used also to reset standby)

65

SQCK

O

Clock signal output for subcode Q data reading to the digital signal processor (IC501)

66

SUBQ

I

Subcode Q data input from the digital signal processor (IC501)

67

—

O

Not used (open)

68

CDCLK

O

Serial data transfer clock signal output to the D-RAM controller (IC401) and digital signal
processor (IC501)

69

CDXLT

O

Serial latch signal output to the digital signal processor (IC501)

70

CDDATA

O

Serial data output to the D-RAM controller (IC401) and digital signal processor (IC501)

71

SCLK

O

Clock signal output for SENS serial data reading to the digital servo processor (IC601)

72

VDD

—

Power supply terminal (+5V)

73

NC

I

Not used (fixed at “H”)

74

A-MUTE

O

Audio mute on/off control signal output terminal    “H”: mute    Not used (open)

75

FOK

I

Focus OK signal input from the digital servo processor (IC601)    “L”: NG, “H”: OK